288 lines
8.8 KiB
VHDL
Executable File
288 lines
8.8 KiB
VHDL
Executable File
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--
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-- Copyright (C) 2009, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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entity threephasepwm is
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port (
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clk: in std_logic;
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hclk: in std_logic;
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refcount: in std_logic_vector (10 downto 0);
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ibus: in std_logic_vector (31 downto 0);
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obus: out std_logic_vector (31 downto 0);
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loadpwmreg: in std_logic;
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loadenareg: in std_logic;
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readenareg: in std_logic;
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loaddzreg: in std_logic;
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pwmouta: out std_logic;
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pwmoutb: out std_logic;
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pwmoutc: out std_logic;
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npwmouta: out std_logic;
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npwmoutb: out std_logic;
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npwmoutc: out std_logic;
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pwmenaout: out std_logic;
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pwmfault: in std_logic;
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pwmsample: out std_logic
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);
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end threephasepwm;
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architecture behavioral of threephasepwm is
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constant buswidth : integer := 32;
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signal pwmval: std_logic_vector (BusWidth -1 downto 0);
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alias pwmaval: std_logic_vector(9 downto 0) is pwmval(9 downto 0);
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alias pwmbval: std_logic_vector(9 downto 0) is pwmval(19 downto 10);
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alias pwmcval: std_logic_vector(9 downto 0) is pwmval(29 downto 20);
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signal pwma: std_logic;
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signal pwmb: std_logic;
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signal pwmc: std_logic;
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signal npwma: std_logic;
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signal npwmb: std_logic;
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signal npwmc: std_logic;
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signal prepwmval: std_logic_vector (BusWidth -1 downto 0);
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signal preenareg: std_logic_vector(1 downto 0);
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signal enareg: std_logic_vector(1 downto 0);
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alias pwmena: std_logic is enareg(0);
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alias pwmfltflg: std_logic is enareg(1);
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signal fltcnt: std_logic_vector(2 downto 0);
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signal predzreg: std_logic_vector(31 downto 0);
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signal dzreg: std_logic_vector(31 downto 0);
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alias dzval: std_logic_vector(8 downto 0) is dzreg (8 downto 0);
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alias sampleval : std_logic_vector(10 downto 0) is dzreg(26 downto 16);
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alias fltpol: std_logic is dzreg(15);
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signal loadpwmreq: std_logic;
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signal oldloadpwmreq: std_logic;
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signal olderloadpwmreq: std_logic;
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signal loadenareq: std_logic;
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signal oldloadenareq: std_logic;
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signal olderloadenareq: std_logic;
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signal loaddzreq: std_logic;
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signal oldloaddzreq: std_logic;
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signal olderloaddzreq: std_logic;
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signal cyclestart: std_logic;
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signal oldrefcount10: std_logic;
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signal samplereq : std_logic;
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signal dsamplereq : std_logic_vector(1 downto 0);
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signal pwmsamplet : std_logic;
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signal fixedrefcount: std_logic_vector(9 downto 0);
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begin
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hspwm: process (hclk,refcount(10),oldrefcount10)
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begin
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if rising_edge(hclk) then
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if ((pwmfault xor fltpol) = '0') and (fltcnt < "111") then -- ~70 ns filter
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fltcnt <= fltcnt + 1; -- on fault input
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end if;
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if ((pwmfault xor fltpol) = '1') and (fltcnt /= 0) then
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fltcnt <= fltcnt -1;
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end if;
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if fltcnt = "111" then -- on fault, disable outputs
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pwmena <= '0';
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pwmfltflg <= '1';
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end if;
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if oldloadpwmreq = '1' and olderloadpwmreq = '1' then
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pwmval <= prepwmval;
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oldloadpwmreq <= '0';
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end if;
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if oldloaddzreq = '1' and olderloaddzreq = '1' then
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dzreg <= predzreg;
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oldloaddzreq <= '0';
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end if;
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if oldloadenareq = '1' and olderloadenareq ='1' then
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enareg <= preenareg;
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end if;
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olderloadpwmreq <= oldloadpwmreq;
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olderloadenareq <= oldloadenareq;
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olderloaddzreq <= oldloaddzreq;
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if (loadpwmreq and cyclestart) = '1' then
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oldloadpwmreq <= '1';
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end if;
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if (loaddzreq and cyclestart) = '1' then
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oldloaddzreq <= '1';
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end if;
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oldloadenareq <= loadenareq;
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oldrefcount10 <= refcount(10);
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-- was combinatorial but now pipelined to meet 100 MHz timing
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if (UNSIGNED('0'&fixedrefcount) < UNSIGNED('0'&pwmaval -dzval)) then
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pwma <= '1';
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else
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pwma <= '0';
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end if;
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if (UNSIGNED('0'&fixedrefcount) < UNSIGNED('0'&pwmaval +dzval)) then
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npwma <= '1';
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else
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npwma <= '0';
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end if;
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if (UNSIGNED('0'&fixedrefcount) < UNSIGNED('0'&pwmbval -dzval)) then
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pwmb <= '1';
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else
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pwmb <= '0';
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end if;
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if (UNSIGNED('0'&fixedrefcount) < UNSIGNED('0'&pwmbval +dzval)) then
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npwmb <= '1';
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else
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npwmb <= '0';
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end if;
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if (UNSIGNED('0'&fixedrefcount) < UNSIGNED('0'&pwmcval -dzval)) then
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pwmc <= '1';
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else
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pwmc <= '0';
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end if;
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if (UNSIGNED('0'&fixedrefcount) < UNSIGNED('0'&pwmcval +dzval)) then
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npwmc <= '1';
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else
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npwmc <= '0';
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end if;
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if refcount = SampleVal then
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samplereq <= '1';
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end if;
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if refcount(10) = '0' then -- always symmetrical (triangle) mode
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fixedrefcount <= refcount(9 downto 0); -- up
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else
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fixedrefcount <= (not refcount(9 downto 0)); -- down
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end if;
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end if; -- hclk
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if dsamplereq = "11" then
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samplereq <= '0';
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end if;
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cyclestart <= not refcount(10) and oldrefcount10; -- falling edge of refcount msb
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end process hspwm;
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lspwm: process(clk,olderloadpwmreq, olderloadenareq, olderloaddzreq,
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pwma, enareg, pwmb, pwmc, npwma, npwmb, npwmc)
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begin
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if rising_edge(clk) then -- 33/48/50 mhz local bus clock
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if loadpwmreg = '1' then
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prepwmval <= ibus;
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loadpwmreq <= '1';
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end if;
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if loadenareg = '1' then
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preenareg <= ibus(1 downto 0);
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loadenareq <= '1';
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end if;
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if loaddzreg = '1' then
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predzreg <= ibus(31 downto 0);
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loaddzreq <= '1';
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end if;
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dsamplereq <= dsamplereq(0) & samplereq;
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if dsamplereq = "10" then
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pwmsamplet <= '1';
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else
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pwmsamplet <= '0';
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end if;
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end if; -- clk
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obus <= (others => 'Z');
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if readenareg = '1' then
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obus(1 downto 0) <= enareg;
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end if;
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if olderloadpwmreq = '1' then -- asynchronous request clear, could use flancter but dont need async clear
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loadpwmreq <= '0';
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end if;
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if olderloadenareq = '1' then -- asynchronous request clear ""
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loadenareq <= '0';
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end if;
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if olderloaddzreq = '1' then -- asynchronous request clear ""
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loaddzreq <= '0';
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end if;
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pwmouta <= pwma and pwmena;
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pwmoutb <= pwmb and pwmena;
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pwmoutc <= pwmc and pwmena;
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npwmouta <= (not npwma) and pwmena;
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npwmoutb <= (not npwmb) and pwmena;
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npwmoutc <= (not npwmc) and pwmena;
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pwmenaout <= not pwmena;
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pwmsample <= pwmsamplet;
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end process lspwm;
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end behavioral;
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