303 lines
13 KiB
VHDL
Executable File
303 lines
13 KiB
VHDL
Executable File
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--
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-- Copyright (C) 2009, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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use work.IDROMConst.all;
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entity IDROM is
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generic (
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idromtype : integer;
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offsettomodules : integer;
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offsettopindesc : integer;
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boardnamelow : std_logic_vector(31 downto 0);
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boardnamehigh : std_logic_vector(31 downto 0);
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fpgasize : integer;
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fpgapins : integer;
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ioports : integer;
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iowidth : integer;
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portwidth : integer;
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clocklow : integer;
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clockhigh : integer;
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inststride0 : integer;
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inststride1 : integer;
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regstride0 : integer;
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regstride1 : integer;
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pindesc : PinDescType;
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moduleid : moduleIDType );
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port (
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clk : in std_logic;
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we : in std_logic;
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re : in std_logic;
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radd : in std_logic_vector(7 downto 0);
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wadd : in std_logic_vector(7 downto 0);
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din : in std_logic_vector(31 downto 0);
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dout : out std_logic_vector(31 downto 0)
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);
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end IDROM;
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architecture syn of IDROM is -- 256 x 32 spram
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constant empty : std_logic_vector(31 downto 0) := x"00000000";
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type ram_type is array (0 to 255) of std_logic_vector(31 downto 0);
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signal RAM : ram_type :=
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(
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CONV_STD_LOGIC_VECTOR(idromtype,32),
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CONV_STD_LOGIC_VECTOR(offsettomodules,32),
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CONV_STD_LOGIC_VECTOR(offsettopindesc,32),
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boardnamelow,
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boardnamehigh,
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CONV_STD_LOGIC_VECTOR(fpgasize,32),
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CONV_STD_LOGIC_VECTOR(fpgapins,32),
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CONV_STD_LOGIC_VECTOR(ioports,32),
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CONV_STD_LOGIC_VECTOR(iowidth,32),
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CONV_STD_LOGIC_VECTOR(portwidth,32),
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CONV_STD_LOGIC_VECTOR(clocklow,32),
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CONV_STD_LOGIC_VECTOR(clockhigh,32),
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CONV_STD_LOGIC_VECTOR(inststride0,32),
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CONV_STD_LOGIC_VECTOR(inststride1,32),
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CONV_STD_LOGIC_VECTOR(regstride0,32),
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CONV_STD_LOGIC_VECTOR(regstride1,32),
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-- module IDs starting at doubleword 16
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-- 32 module id records = 96 doubles total
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moduleid(0).NumInstances&moduleid(0).Clock&moduleid(0).Version&moduleid(0).GTag,
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moduleid(0).Strides&moduleid(0).NumRegisters&moduleid(0).BaseAddr,
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moduleid(0).MultRegs,
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moduleid(1).NumInstances&moduleid(1).Clock&moduleid(1).Version&moduleid(1).GTag,
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moduleid(1).Strides&moduleid(1).NumRegisters&moduleid(1).BaseAddr,
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moduleid(1).MultRegs,
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moduleid(2).NumInstances&moduleid(2).Clock&moduleid(2).Version&moduleid(2).GTag,
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moduleid(2).Strides&moduleid(2).NumRegisters&moduleid(2).BaseAddr,
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moduleid(2).MultRegs,
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moduleid(3).NumInstances&moduleid(3).Clock&moduleid(3).Version&moduleid(3).GTag,
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moduleid(3).Strides&moduleid(3).NumRegisters&moduleid(3).BaseAddr,
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moduleid(3).MultRegs,
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moduleid(4).NumInstances&moduleid(4).Clock&moduleid(4).Version&moduleid(4).GTag,
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moduleid(4).Strides&moduleid(4).NumRegisters&moduleid(4).BaseAddr,
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moduleid(4).MultRegs,
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moduleid(5).NumInstances&moduleid(5).Clock&moduleid(5).Version&moduleid(5).GTag,
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moduleid(5).Strides&moduleid(5).NumRegisters&moduleid(5).BaseAddr,
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moduleid(5).MultRegs,
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moduleid(6).NumInstances&moduleid(6).Clock&moduleid(6).Version&moduleid(6).GTag,
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moduleid(6).Strides&moduleid(6).NumRegisters&moduleid(6).BaseAddr,
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moduleid(6).MultRegs,
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moduleid(7).NumInstances&moduleid(7).Clock&moduleid(7).Version&moduleid(7).GTag,
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moduleid(7).Strides&moduleid(7).NumRegisters&moduleid(7).BaseAddr,
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moduleid(7).MultRegs,
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moduleid(8).NumInstances&moduleid(8).Clock&moduleid(8).Version&moduleid(8).GTag,
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moduleid(8).Strides&moduleid(8).NumRegisters&moduleid(8).BaseAddr,
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moduleid(8).MultRegs,
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moduleid(9).NumInstances&moduleid(9).Clock&moduleid(9).Version&moduleid(9).GTag,
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moduleid(9).Strides&moduleid(9).NumRegisters&moduleid(9).BaseAddr,
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moduleid(9).MultRegs,
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moduleid(10).NumInstances&moduleid(10).Clock&moduleid(10).Version&moduleid(10).GTag,
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moduleid(10).Strides&moduleid(10).NumRegisters&moduleid(10).BaseAddr,
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moduleid(10).MultRegs,
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moduleid(11).NumInstances&moduleid(11).Clock&moduleid(11).Version&moduleid(11).GTag,
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moduleid(11).Strides&moduleid(11).NumRegisters&moduleid(11).BaseAddr,
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moduleid(11).MultRegs,
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moduleid(12).NumInstances&moduleid(12).Clock&moduleid(12).Version&moduleid(12).GTag,
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moduleid(12).Strides&moduleid(12).NumRegisters&moduleid(12).BaseAddr,
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moduleid(12).MultRegs,
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moduleid(13).NumInstances&moduleid(13).Clock&moduleid(13).Version&moduleid(13).GTag,
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moduleid(13).Strides&moduleid(13).NumRegisters&moduleid(13).BaseAddr,
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moduleid(13).MultRegs,
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moduleid(14).NumInstances&moduleid(14).Clock&moduleid(14).Version&moduleid(14).GTag,
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moduleid(14).Strides&moduleid(14).NumRegisters&moduleid(14).BaseAddr,
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moduleid(14).MultRegs,
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moduleid(15).NumInstances&moduleid(15).Clock&moduleid(15).Version&moduleid(15).GTag,
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moduleid(15).Strides&moduleid(15).NumRegisters&moduleid(15).BaseAddr,
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moduleid(15).MultRegs,
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moduleid(16).NumInstances&moduleid(16).Clock&moduleid(16).Version&moduleid(16).GTag,
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moduleid(16).Strides&moduleid(16).NumRegisters&moduleid(16).BaseAddr,
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moduleid(16).MultRegs,
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moduleid(17).NumInstances&moduleid(17).Clock&moduleid(17).Version&moduleid(17).GTag,
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moduleid(17).Strides&moduleid(17).NumRegisters&moduleid(17).BaseAddr,
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moduleid(17).MultRegs,
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moduleid(18).NumInstances&moduleid(18).Clock&moduleid(18).Version&moduleid(18).GTag,
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moduleid(18).Strides&moduleid(18).NumRegisters&moduleid(18).BaseAddr,
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moduleid(18).MultRegs,
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moduleid(19).NumInstances&moduleid(19).Clock&moduleid(19).Version&moduleid(19).GTag,
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moduleid(19).Strides&moduleid(19).NumRegisters&moduleid(19).BaseAddr,
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moduleid(19).MultRegs,
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moduleid(20).NumInstances&moduleid(20).Clock&moduleid(20).Version&moduleid(20).GTag,
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moduleid(20).Strides&moduleid(20).NumRegisters&moduleid(20).BaseAddr,
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moduleid(20).MultRegs,
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moduleid(21).NumInstances&moduleid(21).Clock&moduleid(21).Version&moduleid(21).GTag,
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moduleid(21).Strides&moduleid(21).NumRegisters&moduleid(21).BaseAddr,
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moduleid(21).MultRegs,
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moduleid(22).NumInstances&moduleid(22).Clock&moduleid(22).Version&moduleid(22).GTag,
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moduleid(22).Strides&moduleid(22).NumRegisters&moduleid(22).BaseAddr,
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moduleid(22).MultRegs,
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moduleid(23).NumInstances&moduleid(23).Clock&moduleid(23).Version&moduleid(23).GTag,
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moduleid(23).Strides&moduleid(23).NumRegisters&moduleid(23).BaseAddr,
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moduleid(23).MultRegs,
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moduleid(24).NumInstances&moduleid(24).Clock&moduleid(24).Version&moduleid(24).GTag,
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moduleid(24).Strides&moduleid(24).NumRegisters&moduleid(24).BaseAddr,
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moduleid(24).MultRegs,
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moduleid(25).NumInstances&moduleid(25).Clock&moduleid(25).Version&moduleid(25).GTag,
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moduleid(25).Strides&moduleid(25).NumRegisters&moduleid(25).BaseAddr,
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moduleid(25).MultRegs,
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moduleid(26).NumInstances&moduleid(26).Clock&moduleid(26).Version&moduleid(26).GTag,
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moduleid(26).Strides&moduleid(26).NumRegisters&moduleid(26).BaseAddr,
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moduleid(26).MultRegs,
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moduleid(27).NumInstances&moduleid(27).Clock&moduleid(27).Version&moduleid(27).GTag,
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moduleid(27).Strides&moduleid(27).NumRegisters&moduleid(27).BaseAddr,
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moduleid(27).MultRegs,
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moduleid(28).NumInstances&moduleid(28).Clock&moduleid(28).Version&moduleid(28).GTag,
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moduleid(28).Strides&moduleid(28).NumRegisters&moduleid(28).BaseAddr,
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moduleid(28).MultRegs,
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moduleid(29).NumInstances&moduleid(29).Clock&moduleid(29).Version&moduleid(29).GTag,
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moduleid(29).Strides&moduleid(29).NumRegisters&moduleid(29).BaseAddr,
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moduleid(29).MultRegs,
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moduleid(30).NumInstances&moduleid(30).Clock&moduleid(30).Version&moduleid(30).GTag,
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moduleid(30).Strides&moduleid(30).NumRegisters&moduleid(30).BaseAddr,
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moduleid(30).MultRegs,
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moduleid(31).NumInstances&moduleid(31).Clock&moduleid(31).Version&moduleid(31).GTag,
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moduleid(31).Strides&moduleid(31).NumRegisters&moduleid(31).BaseAddr,
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moduleid(31).MultRegs,
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pindesc(0),pindesc(1),pindesc(2),pindesc(3),pindesc(4),pindesc(5),pindesc(6),pindesc(7),
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pindesc(8),pindesc(9),pindesc(10),pindesc(11),pindesc(12),pindesc(13),pindesc(14),pindesc(15),
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pindesc(16),pindesc(17),pindesc(18),pindesc(19),pindesc(20),pindesc(21),pindesc(22),pindesc(23),
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pindesc(24),pindesc(25),pindesc(26),pindesc(27),pindesc(28),pindesc(29),pindesc(30),pindesc(31),
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pindesc(32),pindesc(33),pindesc(34),pindesc(35),pindesc(36),pindesc(37),pindesc(38),pindesc(39),
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pindesc(40),pindesc(41),pindesc(42),pindesc(43),pindesc(44),pindesc(45),pindesc(46),pindesc(47),
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pindesc(48),pindesc(49),pindesc(50),pindesc(51),pindesc(52),pindesc(53),pindesc(54),pindesc(55),
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pindesc(56),pindesc(57),pindesc(58),pindesc(59),pindesc(60),pindesc(61),pindesc(62),pindesc(63),
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pindesc(64),pindesc(65),pindesc(66),pindesc(67),pindesc(68),pindesc(69),pindesc(70),pindesc(71),
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pindesc(72),pindesc(73),pindesc(74),pindesc(75),pindesc(76),pindesc(77),pindesc(78),pindesc(79),
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pindesc(80),pindesc(81),pindesc(82),pindesc(83),pindesc(84),pindesc(85),pindesc(86),pindesc(87),
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pindesc(88),pindesc(89),pindesc(90),pindesc(91),pindesc(92),pindesc(93),pindesc(94),pindesc(95),
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pindesc(96),pindesc(97),pindesc(98),pindesc(99),pindesc(100),pindesc(101),pindesc(102),pindesc(103),
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pindesc(104),pindesc(105),pindesc(106),pindesc(107),pindesc(108),pindesc(109),pindesc(110),pindesc(111),
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pindesc(112),pindesc(113),pindesc(114),pindesc(115),pindesc(116),pindesc(117),pindesc(118),pindesc(119),
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pindesc(120),pindesc(121),pindesc(122),pindesc(123),pindesc(124),pindesc(124),pindesc(126),pindesc(127),
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pindesc(128),pindesc(129),pindesc(130),pindesc(131),pindesc(132),pindesc(133),pindesc(134),pindesc(135),
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pindesc(136),pindesc(137),pindesc(138),pindesc(139),pindesc(140),pindesc(141),pindesc(142),pindesc(143)
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);
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signal dradd : std_logic_vector(7 downto 0);
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signal readout : std_logic_vector(31 downto 0);
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begin
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process (clk,RAM, re,dradd,readout)
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begin
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if (clk'event and clk = '1') then
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if (we = '1') then
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RAM(conv_integer(wadd)) <= din;
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end if;
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dradd <= radd;
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end if;
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readout <= RAM(conv_integer(dradd));
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dout <= (others => 'Z');
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if re = '1' then
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dout <= readout;
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end if;
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end process;
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end;
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