169 lines
5.7 KiB
VHDL
Executable File
169 lines
5.7 KiB
VHDL
Executable File
library IEEE;
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use IEEE.std_logic_1164.ALL;
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use IEEE.std_logic_ARITH.ALL;
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use IEEE.std_logic_UNSIGNED.ALL;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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entity pwmrefh is
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generic (
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buswidth : integer;
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refwidth : integer
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);
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Port (
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clk: in std_logic;
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hclk: in std_logic;
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refcount: out std_logic_vector (refwidth-1 downto 0);
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ibus: in std_logic_vector (buswidth -1 downto 0);
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pdmrate: out std_logic;
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pwmrateload: in std_logic;
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pdmrateload: in std_logic
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);
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end pwmrefh;
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architecture behavioral of pwmrefh is
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signal count: std_logic_vector (refwidth -1 downto 0);
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signal pwmrateacc: std_logic_vector (16 downto 0);
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alias pwmratemsb: std_logic is pwmrateacc(16);
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signal oldpwmratemsb: std_logic;
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signal pwmratelatch: std_logic_vector (15 downto 0);
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signal prepwmratelatch: std_logic_vector (15 downto 0);
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signal pwmratelatchloadreq: std_logic;
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signal oldpwmratelatchloadreq: std_logic;
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signal olderpwmratelatchloadreq: std_logic;
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signal pdmrateacc: std_logic_vector (16 downto 0);
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alias pdmratemsb: std_logic is pdmrateacc(16);
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signal oldpdmratemsb: std_logic;
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signal pdmratelatch: std_logic_vector (15 downto 0);
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signal prepdmratelatch: std_logic_vector (15 downto 0);
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signal pdmratelatchloadreq: std_logic;
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signal oldpdmratelatchloadreq: std_logic;
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signal olderpdmratelatchloadreq: std_logic;
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signal prate: std_logic;
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begin
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apwmref: process (clk,
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olderpwmratelatchloadreq,
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olderpdmratelatchloadreq,
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prate,
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hclk,
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count,
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ibus)
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begin
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if rising_edge(hclk) then -- 100 Mhz high speed clock
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if oldpwmratelatchloadreq = '1' and olderpwmratelatchloadreq = '1' then
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pwmratelatch <= prepwmratelatch;
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end if;
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oldpwmratelatchloadreq <= pwmratelatchloadreq;
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olderpwmratelatchloadreq <= oldpwmratelatchloadreq;
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pwmrateacc <= pwmrateacc + pwmratelatch;
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oldpwmratemsb <= pwmratemsb;
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if oldpwmratemsb /= pwmratemsb then
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count <= count + 1;
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end if; -- old /= new
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if oldpdmratelatchloadreq = '1' and olderpdmratelatchloadreq = '1' then
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pdmratelatch <= prepdmratelatch;
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end if;
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oldpdmratelatchloadreq <= pdmratelatchloadreq;
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olderpdmratelatchloadreq <= oldpdmratelatchloadreq;
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pdmrateacc <= pdmrateacc + pdmratelatch;
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oldpdmratemsb <= pdmratemsb;
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if oldpdmratemsb /= pdmratemsb then
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prate <= '1';
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else
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prate <= '0';
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end if; -- old /= new
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end if; -- hclk
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if rising_edge(clk) then -- 33/48/50 Mhz local bus clock
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if pwmrateload = '1' then
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prepwmratelatch <= ibus;
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pwmratelatchloadreq <= '1';
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end if;
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if pdmrateload = '1' then
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prepdmratelatch <= ibus;
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pdmratelatchloadreq <= '1';
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end if;
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end if; -- clk
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if olderpwmratelatchloadreq = '1' then -- asyncronous request clear
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pwmratelatchloadreq <= '0';
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end if;
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if olderpdmratelatchloadreq = '1' then -- asyncronous request clear
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pdmratelatchloadreq <= '0';
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end if;
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refcount <= count;
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pdmrate <= prate;
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end process;
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end behavioral;
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