153 lines
5.1 KiB
VHDL
Executable File
153 lines
5.1 KiB
VHDL
Executable File
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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use ieee.math_real.all;
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--
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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entity xfrmrout is
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generic ( clock : integer;
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pins : integer);
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port ( ibus : in std_logic_vector (31 downto 0);
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obus : out std_logic_vector(31 downto 0);
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loadrate : in std_logic;
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readrate : in std_logic;
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loaddata : in std_logic;
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readdata : in std_logic;
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acout : out std_logic_vector(pins-1 downto 0);
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acref : out std_logic;
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clk : in std_logic
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);
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end xfrmrout;
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architecture Behavioral of xfrmrout is
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constant defaultdivisor : real := round((real(clock/2)/1000000.0)) -2.0; -- default driverate is 1.00 MHz
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--
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signal rate: std_logic_vector(11 downto 0) := std_logic_vector(to_unsigned(integer(defaultdivisor),12));
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signal count: std_logic_vector(11 downto 0);
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alias countmsb: std_logic is count(11);
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signal enable: std_logic := '0';
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signal toggle: std_logic;
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signal preacout: std_logic;
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signal preacoutd: std_logic;
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signal datareg: std_logic_vector(pins-1 downto 0);
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begin
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arate: process (clk,count,readrate,rate,enable,readdata,datareg,
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preacoutd,preacout)
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begin
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report("Xfrmr rate divisor: "& real'image(defaultdivisor));
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report("Xfrmr pins: "& integer'image(pins));
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if rising_edge(clk) then
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if countmsb= '0' then
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count <= count -1;
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else
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count <= rate;
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toggle <= not toggle;
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end if;
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if loadrate = '1' then
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rate <= ibus(11 downto 0);
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enable <= ibus(12);
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end if;
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if enable = '1' then
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preacout <= toggle;
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else
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preacout <= '0';
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end if;
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if loaddata = '1' then
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datareg <= ibus(pins-1 downto 0);
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end if;
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end if;
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if falling_edge(clk) then
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preacoutd <= preacout;
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end if;
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obus <= (others => 'Z');
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if readrate = '1' then
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obus(11 downto 0) <= rate;
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obus(12) <= enable;
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obus(31 downto 13) <= (others => '0');
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end if;
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if readdata = '1' then
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obus(pins-1 downto 0) <= datareg;
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obus(31 downto pins) <= (others => '0');
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end if;
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for i in 0 to pins-1 loop
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acout(i) <= preacoutd xor datareg(i);
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end loop;
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acref <= preacout;
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end process;
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end Behavioral;
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