23 lines
654 B
VHDL
Executable File
23 lines
654 B
VHDL
Executable File
-- from Altera forum
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_unsigned.all;
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use ieee.math_real.all;
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package str_to_slv is -- convert string of 8 bit bytes to slv
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function str_to_slv(str : string) return std_logic_vector;
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end str_to_slv;
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package body str_to_slv is
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function str_to_slv( str : string ) return std_logic_vector is
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variable slv : std_logic_vector( str'length * 8 - 1 downto 0) ;
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begin
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for i in 1 to str'high loop
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slv(i * 8 - 1 downto (i - 1) * 8) := std_logic_vector(to_unsigned( character'pos(str(i)),8)) ;
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end loop ;
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return slv ;
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end function ;
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end str_to_slv; |