178 lines
5.5 KiB
VHDL
Executable File
178 lines
5.5 KiB
VHDL
Executable File
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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library UNISIM;
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use UNISIM.VComponents.all;
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--
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-- Copyright (C) 2018, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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entity simpledsad is
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generic (
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buswidth: integer;
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channels: integer
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);
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port (
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clk : in std_logic;
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ibus : in std_logic_vector(buswidth-1 downto 0);
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obus : out std_logic_vector(buswidth-1 downto 0);
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a : in std_logic_vector(3 downto 0);
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readdata : in std_logic;
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loadcontrol : in std_logic;
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compin_p : in std_logic_vector(channels-1 downto 0);
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compin_n : in std_logic_vector(channels-1 downto 0);
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fbout : out std_logic_vector(channels-1 downto 0);
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pwmout : out std_logic
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);
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end simpledsad;
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architecture behavioral of simpledsad is
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-- ssi interface related signals
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signal compin: std_logic_vector(channels-1 downto 0);
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signal count: std_logic_vector(15 downto 0);
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signal bits: std_logic_vector(3 downto 0);
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signal pwmval: std_logic_vector(11 downto 0);
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signal pwmcount: std_logic_vector(11 downto 0);
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signal pwmbit: std_logic;
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signal msb: std_logic;
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signal msbd: std_logic;
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type datatype is array(channels -1 downto 0) of std_logic_vector(15 downto 0);
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signal data: datatype;
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type datalatchtype is array (channels -1 downto 0) of std_logic_vector(15 downto 0);
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signal datalatch: datalatchtype;
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signal flip: std_logic_vector(channels-1 downto 0);
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signal chanindex: integer range 0 to 15;
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begin
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ibufs: for i in 0 to channels-1 generate
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compbuf : IBUFDS
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generic map (
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DIFF_TERM => FALSE,
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IBUF_LOW_PWR => TRUE,
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IOSTANDARD => "DEFAULT")
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port map (
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O => compin(i),
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I => compin_p(i),
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IB => compin_n(i)
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);
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end generate ibufs;
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asimpledsad: process (clk,readdata,a,datalatch,flip,pwmbit)
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begin
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if rising_edge(clk) then
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pwmcount <= pwmcount+1;
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if pwmval < pwmcount then
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pwmbit <= '0';
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else
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pwmbit <= '1';
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end if;
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msbd <= msb;
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for i in 0 to 15 loop -- se bitsize
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if i=bits then
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msb <= count(i);
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end if;
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end loop;
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count <= count+1;
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for i in 0 to channels -1 loop
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flip(i) <= compin(i);
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if flip(i) = '0' then
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data(i) <= data(i)+1;
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end if;
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if msbd = '1' and msb = '0' then -- free running for now
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datalatch(i) <= data(i);
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data(i) <= (others => '0');
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end if;
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end loop;
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if loadcontrol = '1' then
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bits <= ibus(3 downto 0);
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pwmval <= ibus(15 downto 4);
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end if;
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end if; -- clk
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obus <= (others => 'Z');
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if readdata = '1' then
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for i in 0 to channels -1 loop
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if a = i then
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obus(15 downto 0) <= datalatch(conv_integer(a));
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obus(buswidth -1 downto 16) <= (others => '0');
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end if;
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end loop;
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end if;
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fbout <= flip;
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pwmout <= pwmbit;
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end process asimpledsad;
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end Behavioral;
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