266 lines
9.1 KiB
VHDL
Executable File
266 lines
9.1 KiB
VHDL
Executable File
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.NUMERIC_STD.all;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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entity hm2dpll is
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port (
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clk : in std_logic;
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ibus : in std_logic_vector (31 downto 0);
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obus : out std_logic_vector (31 downto 0);
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loadbaserate : in std_logic;
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readbaserate : in std_logic;
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loadphase : in std_logic;
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readphase : in std_logic;
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loadcontrol0 : in std_logic;
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readcontrol0 : in std_logic;
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loadcontrol1 : in std_logic;
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readcontrol1 : in std_logic;
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loadtimers12 : in std_logic;
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readtimers12 : in std_logic;
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loadtimers34 : in std_logic;
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readtimers34 : in std_logic;
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syncwrite : in std_logic;
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syncread : in std_logic;
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syncin : in std_logic;
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timerout : out std_logic_vector(3 downto 0);
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refout : out std_logic
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);
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end hm2dpll;
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architecture behavioral of hm2dpll is
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constant AccumSize: integer := 42;
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constant Ilimit: signed(23 downto 0) := x"700000";
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signal PLimit: signed(23 downto 0);
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signal Accum: signed(AccumSize-1 downto 0);
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signal Prescale : unsigned(7 downto 0);
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signal PrescaleCount : unsigned(7 downto 0);
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signal FilterPrescale : unsigned(15 downto 0);
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signal FilterPrescaleCount : unsigned(15 downto 0);
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signal Accum16: unsigned(15 downto 0);
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signal PhaseErr: signed(31 downto 0);
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alias PhaseErr23: signed(23 downto 0) is PhaseErr(31 downto 8);
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signal BaseRate: signed(31 downto 0);
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signal ITerm: signed(23 downto 0);
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signal BoundedPhaseErr: signed(23 downto 0);
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signal FilteredPhaseErr: signed(23 downto 0);
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signal DPLLCorrection: signed(23 downto 0);
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signal Timer1: unsigned(15 downto 0);
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signal Timer2: unsigned(15 downto 0);
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signal Timer3: unsigned(15 downto 0);
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signal Timer4: unsigned(15 downto 0);
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signal TimerOff1: unsigned(15 downto 0);
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signal TimerOff2: unsigned(15 downto 0);
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signal TimerOff3: unsigned(15 downto 0);
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signal TimerOff4: unsigned(15 downto 0);
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signal SyncInD: std_logic;
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signal SyncInFilter: unsigned(3 downto 0);
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signal FilteredSync: std_logic_vector(1 downto 0);
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signal TimerOutReg: std_logic_vector(3 downto 0);
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begin
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ahm2dpll : process (clk,readphase,readbaserate,readcontrol0,readcontrol1,
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syncread,readtimers12,readtimers34,Accum16,
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Accum,Timer1,Timer2,Timer3,Timer4,PreScale,PhaseErr,
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DPLLCorrection,FilterPreScale,BaseRate,TimerOutReg)
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begin
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if clk'event and clk = '1' then -- per clk stuff
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-- Simple proportional DPLL
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SyncInD <= syncin;
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if SyncInD = '1' then
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if SyncInFilter /= X"F" then
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SyncInFilter <= SyncInFilter + 1;
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end if;
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else
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if SyncInFilter /= X"0" then
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SyncInFilter <= SyncInFilter - 1;
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end if;
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end if;
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if SyncInFilter = X"F" then
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FilteredSync <= FilteredSync(0)&'1';
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end if;
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if SyncInFilter = X"0" then
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FilteredSync <= FilteredSync(0)&'0';
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end if;
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if PrescaleCount = x"01" then
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PrescaleCount <= PreScale;
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Accum <= Accum + (x"00"&BaseRate) -DPLLCorrection;
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if PhaseErr23 > Plimit then
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BoundedPhaseErr <= Plimit;
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elsif PhaseErr23 < -Plimit then
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BoundedPhaseErr <= -Plimit;
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else
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BoundedPhaseErr <= PhaseErr23;
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end if;
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if FilterPrescaleCount = x"01" then
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FilterPrescaleCount <= FilterPreScale;
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FilteredPhaseErr <= FilteredPhaseErr + (resize(BoundedPhaseErr(23 downto 8),24) - resize(FilteredPhaseErr(23 downto 8),24));
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if Iterm > Ilimit then
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ITerm <= Ilimit;
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end if;
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if Iterm < -Ilimit then
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Iterm <= -Ilimit;
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end if;
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ITerm <= ITerm + resize(BoundedPhaseErr(23 downto 12),24);
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else
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FilterPreScaleCount <= FilterPreScaleCount -1;
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end if;
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else
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PreScaleCount <= PreScaleCount -1;
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end if; -- prescale;
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DPLLCorrection <= FilteredPhaseErr + resize(BoundedPhaseErr(23 downto 4),24) + ITerm;
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-- DPLLCorrection <= FilteredPhaseErr + resize(BoundedPhaseErr(23 downto 4),24);
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-- DPLLCorrection <= FilteredPhaseErr;
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if syncread = '1' or syncwrite = '1' or FilteredSync = "01" then
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PhaseErr <= Accum(AccumSize-1 downto AccumSize-32); -- top 32 bits
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end if;
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if loadphase = '1' then
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Accum(AccumSize-1 downto AccumSize-32) <= signed(ibus);
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end if;
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if loadbaserate = '1' then
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baserate <= signed(ibus);
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end if;
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if loadcontrol0 = '1' then
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Plimit <= signed(ibus(23 downto 0));
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PreScale <= unsigned(ibus(31 downto 24));
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FilteredPhaseErr <= (others => '0');
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PhaseErr <= (others => '0');
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ITerm <= (others => '0');
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end if;
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if loadcontrol1 = '1' then
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FilterPreScale <= unsigned(ibus(31 downto 16));
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end if;
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if loadtimers12 = '1' then
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timer1 <= unsigned(ibus(15 downto 0));
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timer2 <= unsigned(ibus(31 downto 16));
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end if;
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if loadtimers34 = '1' then
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timer3 <= unsigned(ibus(15 downto 0));
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timer4 <= unsigned(ibus(31 downto 16));
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end if;
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TimerOutReg(0) <= TimerOff1(15);
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TimerOutReg(1) <= TimerOff2(15);
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TimerOutReg(2) <= TimerOff3(15);
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TimerOutReg(3) <= TimerOff4(15);
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end if; -- clk
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Accum16 <= unsigned(std_logic_vector(Accum(AccumSize-1 downto AccumSize-16)));
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obus <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
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if readphase = '1' or syncread= '1' then
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obus <= std_logic_vector(Accum(AccumSize-1 downto AccumSize-32));
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end if;
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if readbaserate = '1' then
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obus <= std_logic_vector(BaseRate);
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end if;
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if readcontrol0 = '1' then
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obus(31 downto 24) <= std_logic_vector(PreScale);
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obus(23 downto 0) <= std_logic_vector(DPLLCorrection);
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end if;
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if readcontrol1 = '1' then
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obus(31 downto 16) <= std_logic_vector(FilterPreScale);
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obus(15 downto 8) <= (others => '0');
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obus(7 downto 0) <= std_logic_vector(to_unsigned(AccumSize,8));
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end if;
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if readtimers12 = '1' then
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obus(15 downto 0) <= std_logic_vector(Timer1);
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obus(31 downto 16) <= std_logic_vector(Timer2);
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end if;
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if readtimers34 = '1' then
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obus(15 downto 0) <= std_logic_vector(Timer3);
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obus(31 downto 16) <= std_logic_vector(Timer4);
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end if;
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TimerOff1 <= Timer1 + Accum16;
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TimerOff2 <= Timer2 + Accum16;
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TimerOff3 <= Timer3 + Accum16;
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TimerOff4 <= Timer4 + Accum16;
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timerout <= not TimerOutReg; -- These are inverted since we use the rising
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refout <= not Accum(AccumSize-1); -- edge as the external timing reference
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end process;
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end behavioral;
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