262 lines
8.3 KiB
VHDL
Executable File
262 lines
8.3 KiB
VHDL
Executable File
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--
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-- Copyright (C) 2010, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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entity wavegen is
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generic (
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buswidth : integer := 32;
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pdmwidth : integer := 13 --13 max
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);
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port (
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clk: in std_logic;
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hclk: in std_logic;
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ibus: in std_logic_vector (buswidth -1 downto 0);
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-- obus: out std_logic_vector (buswidth -1 downto 0);
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loadrate: in std_logic;
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loadlength: in std_logic;
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loadpdmrate: in std_logic;
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loadtableptr: in std_logic;
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loadtabledata: in std_logic;
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trigger0: out std_logic;
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trigger1: out std_logic;
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trigger2: out std_logic;
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trigger3: out std_logic;
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pdmouta: out std_logic;
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pdmoutb: out std_logic
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);
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end wavegen;
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architecture behavioral of wavegen is
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signal rateacc: std_logic_vector (32 downto 0);
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alias ratemsb: std_logic is rateacc(32);
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signal oldratemsb: std_logic;
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signal pdmrate: std_logic_vector (7 downto 0);
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alias pdmratemsb: std_logic is pdmrate(7);
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signal pdmval: std_logic_vector (pdmwidth-2 downto 0);
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signal pdmaccum: std_logic_vector (pdmwidth-1 downto 0);
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alias pdmbit: std_logic is pdmaccum(pdmwidth-1);
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signal ptabledata: std_logic_vector (15 downto 0); -- need to parametize
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signal htableptr: std_logic_vector (9 downto 0);
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signal ptableptr: std_logic_vector (9 downto 0);
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signal hratereg: std_logic_vector(31 downto 0);
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signal ratereg: std_logic_vector(31 downto 0);
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signal loadratereq: std_logic;
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signal oldloadratereq: std_logic;
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signal olderloadratereq: std_logic;
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signal hlengthreg: std_logic_vector(9 downto 0);
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signal plengthreg: std_logic_vector(9 downto 0);
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signal loadlengthreq: std_logic;
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signal oldloadlengthreq: std_logic;
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signal olderloadlengthreq: std_logic;
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signal pdmratereg: std_logic_vector (7 downto 0);
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signal hpdmratereg: std_logic_vector (7 downto 0);
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signal loadpdmratereq: std_logic;
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signal oldloadpdmratereq: std_logic;
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signal olderloadpdmratereq: std_logic;
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signal htabledatareg: std_logic_vector (15 downto 0);
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signal hhtabledatareg: std_logic_vector (15 downto 0);
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signal loadhtabledatareq: std_logic;
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signal oldloadhtabledatareq: std_logic;
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signal olderloadhtabledatareq: std_logic;
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signal premwrite: std_logic;
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signal mwrite: std_logic;
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signal triggerreg: std_logic_vector(3 downto 0);
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begin
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-- 1024 long max, 12 bit resolution max + 4 trigger bits
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waveram : entity work.waveram
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port map(
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addra => htableptr(9 downto 0),
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addrb => ptableptr(9 downto 0),
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clk => hclk,
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dina => htabledatareg,
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doutb => ptabledata,
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wea => mwrite
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);
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awavegen: process (hclk,clk,ptabledata, olderloadhtabledatareq, olderloadratereq,
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olderloadpdmratereq, olderloadlengthreq, pdmaccum, triggerreg)
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begin
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if rising_edge(hclk) then
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if pdmratemsb = '1' then
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pdmaccum <= ('0'&pdmaccum(pdmwidth-2 downto 0)) + ('0'&pdmval);
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pdmrate <= pdmratereg;
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else
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pdmrate <= pdmrate -1;
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end if;
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rateacc <= rateacc + ('0' & ratereg);
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oldratemsb <= ratemsb;
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-- bus speed to pdm speed register write sync
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if oldloadratereq = '1' and olderloadratereq ='1' then
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ratereg <= hratereg;
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end if;
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olderloadratereq <= oldloadratereq;
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oldloadratereq <= loadratereq;
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if oldloadlengthreq = '1' and olderloadlengthreq ='1' then
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plengthreg <= hlengthreg;
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end if;
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olderloadlengthreq <= oldloadlengthreq;
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oldloadlengthreq <= loadlengthreq;
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if oldloadpdmratereq = '1' and olderloadpdmratereq ='1' then
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pdmratereg <= hpdmratereg;
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end if;
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olderloadpdmratereq <= oldloadpdmratereq;
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oldloadpdmratereq <= loadpdmratereq;
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mwrite <= premwrite; -- mwrite 1 clock after register
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if oldloadhtabledatareq = '1' and olderloadhtabledatareq ='1' then
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htabledatareg <= hhtabledatareg;
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premwrite <= '1';
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else
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premwrite <= '0';
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end if;
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olderloadhtabledatareq <= oldloadhtabledatareq;
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oldloadhtabledatareq <= loadhtabledatareq;
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if ratemsb /= oldratemsb then
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if ptableptr >= plengthreg then
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ptableptr <= (others => '0');
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else
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ptableptr <= ptableptr +1;
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end if;
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end if;
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pdmval <= ptabledata(pdmwidth-2 downto 0);
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triggerreg <= ptabledata(15 downto 12);
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end if; -- hclk
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pdmval <= ptabledata(pdmwidth-2 downto 0);
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if rising_edge(clk) then -- 33/48/50 mhz local bus clock
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if loadtableptr = '1' then
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htableptr <= ibus(9 downto 0); -- no need to sync
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end if;
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if loadtabledata = '1' then
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hhtabledatareg <= ibus(15 downto 0);
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loadhtabledatareq <= '1';
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end if;
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if loadpdmrate = '1' then
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hpdmratereg <= ibus(7 downto 0);
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loadpdmratereq <= '1';
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end if;
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if loadrate = '1' then
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hratereg <= ibus(31 downto 0);
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loadratereq <= '1';
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end if;
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if loadlength = '1' then
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hlengthreg <= ibus(9 downto 0);
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loadlengthreq <= '1';
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end if;
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end if; -- clk
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if olderloadhtabledatareq = '1' then -- asynchronous request clear
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loadhtabledatareq <= '0'; -- if only I had used read and write strobes
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end if; -- these would have folded up into a single slowstrobe-faststrobe
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if olderloadratereq = '1' then -- asynchronous request clear ""
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loadratereq <= '0';
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end if;
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if olderloadpdmratereq = '1' then -- asynchronous request clear ""
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loadpdmratereq <= '0';
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end if;
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if olderloadlengthreq = '1' then -- asynchronous request clear ""
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loadlengthreq <= '0';
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end if;
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pdmouta <= pdmbit; -- push pull pdm
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pdmoutb <= not pdmbit;
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trigger0 <= triggerreg(0);
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trigger1 <= triggerreg(1);
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trigger2 <= triggerreg(2);
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trigger3 <= triggerreg(3);
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end process;
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end behavioral;
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