572 lines
24 KiB
VHDL
Executable File
572 lines
24 KiB
VHDL
Executable File
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-------------------------------------------------------------------------------
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-- 32 bit Harvard Arch accumulator oriented processor ~490 slices:
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-- 1 clk/inst, only exception is conditional jumps:
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-- 1 clock if not taken, 3 clocks if taken
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-- ~70 MHz operation in Spartan3 ~40 MHz in Spartan2
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-- 32 bit data, 24 bit instruction width
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-- 64 JMP instructions:
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-- All Ored true, false, dont-care combinations of sign, zero and carry
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-- 10 basic memory reference instructions:
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-- OR, XOR, AND, ADD, ADDC, SUB, SUBB, LDA, STA, MUL, MULS (ACC OP MEM --> ACC)
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-- OR, XOR, AND, ADD, ADDC, SUB, SUBB, LDA have writeback option (ACC OP MEM --> ACC,MEM)
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-- Multiply has pipelined mac option with aux 40 bit accumulator
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-- 11 operate instructions, load immediate, rotate, mac clear and load bounded mac
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-- LXWI, LLWI, LHWI, WSWP, SXW, RCL, RCR, ASHR, CLRMAC, LDMACB, LDMACT?
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-- 14 index load/store/increment:
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-- LDY, LDX, LDZ, LDT, STY, STX, STZ, STT, ADDIX, ADDIY, ADDIZ, ADDIT, RTT, TTR
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-- 4K words instruction space
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-- 4K words data space (exp to 32K words)
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-- 4 index registers for indirect memory access
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-- 12-15 bit offset for indirect addressing (ADD sinetable(6) etc)
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-- 12-15 bit direct memory addressing range
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-- 12-15 bit indirect addressing range with 12 bit offset range
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-- 2 levels of subroutine call/return
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-- Starts at address 0 from reset
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-- THE BAD NEWS: pipelined processor with no locks so --->
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-- Instruction hazards:
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-- PUSH/POP must precede JSR by at least 2 instructions
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--
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-- PUSH/POP must precede RET by at least 2 instructions
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-- (option) No unconditional jumps in 2 instructions after a conditional jump
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-- Data hazards:
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-- Stored data requires 3 instructions before fetch
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-- MAC data needs one extra instruction time after last MUL before transfer to ACC
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-- Address hazards:
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-- Fetches via index register require 2 instructions from ST(X,Y,Z,T),ADDI(X,Y)
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-- to actual fetch (STA via index takes no extra delay)
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-------------------------------------------------------------------------------
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entity Big32v2 is
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generic(
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width : integer := 32; -- data width
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iwidth : integer := 24; -- instruction width
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maddwidth : integer := 12; -- memory address width
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macwidth : integer := 40; -- macwidth
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paddwidth : integer := 12 -- program counter width
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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iabus : out std_logic_vector(paddwidth-1 downto 0); -- program address bus
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idbus : in std_logic_vector(iwidth-1 downto 0); -- program data bus
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mradd : out std_logic_vector(maddwidth-1 downto 0); -- memory read address
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mwadd : out std_logic_vector(maddwidth-1 downto 0); -- memory write address
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mibus : in std_logic_vector(width-1 downto 0); -- memory data in bus
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mobus : out std_logic_vector(width-1 downto 0); -- memory data out bus
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mwrite : out std_logic; -- memory write signal
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mread : out std_logic; -- memory read signal
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carryflg : out std_logic -- carry flag
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);
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end Big32v2;
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architecture Behavioral of Big32v2 is
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-- basic op codes -- IIII0MRRXXXXAAAAAAAAAAAA or IIII1MXXXXXXOOOOOOOOOOOO
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-- Beware, certain bits are used to simpilfy decoding - dont change without knowing what you are doing...
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constant opr : std_logic_vector (3 downto 0) := x"0"; -- operate
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constant jsr : std_logic_vector (3 downto 0) := x"1"; -- jump to sub
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constant jmp : std_logic_vector (3 downto 0) := x"2"; -- unconditional jump
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constant jmpc : std_logic_vector (3 downto 0) := x"3"; -- conditional jump
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constant lda : std_logic_vector (3 downto 0) := x"4"; -- load accumulator from memory
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constant lor : std_logic_vector (3 downto 0) := x"5"; -- OR accumulator with memory
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constant lxor : std_logic_vector (3 downto 0) := x"6"; -- XOR accumulator with memory
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constant land : std_logic_vector (3 downto 0) := x"7"; -- AND accumulator with memory
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constant idxo : std_logic_vector (3 downto 0) := x"8"; -- IDX operate
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constant mul : std_logic_vector (3 downto 0) := x"9"; -- signed unsigned Multiply
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constant muls : std_logic_vector (3 downto 0) := x"A"; -- signed signed Multiply
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constant sta : std_logic_vector (3 downto 0) := x"B"; -- store accumulator to memory
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constant add : std_logic_vector (3 downto 0) := x"C"; -- add memory to accumulator
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constant addc : std_logic_vector (3 downto 0) := x"D"; -- add memory and carry to accumulator
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constant sub : std_logic_vector (3 downto 0) := x"E"; -- subtract memory from accumulator
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constant subc : std_logic_vector (3 downto 0) := x"F"; -- subtract memory and carry from accumulator
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-- operate instructions
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constant nop : std_logic_vector (3 downto 0) := x"0";
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-- immediate load type -- 0INNNNh
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constant lxwi : std_logic_vector (3 downto 0) := x"1";
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constant llwi : std_logic_vector (3 downto 0) := x"2";
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constant lhwi : std_logic_vector (3 downto 0) := x"3";
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-- accumulator operate type -- 0IXXXXh
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constant rotcl : std_logic_vector (3 downto 0) := x"4";
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constant rotcr : std_logic_vector (3 downto 0) := x"5";
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constant wswp : std_logic_vector (3 downto 0) := x"6";
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constant sxw : std_logic_vector (3 downto 0) := x"7";
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constant clrmac : std_logic_vector (3 downto 0) := x"8";
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constant ldmacb : std_logic_vector (3 downto 0) := x"9";
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constant ldmact : std_logic_vector (3 downto 0) := x"A";
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constant ashr : std_logic_vector (3 downto 0) := x"B";
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-- constant bitset?
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-- constant bitclr?
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-- constant setbit
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-- constant clrbit
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-- index register load/store in address order -- 8IXXXXh
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constant ldx : std_logic_vector (3 downto 0) := x"0";
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constant ldy : std_logic_vector (3 downto 0) := x"1";
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constant ldz : std_logic_vector (3 downto 0) := x"2";
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constant ldt : std_logic_vector (3 downto 0) := x"3";
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constant stx : std_logic_vector (3 downto 0) := x"4";
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constant sty : std_logic_vector (3 downto 0) := x"5";
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constant stz : std_logic_vector (3 downto 0) := x"6";
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constant stt : std_logic_vector (3 downto 0) := x"7";
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constant addix : std_logic_vector (3 downto 0) := x"8";
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constant addiy : std_logic_vector (3 downto 0) := x"9";
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constant addiz : std_logic_vector (3 downto 0) := x"A";
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constant addit : std_logic_vector (3 downto 0) := x"B";
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-- return register save/restore -- 8IXXXXh
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constant pop : std_logic_vector (3 downto 0) := x"C";
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constant push : std_logic_vector (3 downto 0) := x"D";
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constant ldsp : std_logic_vector (3 downto 0) := x"E";
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constant stsp : std_logic_vector (3 downto 0) := x"F";
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-- basic signals
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signal accumcar : std_logic_vector (width downto 0); -- accumulator+carry
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alias accum : std_logic_vector (width-1 downto 0) is accumcar(width-1 downto 0);
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alias carrybit : std_logic is accumcar(width);
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alias signbit : std_logic is accumcar(width-1);
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signal maskedcarry : std_logic;
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signal macc : std_logic_vector (macwidth-1 downto 0); -- macccumulator
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alias mmsb : std_logic is macc(macwidth-1);
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alias mnmsbs : std_logic_vector(6 downto 0) is macc(macwidth-2 downto macwidth-8);
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signal macnext : std_logic;
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signal pc : std_logic_vector (paddwidth -1 downto 0); -- program counter - 12 bits = 4k
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signal mra : std_logic_vector (maddwidth -1 downto 0); -- memory read address - 12 bits = 4k
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signal id1 : std_logic_vector (iwidth -1 downto 0); -- instruction pipeline 1
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signal id2 : std_logic_vector (iwidth -1 downto 0); -- instruction pipeline 2
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alias wbena2 : std_logic is id2(iwidth-2);
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alias writeback2 : std_logic is id2(iwidth-9);
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signal wbena3 : std_logic;
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signal writeback3: std_logic;
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alias opcode0 : std_logic_vector (3 downto 0) is idbus (iwidth-1 downto iwidth-4); -- main opcode at pipe0
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alias opcode2 : std_logic_vector (3 downto 0) is id2 (iwidth-1 downto iwidth-4); -- main opcode at pipe2
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signal opcode3 : std_logic_vector (3 downto 0);
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alias CarryMask2 : std_logic is id2 (iwidth-5);
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alias CarryXor2 : std_logic is id2 (iwidth-6);
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alias ZeroMask2 : std_logic is id2 (iwidth-7);
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alias ZeroXor2 : std_logic is id2 (iwidth-8);
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alias SignMask2 : std_logic is id2 (iwidth-9);
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alias SignXor2 : std_logic is id2 (iwidth-10);
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alias OvflMask2 : std_logic is id2 (iwidth-11);
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alias OvflXor2 : std_logic is id2 (iwidth-12);
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signal jumpq : std_logic;
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alias Arith : std_logic_vector (1 downto 0) is id2 (iwidth-1 downto iwidth-2);
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alias WithCarry : std_logic is id2(iwidth-4); -- indicates add with carry or subtract with borrow
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alias Minus : std_logic is id2(iwidth-3); -- indicates subtract
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alias opradd0 : std_logic_vector (maddwidth -1 downto 0) is idbus (maddwidth -1 downto 0); -- operand address at pipe0
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alias opradd2 : std_logic_vector (maddwidth -1 downto 0) is id2 (maddwidth -1 downto 0); -- operand address at pipe2
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alias ind0 : std_logic is idbus(iwidth -5);
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alias ind2 : std_logic is id2(iwidth -5);
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alias domac : std_logic is id2(iwidth -6);
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alias ireg0 : std_logic_vector(1 downto 0) is idbus(iwidth -7 downto iwidth -8);
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alias offset0 : std_logic_vector (maddwidth-1 downto 0) is idbus(maddwidth-1 downto 0);
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alias opropcode2 : std_logic_vector (3 downto 0) is id2 (iwidth-5 downto iwidth-8); -- operate opcode at pipe2 alias iopr2 : std_logic_vector (7 downto 0) is id2 (7 downto 0); -- immediate operand at pipe2
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alias iopr2 : std_logic_vector (15 downto 0) is id2 (15 downto 0); -- immediate operand at pipe2
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signal oprr : std_logic_vector (width -1 downto 0); -- operand register
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signal idx : std_logic_vector (maddwidth -1 downto 0);
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signal idy : std_logic_vector (maddwidth -1 downto 0);
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signal idz : std_logic_vector (maddwidth -1 downto 0);
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signal idt : std_logic_vector (maddwidth -1 downto 0);
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signal idn0 : std_logic_vector (maddwidth -1 downto 0);
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signal nextpc : std_logic_vector (paddwidth -1 downto 0);
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signal pcplus1 : std_logic_vector (paddwidth -1 downto 0);
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signal acczero : std_logic;
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signal maddpipe1 : std_logic_vector (maddwidth -1 downto 0);
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signal maddpipe2 : std_logic_vector (maddwidth -1 downto 0);
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signal maddpipe3 : std_logic_vector (maddwidth -1 downto 0);
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signal product : std_logic_vector (width -1 downto 0);
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signal apatch : std_logic_vector (width/2 -1 downto 0);
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signal opatch : std_logic_vector (width/2 -1 downto 0);
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signal spw: std_logic_vector (3 downto 0);
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signal spr: std_logic_vector (3 downto 0);
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signal stackdin: std_logic_vector (width-1 downto 0);
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signal stackdout: std_logic_vector (width-1 downto 0);
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signal stackwe: std_logic;
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signal dopush: std_logic;
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signal dopop: std_logic;
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function rotcleft(v : std_logic_vector ) return std_logic_vector is
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variable result : std_logic_vector(width downto 0);
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begin
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result(width downto 1) := v(width-1 downto 0);
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result(0) := v(width);
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return result;
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end rotcleft;
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function rotcright(v : std_logic_vector ) return std_logic_vector is
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variable result : std_logic_vector(width downto 0);
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begin
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result(width -1 downto 0) := v(width downto 1);
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result(width) := v(0);
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return result;
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end rotcright;
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function signextendword(v : std_logic_vector ) return std_logic_vector is
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variable result : std_logic_vector(width -1 downto 0);
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begin
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if v(15) = '1' then
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result(width-1 downto 16) := x"FFFF";
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else
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result(width-1 downto 16) := x"0000";
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end if;
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result(15 downto 0) := v(15 downto 0);
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return result;
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end signextendword;
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function wordswap(v : std_logic_vector ) return std_logic_vector is
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variable result : std_logic_vector(width -1 downto 0);
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begin
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result(width -1 downto 16) := v(15 downto 0);
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result(15 downto 0) := v(width-1 downto 16);
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return result;
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end wordswap;
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begin -- the CPU
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StackRam : entity work.adpram
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generic map (
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width => width,
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depth => 16
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)
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port map(
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addra => spw,
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addrb => spr,
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clk => clk,
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dina => stackdin,
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-- douta =>
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doutb => stackdout,
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wea => stackwe
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);
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nextpcproc : process (clk, reset, pc, acczero, nextpc,
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id2, ind0, ind2, idbus, opcode0,
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opcode2, carrybit, accumcar) -- next pc calculation - jump decode
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begin
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jumpq <= (((SignBit xor SignXor2) and SignMask2) or
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((CarryBit xor CarryXor2) and CarryMask2) or
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((acczero xor ZeroXor2) and ZeroMask2));
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pcplus1 <= pc + '1';
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iabus <= nextpc; -- program memory address from combinatorial
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if reset = '1' then -- nextpc since blockram has built in addr register
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nextpc <= (others => '0');
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else
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if (opcode0 = jmp) or (opcode0= jsr) then
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if ind0 = '1' then -- indirect (computed jump or return)
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nextpc <= stackdout(paddwidth -1 downto 0);
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else -- direct (jump or jsr)
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nextpc <= idbus(paddwidth -1 downto 0);
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end if;
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elsif (opcode2 = jmpc) and (jumpq = '1') then -- direct only
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nextpc <= id2(paddwidth -1 downto 0);
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else
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nextpc <= pcplus1;
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end if; -- opcode = jmp
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end if; -- no reset
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if clk'event and clk = '1' then
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pc <= nextpc;
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id1 <= idbus; -- instruction pipeline
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id2 <= id1;
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writeback3 <= writeback2; -- the writeback bit
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wbena3 <= wbena2; -- determines writeback suitable instructions
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opcode3 <= opcode2; -- for late decode of STA
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if reset = '1' or ((opcode2 = jmpc) and (jumpq = '1')) then
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-- if reset = '1' then
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id1 <= (others => '0'); -- on reset or taken conditional jump
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id2 <= (others => '0'); -- fill inst pipeline with two 0s (nop)
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end if;
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end if;
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end process nextpcproc;
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mraproc : process (idbus, idx, idy, idz, idt, mra, ind0,
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ireg0,
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offset0, opcode0, opradd0, clk) -- memory read address generation
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begin
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mradd <= mra;
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-- idx reg mux
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case ireg0 is
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when "00" => idn0 <= idx;
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when "01" => idn0 <= idy;
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when "10" => idn0 <= idz;
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when "11" => idn0 <= idt;
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when others => null;
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end case;
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-- direct/ind mux
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if ((opcode0 /= opr) and (opcode0 /= idxo) and (ind0 = '0')) then
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mra <= opradd0;
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else
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mra <= idn0 + offset0;
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end if;
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if clk'event and clk = '1' then
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if (opcode0 = lda) or (opcode0 = lor) or (opcode0 = lxor) or (opcode0 = land) or (opcode0 = mul)
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or (opcode0 = add) or (opcode0 = addc) or (opcode0 = sub) or (opcode0 = subc) then
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mread <= '1'; -- assert mread for side effects (FIFOs etc)
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else
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mread <= '0';
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end if;
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maddpipe3 <= maddpipe2;
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maddpipe2 <= maddpipe1;
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maddpipe1 <= mra;
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end if;
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end process mraproc;
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oprrproc : process (clk) -- memory operand register -- could remove to
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begin -- reduce pipelining depth but would impact I/O read
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if clk'event and clk = '1' then -- access time --> not good for larger systems
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oprr <= mibus;
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end if;
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end process oprrproc;
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accumproc : process (clk, accumcar, accum, id2, oprr) -- accumulator instruction decode - operate
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begin
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|
carryflg <= carrybit;
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if accum = x"00000000" then
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|
acczero <= '1';
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else
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acczero <= '0';
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end if;
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maskedcarry <= carrybit and WithCarry;
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|
|
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if clk'event and clk = '1' then
|
|
case opcode2 is -- memory reference first
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|
when land => accum <= accum and oprr;
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when lor => accum <= accum or oprr;
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when lxor => accum <= accum xor oprr;
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|
when lda => accum <= oprr;
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if domac = '1' then
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|
macnext <= '1';
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else
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|
macnext <= '0';
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|
end if;
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|
when mul => accum(15 downto 0) <= product(15 downto 0);
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|
accum(31 downto 16)<= product(31 downto 16) -apatch;
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|
if domac = '1' then
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|
macnext <= '1';
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|
else
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|
macnext <= '0';
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|
end if;
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when muls => accum(15 downto 0) <= product(15 downto 0);
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|
accum(31 downto 16)<= product(31 downto 16) -apatch -opatch;
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|
if domac = '1' then
|
|
macnext <= '1';
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|
else
|
|
macnext <= '0';
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|
end if;
|
|
|
|
when opr => -- then operate
|
|
case opropcode2 is
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|
when lxwi => accum <= signextendword(iopr2); -- load sign extended word immediate
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|
when llwi => accum(15 downto 0) <= iopr2; -- load low word immediate
|
|
when lhwi => accum(31 downto 16) <= iopr2; -- load high word immediate
|
|
when rotcl => accumcar <= rotcleft(accumcar); -- rotate left through carry
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|
when rotcr => accumcar <= rotcright(accumcar); -- rotate right through carry
|
|
when ashr => accumcar(width-2 downto 0) <= accumcar(width-1 downto 1);
|
|
accumcar(width-1) <= accumcar(width-1); -- shift right arithmetic (fixed 7/24/12)
|
|
when wswp => accum <= wordswap(accum); -- word swap
|
|
when sxw => accum <= signextendword(accum); -- sign extend 16 bit value in low half
|
|
when clrmac => macc <= (others => '0'); -- clear the macc
|
|
when ldmacb =>
|
|
if mmsb = '0' then -- positive case
|
|
if mnmsbs = 0 then
|
|
accum <= macc(31 downto 0); -- no overflow
|
|
else
|
|
accum <= x"7FFFFFFF"; -- if overflow bound to max positive
|
|
end if;
|
|
else -- negative case
|
|
if mnmsbs = "1111111" then
|
|
accum <= macc(31 downto 0); -- no overflow
|
|
else
|
|
accum <= x"80000000"; -- if overflow bound to max negative
|
|
end if;
|
|
end if;
|
|
when others => null;
|
|
end case;
|
|
when idxo => -- then index register operate
|
|
case opropcode2 is
|
|
when ldx => accum(maddwidth-1 downto 0) <= idx;
|
|
when ldy => accum(maddwidth-1 downto 0) <= idy;
|
|
when ldz => accum(maddwidth-1 downto 0) <= idz;
|
|
when ldt => accum(maddwidth-1 downto 0) <= idt;
|
|
|
|
when stx => idx <= accum(maddwidth-1 downto 0);
|
|
when sty => idy <= accum(maddwidth-1 downto 0);
|
|
when stz => idz <= accum(maddwidth-1 downto 0);
|
|
when stt => idt <= accum(maddwidth-1 downto 0);
|
|
|
|
when addix => idx <= maddpipe2; -- re-use the offset adder
|
|
when addiy => idy <= maddpipe2; -- for add immediate to index
|
|
when addiz => idz <= maddpipe2;
|
|
when addit => idt <= maddpipe2;
|
|
|
|
when pop => accum <= stackdout;
|
|
when stsp => spw <= accum(3 downto 0);
|
|
when ldsp => accum(3 downto 0) <= spw;
|
|
accum(width-1 downto 4) <= (others => '0');
|
|
|
|
when others => null;
|
|
end case;
|
|
when others => null;
|
|
end case;
|
|
|
|
if Arith = "11" then
|
|
if Minus = '0' then
|
|
accumcar <= '0'&accum + oprr + maskedcarry; -- add/addc
|
|
else
|
|
accumcar <= '0'&accum - oprr - maskedcarry; -- sub/subc
|
|
end if;
|
|
if domac = '1' then
|
|
macnext <= '1';
|
|
else
|
|
macnext <= '0';
|
|
end if;
|
|
end if;
|
|
|
|
if macnext = '1' then
|
|
macc <= macc + accum;
|
|
end if;
|
|
|
|
if dopush = '1' then
|
|
spw <= spw +1;
|
|
end if;
|
|
|
|
if dopop = '1' then
|
|
spw <= spw -1;
|
|
end if;
|
|
|
|
end if; -- clk
|
|
|
|
if opcode0 = jsr then
|
|
stackdin(paddwidth-1 downto 0) <= pcplus1; -- a jsr (note jsr has priority)
|
|
stackdin(width -1 downto paddwidth) <=(others => '0');
|
|
else
|
|
stackdin <= accum;
|
|
end if;
|
|
|
|
if (opcode0 = jsr) or ((opcode2 = idxo) and (opropcode2 = push)) then
|
|
stackwe <= '1';
|
|
dopush <= '1';
|
|
else
|
|
stackwe <= '0';
|
|
dopush <= '0';
|
|
end if;
|
|
|
|
if ((opcode0= jmp) and (ind0 = '1')) -- jmp indirect is a return
|
|
or ((opcode2 = idxo) and (opropcode2 = pop)) then
|
|
dopop <= '1';
|
|
else
|
|
dopop <= '0';
|
|
end if;
|
|
|
|
spr <= spw -1;
|
|
|
|
product <= accum(15 downto 0) * oprr(15 downto 0);
|
|
if accum(15) = '1' then
|
|
apatch <= oprr(15 downto 0);
|
|
else
|
|
apatch <= (others =>'0');
|
|
end if;
|
|
if oprr(15) = '1' then
|
|
opatch <= accum(15 downto 0);
|
|
else
|
|
opatch <= (others =>'0');
|
|
end if;
|
|
|
|
end process accumproc;
|
|
|
|
|
|
mwproc : process (accumcar,opcode3,writeback3,wbena3,maddpipe3) -- sta/writeback decode -- not much to do but enable mwrite
|
|
begin
|
|
mwadd <= maddpipe3; -- address at pipe 3 to match latched accumulator timimg
|
|
mobus <= accum; -- all we can write is whats in the accum
|
|
if (opcode3 = sta) or ((writeback3 = '1') and (wbena3 = '1')) then
|
|
mwrite <= '1'; -- asserted at pipe 3 to match
|
|
else -- latched accumulator/maddpipe3
|
|
mwrite <= '0';
|
|
end if;
|
|
end process mwproc;
|
|
|
|
end Behavioral;
|