145 lines
4.7 KiB
VHDL
Executable File
145 lines
4.7 KiB
VHDL
Executable File
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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entity watchdog is
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generic (
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buswidth : integer
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);
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port ( clk : in std_logic;
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ibus : in std_logic_vector (buswidth-1 downto 0);
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obus : out std_logic_vector (buswidth-1 downto 0);
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loadtime : in std_logic;
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readtime : in std_logic;
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loadstatus: in std_logic;
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readstatus: in std_logic;
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cookie: in std_logic;
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wdbite : out std_logic;
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wdlatchedbite : out std_logic );
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end watchdog;
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architecture Behavioral of watchdog is
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constant otherz: std_logic_vector (buswidth-2 downto 0) := (others => '0');
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signal wdtimer: std_logic_vector (buswidth-1 downto 0) := '1' & otherz;
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signal wdtime: std_logic_vector (buswidth-1 downto 0);
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alias wdtimermsb: std_logic is wdtimer(buswidth-1);
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signal wdstatus: std_logic := '0';
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signal oldwdtimermsb: std_logic := '1';
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begin
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atimeout: process (clk,wdtimer,wdstatus,
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readtime, readstatus,
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wdtimermsb, oldwdtimermsb)
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begin
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if rising_edge(clk) then
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oldwdtimermsb <= wdtimermsb;
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if wdtimermsb /= '1' then
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wdtimer <= wdtimer -1;
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end if;
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if loadtime = '1' then
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wdtimer <= ibus;
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wdtime <= ibus;
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end if;
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if cookie = '1' then
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if ibus(buswidth-1 downto buswidth-8) = x"5A" then
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wdtimer <= wdtime;
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end if;
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end if;
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if loadstatus = '1' then
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wdstatus <= ibus(0);
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end if;
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if wdtimermsb = '1' and oldwdtimermsb = '0' then -- edge triggered
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wdbite <= '1';
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wdstatus <= '1';
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else
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wdbite <= '0';
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end if;
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end if; -- clk
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obus <= (others =>'Z');
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if readtime = '1' then
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obus <= wdtimer;
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end if;
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if readstatus = '1' then
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obus(0) <= wdstatus;
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obus(buswidth -1 downto 1) <= (others => '0');
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end if;
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wdlatchedbite <= wdstatus;
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end process;
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end Behavioral;
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