315 lines
9.5 KiB
VHDL
Executable File
315 lines
9.5 KiB
VHDL
Executable File
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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entity uartx is
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Port ( clk : in std_logic;
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ibus : in std_logic_vector(31 downto 0);
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obus : out std_logic_vector(31 downto 0);
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addr : in std_logic_vector(1 downto 0);
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pushfifo : in std_logic;
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loadbitrate : in std_logic;
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readbitrate : in std_logic;
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clrfifo : in std_logic;
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readfifocount : in std_logic;
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loadmode : in std_logic;
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readmode : in std_logic;
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fifoempty : out std_logic;
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txen : in std_logic;
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drven : out std_logic;
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txdata : out std_logic
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);
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end uartx;
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architecture Behavioral of uartx is
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-- FIFO related signals
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signal pushdata: std_logic_vector(33 downto 0);
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signal popadd: std_logic_vector(3 downto 0) := x"f";
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signal popdata: std_logic_vector(33 downto 0);
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alias byteshere: std_logic_vector(1 downto 0) is popdata(33 downto 32);
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signal datacounter: std_logic_vector(4 downto 0);
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signal push: std_logic;
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signal pop: std_logic;
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signal clear: std_logic;
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signal lfifoempty: std_logic;
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signal fifohasdata: std_logic;
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-- uart interface related signals
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constant DDSWidth : integer := 20;
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signal BitrateDDSReg : std_logic_vector(DDSWidth-1 downto 0);
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signal BitrateDDSAccum : std_logic_vector(DDSWidth-1 downto 0);
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alias DDSMSB : std_logic is BitrateDDSAccum(DDSWidth-1);
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signal OldDDSMSB: std_logic;
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signal SampleTime: std_logic;
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signal BitCount : std_logic_vector(3 downto 0);
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signal BytePointer : std_logic_vector(2 downto 0) := "000";
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signal SReg: std_logic_vector(10 downto 0);
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signal SendData: std_logic_vector(7 downto 0);
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alias SregData: std_logic_vector(7 downto 0)is SReg(9 downto 2);
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alias StartBit: std_logic is Sreg(1);
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alias StopBit: std_logic is Sreg(10);
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alias IdleBit: std_logic is Sreg(0);
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signal Go: std_logic := '0';
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signal ModeReg: std_logic_vector(6 downto 0);
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alias DriveEnDelay: std_logic_vector(3 downto 0) is ModeReg (3 downto 0);
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alias FIFOError: std_logic is ModeReg(4);
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alias DriveEnAuto: std_logic is ModeReg(5);
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alias DriveEnBit: std_logic is ModeReg(6);
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signal DriveEnable: std_logic;
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signal DriveEnHold: std_logic;
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signal WaitingForDrive: std_logic;
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signal DriveDelayCount: std_logic_vector(3 downto 0);
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component SRL16E
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--
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generic (INIT : bit_vector);
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--
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port (D : in std_logic;
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CE : in std_logic;
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CLK : in std_logic;
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A0 : in std_logic;
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A1 : in std_logic;
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A2 : in std_logic;
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A3 : in std_logic;
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Q : out std_logic);
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end component;
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begin
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fifosrl: for i in 0 to 33 generate
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asr16e: SRL16E generic map (x"0000") port map(
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D => pushdata(i),
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CE => push,
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CLK => clk,
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A0 => popadd(0),
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A1 => popadd(1),
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A2 => popadd(2),
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A3 => popadd(3),
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Q => popdata(i)
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);
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end generate;
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afifo: process (clk,popdata,datacounter)
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begin
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if rising_edge(clk) then
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if push = '1' and pop = '0' then
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if datacounter /= 16 then -- a push
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-- always increment the data counter if not full
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datacounter <= datacounter +1;
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popadd <= popadd +1; -- popadd must follow data down shiftreg
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else
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FIFOError <= '1';
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end if;
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end if;
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if (pop = '1') and (push = '0') and (lfifoempty = '0') then -- a pop
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-- always decrement the data counter if not empty
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datacounter <= datacounter -1;
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popadd <= popadd -1;
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end if;
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-- if both push and pop are asserted we dont change either counter
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if clear = '1' then -- a clear fifo
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popadd <= (others => '1');
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datacounter <= (others => '0');
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FIFOError <= '0';
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end if;
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end if; -- clk rise
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if datacounter = 0 then
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lfifoempty <= '1';
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else
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lfifoempty <= '0';
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end if;
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fifohasdata <= not lfifoempty;
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end process afifo;
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asimpleuarttx: process (clk)
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begin
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if rising_edge(clk) then
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if Go = '1' then
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BitRateDDSAccum <= BitRateDDSAccum - BitRateDDSReg;
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if SampleTime = '1' then
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SReg <= '1' & SReg(10 downto 1); -- right shift = LSb first
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BitCount <= BitCount -1;
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if BitCount = 0 then
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Go <= '0';
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end if;
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end if;
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else
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BitRateDDSAccum <= (others => '0');
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end if;
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if pop = '1' then -- just one clock
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pop <= '0';
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end if;
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if Go = '0' then
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StartBit <= '0';
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StopBit <= '1';
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IdleBit <= '1';
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BitCount <= "1010";
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if fifohasdata = '1' and pop = '0' and txen = '1' and DriveEnHold = '0' then -- UART SReg not busy and we have data
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if bytepointer <= ('0'& byteshere) then -- still bytes to send in this double word
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SRegData <= SendData;
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Go <= '1';
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bytepointer <= bytepointer +1;
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else
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pop <= '1';
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bytepointer <= "000";
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end if;
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end if;
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end if;
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if DriveEnable = '0' then
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DriveDelayCount <= DriveEnDelay;
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else
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if WaitingForDrive = '1' then
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DriveDelayCount <= DriveDelayCount -1;
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end if;
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end if;
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OldDDSMSB <= DDSMSB;
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if loadbitrate = '1' then
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BitRateDDSReg <= ibus(DDSWidth-1 downto 0);
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end if;
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if loadmode = '1' then
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ModeReg(3 downto 0) <= ibus(3 downto 0);
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ModeReg(6 downto 5) <= ibus(6 downto 5);
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end if;
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end if; -- clk
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SampleTime <= (not OldDDSMSB) and DDSMSB;
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pushdata <= addr & ibus; -- msbs of FIFO data are address bits to specify data size
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push <= pushfifo;
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clear <= clrfifo;
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if DriveDelayCount /= 0 then
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WaitingForDrive <= '1';
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else
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WaitingForDrive <= '0';
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end if;
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DriveEnHold <= (not DriveEnable) or WaitingForDrive;
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if DriveEnAuto = '1' then
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DriveEnable <= (Go or Pop or FIFOHasData) and txen; -- note that this means txen should never be removed -- when there is data to xmit
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else -- in the middle of a block transmission
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DriveEnable <= DriveEnBit;
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end if;
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case bytepointer(1 downto 0) is
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when "00" => SendData <= PopData(7 downto 0);
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when "01" => SendData <= PopData(15 downto 8);
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when "10" => SendData <= PopData(23 downto 16);
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when "11" => SendData <= PopData(31 downto 24);
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when others => null;
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end case;
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obus <= (others => 'Z');
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if readfifocount = '1' then
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obus(4 downto 0) <= datacounter;
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obus(31 downto 5) <= (others => '0');
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end if;
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if readbitrate = '1' then
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obus(DDSWidth-1 downto 0) <= BitRateDDSReg;
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end if;
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if readmode = '1' then
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obus(6 downto 0) <= ModeReg;
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obus(7) <= Go or Pop or FIFOHasData;
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end if;
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txdata<= SReg(0);
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fifoempty <= lfifoempty;
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drven <= DriveEnable;
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end process asimpleuarttx;
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end Behavioral;
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