52 lines
1.3 KiB
VHDL
Executable File
52 lines
1.3 KiB
VHDL
Executable File
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity dmdrqlogic is
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generic (
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ndrqs : integer );
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port ( clk : in std_logic;
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ibus : in std_logic_vector (31 downto 0);
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obus : out std_logic_vector (31 downto 0);
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loadmode : in std_logic;
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readmode : in std_logic;
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drqsources : in std_logic_vector (ndrqs-1 downto 0);
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dreqout : out std_logic;
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demandmode : out std_logic);
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end dmdrqlogic;
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architecture Behavioral of dmdrqlogic is
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constant zeromask: std_logic_vector (ndrqs-1 downto 0) := (others => '0');
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signal modereg: std_logic_vector (31 downto 0);
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alias mask: std_logic_vector (ndrqs-1 downto 0) is modereg(ndrqs+15 downto 16); -- 16 max
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alias enable: std_logic is modereg(0);
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signal drq: std_logic;
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begin
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admdrq: process(clk,drqsources,readmode,mask, modereg)
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begin
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if rising_edge(clk) then
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if loadmode = '1' then
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modereg <= ibus;
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end if;
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end if;
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if (mask and drqsources) /= 0 then
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drq <= enable;
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else
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drq <= '0';
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end if;
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demandmode <= enable;
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obus <= (others => 'Z');
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if readmode = '1' then
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obus(31 downto 16) <= modereg(31 downto 16);
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obus(0) <= modereg(0);
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obus(1) <= drq;
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obus(15 downto 2) <= (others => '0');
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end if;
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dreqout <= drq;
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end process;
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end Behavioral;
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