239 lines
7.6 KiB
VHDL
Executable File
239 lines
7.6 KiB
VHDL
Executable File
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--
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-- Copyright (C) 2010, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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use work.log2.all;
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entity DAQFIFO16 is
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generic (
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Depth : integer -- and when parametized, width as well
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);
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port ( clk : in std_logic;
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ibus : in std_logic_vector (31 downto 0);
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obus : out std_logic_vector (31 downto 0);
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readfifo : in std_logic;
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readfifocount : in std_logic;
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clearfifo : in std_logic;
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loadmode : in std_logic;
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readmode : in std_logic;
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pushfrac : in std_logic;
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daqdata : in std_logic_vector (15 downto 0);
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daqfull : out std_logic;
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daqreq : out std_logic;
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daqstrobe : in std_logic );
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end DAQFIFO16;
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architecture Behavioral of DAQFIFO16 is
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signal pushadd: std_logic_vector(log2(depth)-1 downto 0);
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signal pushdata: std_logic_vector(31 downto 0);
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signal popadd: std_logic_vector(log2(depth)-1 downto 0);
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signal popdata: std_logic_vector(31 downto 0);
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signal datacounter: std_logic_vector(log2(depth) downto 0);
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signal push: std_logic; -- the write enable for our dual ported RAM
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signal pop: std_logic;
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signal oddword: std_logic;
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signal syncpush: std_logic;
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signal modereg: std_logic_vector(31 downto 0);
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alias strobepol: std_logic is modereg(0); -- 0 for falling edge, 1 for rising edge
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alias underflow: std_logic is modereg(1); -- read (pop) without data
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alias overflow: std_logic is modereg(2); -- write (push) when FIFO full
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alias dreqthresh: std_logic_vector(log2(depth)-1 downto 0) is modereg(log2(depth)+15 downto 16);
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signal strobepipe: std_logic_vector(1 downto 0);
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signal datapipe0: std_logic_vector(15 downto 0);
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signal datapipe1: std_logic_vector(15 downto 0);
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signal evenwordlatch: std_logic_vector(15 downto 0);
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signal ldaqreq: std_logic;
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begin
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daqram : entity work.dpram
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generic map (
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width => 32,
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depth => Depth
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)
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port map(
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addra => pushadd,
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addrb => popadd,
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clk => clk,
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dina => pushdata,
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-- douta =>
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doutb => popdata,
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wea => push
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);
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adaqfifo: process (clk,strobepipe, strobepol, oddword, pushfrac, datapipe1, evenwordlatch,
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datacounter, readfifo, popdata, readfifocount, readmode, modereg, ldaqreq)
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begin
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if clk'event and clk = '1' then
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-- first the FIFO pointer management
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if push = '1' and pop = '0' then -- a push
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datacounter <= datacounter + 1;
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pushadd <= pushadd + 1;
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end if;
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if pop = '1' and push = '0' then -- a pop
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datacounter <= datacounter -1;
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popadd <= popadd + 1;
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end if;
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if pop = '1' and push = '1' then -- a push and a pop
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popadd <= popadd + 1;
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pushadd <= pushadd + 1;
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end if;
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-- if neither push nor pop, do nothing... --
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if clearfifo = '1' then
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pushadd <= (others => '0');
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popadd <= (others => '0');
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datacounter <= (others => '0');
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oddword <= '0';
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end if;
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if syncpush = '1' and datacounter = depth then
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overflow <= '1';
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end if;
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if readfifo = '1' and datacounter = 0 then
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underflow <= '1';
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end if;
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-- then the data acq stuff
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strobepipe <= strobepipe(0) & daqstrobe;
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datapipe1 <= datapipe0;
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datapipe0 <= daqdata;
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if (strobepipe(0) = '1' and strobepipe(1) = '0' and strobepol = '1') -- rising edge
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or (strobepipe(0) = '0' and strobepipe(1) = '1' and strobepol = '0') then -- falling edge
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if oddword = '0' then
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evenwordlatch <= datapipe1;
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oddword <= '1';
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else
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oddword <= '0';
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end if;
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end if;
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if loadmode = '1' then
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modereg <= ibus;
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end if;
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end if; -- clk rise
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if (((strobepipe(0) = '1' and strobepipe(1) = '0' and strobepol = '1')
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or (strobepipe(0) = '0' and strobepipe(1) = '1' and strobepol = '0')) and oddword = '1') or pushfrac = '1' then
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syncpush <= '1';
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else
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syncpush <= '0';
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end if;
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pushdata <= datapipe1 & evenwordlatch; -- 32 bit push data is
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if syncpush = '1' and datacounter /= depth then
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push <= '1';
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else
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push <= '0';
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end if;
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if readfifo = '1' and datacounter /= 0 then
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pop <= '1';
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else
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pop <= '0';
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end if;
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obus <= (others => 'Z');
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if readfifo = '1' then
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obus <= popdata;
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end if;
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if readfifocount = '1' then
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obus(log2(Depth) downto 0) <= datacounter;
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obus(23 downto log2(Depth)+1) <= (others => '0');
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obus(31 downto 25) <= (others => '0');
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obus(24) <= oddword; -- eventually if this gets parametized the piece count goes here
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end if;
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if readmode = '1' then
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obus(31 downto 4) <= modereg(31 downto 4);
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obus(3) <= ldaqreq;
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obus(2 downto 0) <= modereg(2 downto 0);
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end if;
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if datacounter = depth then
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daqfull <= '1';
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else
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daqfull <= '0';
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end if;
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if (datacounter >= dreqthresh) then
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ldaqreq <= '1';
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else
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ldaqreq <= '0';
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end if;
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daqreq <= ldaqreq;
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end process;
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end Behavioral;
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