520 lines
22 KiB
VHDL
Executable File
520 lines
22 KiB
VHDL
Executable File
library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use IEEE.STD_LOGIC_ARITH.all;
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use IEEE.STD_LOGIC_UNSIGNED.all;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-------------------------------------------------------------------------------
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-- Small 8 bit Harvard Arch accumulator oriented processor ~200 slices:
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-- 1 clk/inst (except taken cond jumps = 3),
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-- > 120 MHz operation in Spartan6 >80 MHz operation in Spartan3 >50 MHz in Spartan2
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-- 8 bit data, 16 bit instruction width
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-- 6 JMP instructions:
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-- JMP, JMPNZ, JMPZ, JMPNC, JMPC, JSR
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-- 9 basic memory reference instructions:
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-- OR, XOR, AND, ADD, ADDC, SUB, SUBB, LDA, STA
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-- All memory reference instructions have writeback option (except LDA and STA)
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-- ORTO, XORTO, ANDTO, ADDTO, ADDCTO, SUBTO, SUBBTO
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-- 25 operate instructions, load immediate, rotate, index load/store:
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-- LDI, RCL, RCR, SHNL, SHNR, LDXL, LDYL, STXL, STYL, LDXH, LDYH, STXH, STYH, RTT, TTR, ADDIX, ADDIY
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-- LDZL, LDTL, STZL, STTL, LDZH, LDTH, STZH, STXH, ADDIZ, ADDIT
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-- 2K words instruction space
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-- 4K words data space
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-- Four 12 bit index registers (X,Y,Z,T) for indirect memory access
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-- 7 bit offset for indirect addressing (ADD sinetable(6) etc)
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-- 10 bit direct memory addressing range
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-- 12 bit indirect addressing range with 7 bit offset
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-- 16 levels of subroutine call/return
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-- Starts at address 0 from reset
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-- THE BAD NEWS: pipelined processor with no locks so --->
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-- Instruction hazards:
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-- PUSH must precede JMP@ by at least 2 instructions
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-- Data hazards:
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-- Stored data requires 3 instructions before fetch
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-- No reads with side effects in conditional jump shadow (2 inst after cond jump)
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-- PC Hazards:
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-- No unconditional jumps in jump shadow (2 inst after conditional jump)
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-- Address hazards:
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-- Fetches via index register require 3 instructions from ST(X,Y,Z,T) or ADDI(X,Y,Z,T)
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-- to actual fetch (STA via index takes 2 instruction delay)
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-- addix,y,z,t must have inst between successive adds that is addix,1 addix,7 wont work
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-- this may be a pipeline bug, FIXME
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-------------------------------------------------------------------------------
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entity DumbAss8sqws is -- s --> jump shadow nop q--> quad index w --> writeback
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generic( -- note dont mix this processor up with plain DumbAss8sq
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width : integer := 8; -- data width
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iwidth : integer := 16; -- instruction width
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maddwidth : integer := 12; -- memory address width
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paddwidth : integer := 11 -- program counter width
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);
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port (
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clk : in std_logic;
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reset : in std_logic;
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iabus : out std_logic_vector(paddwidth-1 downto 0); -- program address bus
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idbus : in std_logic_vector(iwidth-1 downto 0); -- program data bus
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mradd : out std_logic_vector(maddwidth-1 downto 0); -- memory read address
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mwadd : out std_logic_vector(maddwidth-1 downto 0); -- memory write address
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mibus : in std_logic_vector(width-1 downto 0); -- memory data in bus
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mobus : out std_logic_vector(width-1 downto 0); -- memory data out bus
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mwrite: out std_logic; -- memory write signal
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mread: out std_logic; -- memory read signal
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carryflg : out std_logic -- carry flag
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);
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end DumbAss8sqws;
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architecture Behavioral of DumbAss8sqws is
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constant carrymask : std_logic_vector := b"0_1111_1111"; -- mask to drop carry bit
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-- basic op codes
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-- Beware, certain bits are used to simpilfy decoding - dont change without knowing what you are doing...
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constant opr : std_logic_vector (3 downto 0) := x"0";
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constant jmp : std_logic_vector (3 downto 0) := x"1";
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constant jmpnz : std_logic_vector (3 downto 0) := x"2";
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constant jmpz : std_logic_vector (3 downto 0) := x"3";
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constant jmpnc : std_logic_vector (3 downto 0) := x"4";
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constant jmpc : std_logic_vector (3 downto 0) := x"5";
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constant jsr : std_logic_vector (3 downto 0) := x"6";
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constant lda : std_logic_vector (3 downto 0) := x"7";
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constant lor : std_logic_vector (3 downto 0) := x"8";
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constant lxor : std_logic_vector (3 downto 0) := x"9";
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constant land : std_logic_vector (3 downto 0) := x"A";
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constant sta : std_logic_vector (3 downto 0) := x"B";
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constant add : std_logic_vector (3 downto 0) := x"C"; -- beware magic decoding of carry ops
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constant addc : std_logic_vector (3 downto 0) := x"D";
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constant sub : std_logic_vector (3 downto 0) := x"E";
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constant subc : std_logic_vector (3 downto 0) := x"F";
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-- operate instructions
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constant nop : std_logic_vector (3 downto 0) := x"0";
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-- immediate load type
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constant ldi : std_logic_vector (3 downto 0) := x"1";
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-- accumulator operate type
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constant rotcl : std_logic_vector (4 downto 0) := "00100"; -- x20
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constant shnl : std_logic_vector (4 downto 0) := "00101"; -- x28
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constant rotcr : std_logic_vector (4 downto 0) := "00110"; -- x30
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constant shnr : std_logic_vector (4 downto 0) := "00111"; -- x38
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-- index register load/store in address order Beware! this encodes index specifier
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constant ldxl : std_logic_vector (4 downto 0) := "01000"; -- x40
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constant ldyl : std_logic_vector (4 downto 0) := "01010"; -- x50
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constant ldzl : std_logic_vector (4 downto 0) := "01100"; -- x60
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constant ldtl : std_logic_vector (4 downto 0) := "01110"; -- x70
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constant ldxh : std_logic_vector (4 downto 0) := "01001"; -- x48
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constant ldyh : std_logic_vector (4 downto 0) := "01011"; -- x58
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constant ldzh : std_logic_vector (4 downto 0) := "01101"; -- x68
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constant ldth : std_logic_vector (4 downto 0) := "01111"; -- x78
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constant stxl : std_logic_vector (4 downto 0) := "10000"; -- x80
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constant styl : std_logic_vector (4 downto 0) := "10010"; -- x90
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constant stzl : std_logic_vector (4 downto 0) := "10100"; -- xA0
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constant sttl : std_logic_vector (4 downto 0) := "10110"; -- xB0
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constant stxh : std_logic_vector (4 downto 0) := "10001"; -- x88
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constant styh : std_logic_vector (4 downto 0) := "10011"; -- x98
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constant stzh : std_logic_vector (4 downto 0) := "10101"; -- xA8
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constant stth : std_logic_vector (4 downto 0) := "10111"; -- xB8
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constant addix : std_logic_vector (4 downto 0) := "11000"; -- xC0
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constant addiy : std_logic_vector (4 downto 0) := "11010"; -- xD0
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constant addiz : std_logic_vector (4 downto 0) := "11100"; -- xE0
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constant addit : std_logic_vector (4 downto 0) := "11110"; -- xF0
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-- return register save/restore
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constant pop : std_logic_vector (4 downto 0) := "11001"; -- xC8
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constant push : std_logic_vector (4 downto 0) := "11011"; -- xD8
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constant ldsp : std_logic_vector (4 downto 0) := "11101"; -- xE8
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constant stsp : std_logic_vector (4 downto 0) := "11111"; -- xF8
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-- basic signals
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signal accumcar : std_logic_vector (width downto 0); -- accumulator+carry
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alias accum : std_logic_vector (width-1 downto 0) is accumcar(width-1 downto 0);
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alias carrybit : std_logic is accumcar(width);
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signal maskedcarry : std_logic;
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signal pc : std_logic_vector (paddwidth -1 downto 0); -- program counter - 11 bits = 2k
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signal mra : std_logic_vector (maddwidth -1 downto 0); -- memory read address - 12 bits = 4k max
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signal mwa : std_logic_vector (maddwidth -1 downto 0); -- memory write address - 12 bits = 4k max
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signal id1 : std_logic_vector (iwidth -1 downto 0); -- instruction pipeline 1
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signal id2 : std_logic_vector (iwidth -1 downto 0); -- instruction pipeline 2
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alias opcode0 : std_logic_vector (3 downto 0) is idbus (iwidth-1 downto iwidth-4); -- main opcode at pipe0
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alias opcode2 : std_logic_vector (3 downto 0) is id2 (iwidth-1 downto iwidth-4); -- main opcode at pipe2
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signal opcode3 : std_logic_vector (3 downto 0);
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alias Arith : std_logic_vector (1 downto 0) is id2 (iwidth-1 downto iwidth-2);
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alias WithCarry : std_logic is id2(iwidth-4); -- indicates add with carry or subtract with borrow
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alias Minus is id2(iwidth-3); -- indicates subtract
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alias opradd0 : std_logic_vector (maddwidth -3 downto 0) is idbus (maddwidth -3 downto 0); -- operand address at pipe0
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alias opradd2 : std_logic_vector (maddwidth -3 downto 0) is id2 (maddwidth -3 downto 0); -- operand address at pipe2
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alias ind0 : std_logic is idbus(iwidth -6);
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alias ind2 : std_logic is id2(iwidth -6);
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alias jind0 : std_logic is idbus(iwidth -5);
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alias jind2 : std_logic is id2(iwidth -5);
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alias wbena2 : std_logic is id2(iwidth-1);
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alias writeback2 : std_logic is id2(iwidth-5);
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signal wbena3 : std_logic;
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signal writeback3: std_logic;
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alias ireg0 : std_logic_vector(1 downto 0) is idbus(iwidth -7 downto iwidth -8);
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alias ireg2 : std_logic_vector(1 downto 0) is id2(iwidth -7 downto iwidth -8);
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alias offset0 : std_logic_vector (iwidth-10 downto 0) is idbus(iwidth-10 downto 0);
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alias offset2 : std_logic_vector (iwidth-10 downto 0) is id2(iwidth-10 downto 0);
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alias opropcode0 : std_logic_vector (3 downto 0) is idbus(iwidth-5 downto iwidth-8); -- operate opcode at pipe2 alias iopr2 : std_logic_vector (7 downto 0) is id2 (7 downto 0); -- immediate operand at pipe2
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alias liopropcode2 : std_logic_vector (3 downto 0) is id2(iwidth-5 downto iwidth-8); -- operate opcode at pipe2 alias iopr2 : std_logic_vector (7 downto 0) is id2 (7 downto 0); -- immediate operand at pipe2
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alias opropcode2 : std_logic_vector (4 downto 0) is id2(iwidth-5 downto iwidth-9); -- operate opcode at pipe2 alias iopr2 : std_logic_vector (7 downto 0) is id2 (7 downto 0); -- immediate operand at pipe2
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alias idxopcode2 : std_logic_vector (4 downto 0) is id2(iwidth-5 downto iwidth-9); -- index opcode at pipe2 alias iopr2 : std_logic_vector (7 downto 0) is id2 (7 downto 0); -- immediate operand at pipe2
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alias iopr2 : std_logic_vector (7 downto 0) is id2 (7 downto 0); -- immediate operand at pipe2
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signal oprr : std_logic_vector (width -1 downto 0); -- operand register
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signal idx : std_logic_vector (maddwidth -1 downto 0);
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signal idy : std_logic_vector (maddwidth -1 downto 0);
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signal idz : std_logic_vector (maddwidth -1 downto 0);
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signal idt : std_logic_vector (maddwidth -1 downto 0);
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signal idn0 : std_logic_vector (maddwidth -1 downto 0);
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signal maddpipe1 : std_logic_vector (maddwidth -1 downto 0);
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signal maddpipe2 : std_logic_vector (maddwidth -1 downto 0);
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signal maddpipe3 : std_logic_vector (maddwidth -1 downto 0);
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signal nextpc : std_logic_vector (paddwidth -1 downto 0);
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signal pcplus1 : std_logic_vector (paddwidth -1 downto 0);
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signal zero : std_logic;
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signal spw: std_logic_vector (3 downto 0);
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signal spr: std_logic_vector (3 downto 0);
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signal stackdin: std_logic_vector (paddwidth-1 downto 0);
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signal stackdout: std_logic_vector (paddwidth-1 downto 0);
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signal stackwe: std_logic;
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signal dopush: std_logic;
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signal dopop: std_logic;
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function rotcleft(v : std_logic_vector ) return std_logic_vector is
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variable result : std_logic_vector(width downto 0);
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begin
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result(width downto 1) := v(width-1 downto 0);
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result(0) := v(width);
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return result;
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end rotcleft;
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function rotcright(v : std_logic_vector ) return std_logic_vector is
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variable result : std_logic_vector(width downto 0);
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begin
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result(width -1 downto 0) := v(width downto 1);
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result(width) := v(0);
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return result;
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end rotcright;
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begin -- the CPU
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StackRam : entity work.adpram
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generic map (
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width => paddwidth,
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depth => 16
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)
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port map(
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addra => spw,
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addrb => spr,
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clk => clk,
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dina => stackdin,
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-- douta =>
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doutb => stackdout,
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wea => stackwe
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);
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nextpcproc : process (clk, reset, pc, zero, nextpc, id2,
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ind0, ind2, idbus, opcode0, jind0, jind2,
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opcode2, carrybit,pcplus1, stackdout) -- next pc calculation - jump decode
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begin
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pcplus1 <= pc + '1';
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iabus <= nextpc; -- program memory address from combinatorial
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if reset = '1' then -- nextpc since blockram has built in addr register
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nextpc <= (others => '0');
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else
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if (opcode0 = jmp) or (opcode0 = jsr) then
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if jind0 = '1' then -- indirect
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nextpc <= stackdout;
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else -- direct
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nextpc <= idbus(paddwidth -1 downto 0);
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end if;
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elsif
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((opcode2 = jmpnz) and (zero = '0')) or
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((opcode2 = jmpz) and (zero = '1')) or
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((opcode2 = jmpnc) and (carrybit = '0')) or
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((opcode2 = jmpc) and (carrybit = '1')) then
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if jind2 = '1' then -- indirect
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nextpc <= stackdout;
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else -- direct
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nextpc <= id2(paddwidth -1 downto 0);
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end if;
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else
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nextpc <= pcplus1;
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end if; -- opcode = jmp
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end if; -- no reset
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if clk'event and clk = '1' then
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pc <= nextpc;
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id1 <= idbus;
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id2 <= id1;
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if
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((opcode2 = jmpnz) and (zero = '0')) or
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((opcode2 = jmpz) and (zero = '1')) or
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((opcode2 = jmpnc) and (carrybit = '0')) or
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((opcode2 = jmpc) and (carrybit = '1')) or
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(reset = '1') then
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id1 <= (others => '0'); -- on reset or taken conditional jump
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id2 <= (others => '0'); -- fill inst pipeline with two 0s (nop)
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end if;
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writeback3 <= writeback2; -- the writeback bit
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wbena3 <= wbena2; -- determines writeback suitable instructions
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opcode3 <= opcode2; -- for late decode of STA
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end if; -- if clk
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end process nextpcproc;
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mraproc : process (idbus, idx, idy, idz, idt, mra, ind0,
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idn0, ireg0,
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offset0, opcode0, opradd0, clk) -- memory read address generation
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begin
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mradd <= mra;
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case ireg0 is
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when "00" => idn0 <= idx; -- beware! encoded in memory reference _and_ addix,y,z,t
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when "01" => idn0 <= idy;
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when "10" => idn0 <= idz;
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when "11" => idn0 <= idt;
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when others => null;
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end case;
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-- mux
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if ((opcode0 /= opr) and (ind0 = '0')) then
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mra <= "00"&opradd0; -- 10 bit address range for direct access
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else
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mra <= idn0 + ("00000"&offset0); -- 12 bit address range for indirect access (w 7 bit offset)
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end if;
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if clk'event and clk = '1' then
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maddpipe3 <= maddpipe2;
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maddpipe2 <= maddpipe1;
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maddpipe1 <= mra;
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if (opcode0 = lda) or (opcode0 = lor) or (opcode0 = lxor) or (opcode0 = land)
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or (opcode0 = add) or (opcode0 = addc) or (opcode0 = sub) or (opcode0 = subc) then
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mread <= '1';
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else
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mread <= '0';
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end if;
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end if;
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end process mraproc;
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oprrproc : process (clk) -- memory operand register -- could remove to
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begin -- reduce pipelining depth but would impact I/O read
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if clk'event and clk = '1' then -- access time --> not good for larger systems
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oprr <= mibus;
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end if;
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end process oprrproc;
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accumproc : process (clk, accum, carrybit, accumcar, id2, opcode0,
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pcplus1, opcode2, opropcode2, jind0, spw) -- accumulator instruction decode - operate
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begin
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carryflg <= carrybit;
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if accum = x"00" then
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zero <= '1';
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else
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zero <= '0';
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end if;
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maskedcarry <= carrybit and WithCarry;
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if clk'event and clk = '1' then
|
|
case opcode2 is -- memory reference first
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|
when land => accum <= accum and oprr;
|
|
when lor => accum <= accum or oprr;
|
|
when lxor => accum <= accum xor oprr;
|
|
when lda => accum <= oprr;
|
|
|
|
when opr => -- operate
|
|
case liopropcode2 is
|
|
when ldi => accum <= iopr2; -- load immediate byte
|
|
when others => null;
|
|
end case;
|
|
case opropcode2 is
|
|
when rotcl => accumcar <= rotcleft(accumcar); -- rotate left through carry
|
|
when rotcr => accumcar <= rotcright(accumcar); -- rotate right through carry
|
|
when shnl => accumcar(width downto 4) <= accumcar(width-4 downto 0);
|
|
accumcar(width-4 downto 0) <= (others => '0');
|
|
when shnr => accumcar(width-4 downto 0) <= accumcar(width downto 4);
|
|
accumcar(width downto 4) <= (others => '0');
|
|
when pop => accum <= stackdout(width-1 downto 0);
|
|
when stsp => spw <= accum(3 downto 0);
|
|
when ldsp => accum(3 downto 0) <= spw;
|
|
accum(width-1 downto 4) <= (others => '0');
|
|
when others => null;
|
|
end case;
|
|
|
|
case idxopcode2 is
|
|
when ldxl => accum <= idx(width-1 downto 0); -- index operate
|
|
when ldyl => accum <= idy(width-1 downto 0);
|
|
when ldzl => accum <= idz(width-1 downto 0);
|
|
when ldtl => accum <= idt(width-1 downto 0);
|
|
|
|
when stxl => idx(width-1 downto 0) <= accum;
|
|
when styl => idy(width-1 downto 0) <= accum;
|
|
when stzl => idz(width-1 downto 0) <= accum;
|
|
when sttl => idt(width-1 downto 0) <= accum;
|
|
|
|
when ldxh => accum((maddwidth-width)-1 downto 0) <= idx(maddwidth-1 downto width);
|
|
accum(width-1 downto maddwidth-width) <= (others => '0');
|
|
when ldyh => accum((maddwidth-width)-1 downto 0) <= idy(maddwidth-1 downto width);
|
|
accum(width-1 downto maddwidth-width) <= (others => '0');
|
|
when ldzh => accum((maddwidth-width)-1 downto 0) <= idz(maddwidth-1 downto width);
|
|
accum(width-1 downto maddwidth-width) <= (others => '0');
|
|
when ldth => accum((maddwidth-width)-1 downto 0) <= idt(maddwidth-1 downto width);
|
|
accum(width-1 downto maddwidth-width) <= (others => '0');
|
|
|
|
when stxh => idx(maddwidth-1 downto width) <= accum((maddwidth-width)-1 downto 0);
|
|
when styh => idy(maddwidth-1 downto width) <= accum((maddwidth-width)-1 downto 0);
|
|
when stzh => idz(maddwidth-1 downto width) <= accum((maddwidth-width)-1 downto 0);
|
|
when stth => idt(maddwidth-1 downto width) <= accum((maddwidth-width)-1 downto 0);
|
|
|
|
when addix => idx <= maddpipe2; -- share the offset address adder for addix
|
|
when addiy => idy <= maddpipe2; -- same for Y
|
|
when addiz => idz <= maddpipe2; -- same for Z
|
|
when addit => idt <= maddpipe2; -- same for T
|
|
when others => null;
|
|
end case;
|
|
when others => null;
|
|
end case;
|
|
if Arith = "11" then
|
|
if Minus = '0' then
|
|
accumcar <= '0'&accum + oprr + maskedcarry; -- add/addc
|
|
else
|
|
accumcar <= '0'&accum - oprr - maskedcarry; -- sub/subc
|
|
end if;
|
|
end if;
|
|
|
|
if dopush = '1' then
|
|
spw <= spw +1;
|
|
end if;
|
|
if dopop = '1' then
|
|
spw <= spw -1;
|
|
end if;
|
|
|
|
-- if opcode0 = opr then -- this can be done at pipe 0 at the cost of 6 or so slices
|
|
-- if opropcode0 = addix then
|
|
-- idx <= mra;
|
|
-- end if;
|
|
-- if opropcode0 = addiy then
|
|
-- idy <= mra;
|
|
-- end if;
|
|
-- if opropcode0 = addiz then
|
|
-- idz <= mra;
|
|
-- end if;
|
|
-- if opropcode0 = addit then
|
|
-- idt <= mra;
|
|
-- end if;
|
|
-- end if;
|
|
end if; -- clk
|
|
|
|
if opcode0 = jsr then
|
|
stackdin <= pcplus1; -- a jsr (note jsr has priority)
|
|
else
|
|
stackdin(width-1 downto 0) <= accum; -- default push data is accum (and zero top bits)
|
|
stackdin(paddwidth-1 downto width) <=(others => '0');
|
|
end if;
|
|
|
|
if (opcode0 = jsr) or ((opcode2 = opr) and (opropcode2 = push)) then
|
|
stackwe <= '1';
|
|
dopush <= '1';
|
|
else
|
|
stackwe <= '0';
|
|
dopush <= '0';
|
|
end if;
|
|
|
|
if ((opcode0= jmp) and (jind0 = '1')) -- jmp indirect is a return
|
|
or ((opcode2 = opr)and (opropcode2 = pop)) then
|
|
dopop <= '1';
|
|
else
|
|
dopop <= '0';
|
|
end if;
|
|
|
|
spr <= spw -1;
|
|
|
|
end process accumproc;
|
|
|
|
staproc : process (clk, accum, maddpipe3, opcode3, writeback3, wbena3, accumcar, id2) -- sta decode -- not much to do but enable mwrite
|
|
begin
|
|
mobus <= accum;
|
|
mwadd <= maddpipe3; -- address at pipe 3 to match latched accumulator timimg
|
|
if opcode3 = sta or ((writeback3 = '1') and (wbena3 = '1')) then
|
|
mwrite <= '1';
|
|
else
|
|
mwrite <= '0';
|
|
end if;
|
|
end process staproc;
|
|
|
|
end Behavioral;
|