795 lines
23 KiB
VHDL
Executable File
795 lines
23 KiB
VHDL
Executable File
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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library UNISIM;
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use UNISIM.VComponents.all;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.c1
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- dont change these:
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use work.IDROMConst.all;
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-------------------- option selection area ----------------------------
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-------------------- select one card type------------------------------
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use work.@Card@.all;
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--use work.i43_200card.all; -- needs 7i43u.ucf and SP3 200K 144 pin
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--use work.i43_400card.all; -- needs 7i43u.ucf and SP3 400K 144 pin
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--use work.i61_x16card.all; -- needs 7i61u.ucf and SP6 x16 256 pin
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--use work.i61_x25card.all; -- needs 7i61u.ucf and SP6 x25 256 pin
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-----------------------------------------------------------------------
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-------------------- select (or add) one pinout -----------------------
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-- note that all the USB configurations drop the address translation
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-- as the LB Protocol has its own address system
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use work.@Pin@.all;
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-- 48 I/O pinouts for the 7I43
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--use work.PIN_SV8_48.all;
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--use work.PIN_SVSPD6_2_48.all;
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--use work.PIN_SPSVST_7I47_7I65_48.all;
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--use work.PIN_SVSP6_2_48.all;
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--use work.PIN_SVST4_4_48.all;
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--use work.PIN_SVST4_6_48.all;
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--use work.PIN_SVST2_4_7I47_48.all;
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--use work.PIN_SVST4_12_48.all ;
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--use work.PIN_SVSSP4_6_7I46_48.all;
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--use work.PIN_SVST2_4_7I47_48.all ;
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--use work.PIN_SVUA4_8_48.all;
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--use work.PIN_SVSS4_8_48.all;
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--use work.PIN_SVSI8_48.all;
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--use work.PIN_SVFA8_48.all;
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--use work.PIN_SVTW4_24_24_48.all ;
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--use work.PIN_SVTP4_7I39_48.all;
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--use work.PIN_SVST6_6_7I48_48.all;
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--use work.PIN_SVRM6_48.all;
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--use work.PIN_SISVST6_2_3_7I47_48.all;
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--use work.PIN_BOSSV.all ;
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--use work.PIN_Enslavko_48.all;
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-- 96 I/O pinouts for 7I61:
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--use work.PIN_SV16_96.all;
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--use work.PIN_SVST8_8_96.all;
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--use work.PIN_SVST8_24_96.all;
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--use work.PIN_SVSTSP8_12_6_96.all;
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--use work.PIN_SV12_2X7I49_96.all;
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--use work.PIN_SVST12_12_2X7I48_2X7I47_96.all;
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----------------------------------------------------------------------
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-- dont change anything below unless you know what you are doing -----
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entity TopUSBHostMot2 is -- for 7I43/7I61 in USB mode
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generic
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(
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ThePinDesc: PinDescType := PinDesc;
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TheModuleID: ModuleIDType := ModuleID;
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PWMRefWidth: integer := 13; -- PWM resolution is PWMRefWidth-1 bits
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IDROMType: integer := 3;
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UseIRQLogic: boolean := true;
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UseWatchDog: boolean := true;
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OffsetToModules: integer := 64;
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OffsetToPinDesc: integer := 448;
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BusWidth: integer := 32;
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AddrWidth: integer := 16;
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InstStride0: integer := 4; -- instance stride 0 = 4 bytes = 1 x 32 bit
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InstStride1: integer := 64; -- instance stride 1 = 64 bytes = 16 x 32 bit registers
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RegStride0: integer := 256; -- register stride 0 = 256 bytes = 64 x 32 bit registers
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RegStride1: integer := 256 -- register stride 1 = 256 bytes - 64 x 32 bit
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);
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Port ( CLK : in std_logic;
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LEDS : out std_logic_vector(LEDCount -1 downto 0);
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IOBITS : inout std_logic_vector(IOWidth -1 downto 0);
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DATABUS : inout std_logic_vector(7 downto 0);
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USB_WRITE : out std_logic;
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USB_RD : out std_logic;
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USB_TXE : in std_logic;
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USB_RXF : in std_logic;
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RECONFIG : out std_logic;
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HRECONFIG : out std_logic;
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PARACONFIG : out std_logic;
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SPICLK : out std_logic;
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SPIIN : in std_logic;
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SPIOUT : out std_logic;
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SPICS : out std_logic
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);
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end TopUSBHostMot2;
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architecture Behavioral of TopUSBHostMot2 is
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-- GPIO interface signals
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signal ReconfigSel : std_logic;
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signal ReConfigreg : std_logic := '0';
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signal LoadSPIReg : std_logic;
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signal ReadSPIReg : std_logic;
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signal LoadSPICS : std_logic;
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signal ReadSPICS : std_logic;
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signal LoadUSBDataReg : std_logic;
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signal ReadUSBData : std_logic;
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signal LoadUSBControlReg : std_logic;
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signal ReadUSBStatus : std_logic;
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signal USBDataReg : std_logic_vector(7 downto 0);
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signal USBContReg : std_logic_vector(2 downto 0) := "011";
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alias USB_RdReg : std_logic is USBContReg(0);
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alias USB_WriteReg : std_logic is USBContReg(1);
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alias USB_TSEn : std_logic is USBContReg(2);
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signal iabus : std_logic_vector(10 downto 0); -- program address bus (changed to 11 bits 8/2010)
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signal idbus : std_logic_vector(15 downto 0); -- program data bus
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signal mradd : std_logic_vector(11 downto 0); -- memory read address
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signal ioradd : std_logic_vector(11 downto 0); -- I/O read address
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signal mwadd : std_logic_vector(11 downto 0); -- memory write address
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signal mibus : std_logic_vector(7 downto 0); -- memory data in bus
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signal mobus : std_logic_vector(7 downto 0); -- memory data out bus
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signal mwrite : std_logic; -- memory write signal
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signal mread : std_logic; -- memory read signal
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signal pagedmradd : std_logic_vector(10 downto 0);
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signal pagedmwadd : std_logic_vector(10 downto 0);
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signal pagedmwrite : std_logic;
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signal mibus_ram : std_logic_vector(7 downto 0); -- memory data in bus RAM
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signal mibus_io : std_logic_vector(7 downto 0); -- memory data in bus IO
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alias wiosel : std_logic is mwadd(10);
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alias riosel : std_logic is ioradd(10);
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signal WriteLEDs : std_logic;
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Signal LocalLEDs : std_logic_vector(7 downto 0);
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signal ReadExtData : std_logic;
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signal WriteExtData : std_logic;
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signal ReadExtAddLow : std_logic;
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signal WriteExtAddLow : std_logic;
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signal ReadExtAddHigh : std_logic;
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signal WriteExtAddHigh : std_logic;
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signal StartExtRead : std_logic;
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signal StartExtReadRQ : std_logic;
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signal StartExtReadDel : std_logic_vector(1 downto 0);
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signal StartExtWrite : std_logic;
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signal StartExtWriteRQ : std_logic;
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signal StartExtWriteDel : std_logic_vector(1 downto 0);
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signal ReadEIOCookie : std_logic;
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signal HM2ReadBuffer0 : std_logic_vector(31 downto 0);
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signal HM2WriteBuffer0 : std_logic_vector(31 downto 0);
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signal HM2ReadBuffer1 : std_logic_vector(31 downto 0);
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signal HM2WriteBuffer1 : std_logic_vector(31 downto 0);
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signal Write32 : std_logic;
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signal Read32 : std_logic;
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signal ExtAddress0: std_logic_vector(15 downto 0);
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signal ExtAddress1: std_logic_vector(15 downto 0);
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signal HM2obus : std_logic_vector(31 downto 0);
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signal wseladd: std_logic_vector(7 downto 0);
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signal rseladd: std_logic_vector(7 downto 0);
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signal clk0fx : std_logic;
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signal clk0 : std_logic;
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signal procclk : std_logic;
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signal clk1fx : std_logic;
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signal clk1 : std_logic;
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signal hm2fastclock : std_logic;
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constant EIOCookie: std_logic_vector(7 downto 0) := x"EE";
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begin
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ahostmot2: entity work.HostMot2
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generic map (
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thepindesc => ThePinDesc,
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themoduleid => TheModuleID,
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idromtype => IDROMType,
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sepclocks => SepClocks,
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onews => OneWS,
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useirqlogic => UseIRQLogic,
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pwmrefwidth => PWMRefWidth,
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usewatchdog => UseWatchDog,
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offsettomodules => OffsetToModules,
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offsettopindesc => OffsetToPinDesc,
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clockhigh => ClockHigh,
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clockmed => ClockMed,
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clocklow => ClockLow,
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boardnamelow => BoardNameLow,
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boardnamehigh => BoardNameHigh,
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fpgasize => FPGASize,
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fpgapins => FPGAPins,
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ioports => IOPorts,
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iowidth => IOWidth,
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liowidth => LIOWidth,
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portwidth => PortWidth,
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buswidth => BusWidth,
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addrwidth => AddrWidth,
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inststride0 => InstStride0,
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inststride1 => InstStride1,
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regstride0 => RegStride0,
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regstride1 => RegStride1,
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ledcount => LEDCount )
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port map (
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ibus => HM2WriteBuffer1,
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obus => HM2obus,
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addr => ExtAddress1(15 downto 2),
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readstb => Read32,
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writestb => Write32,
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clklow => CLK,
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clkmed => procclk,
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clkhigh => hm2fastclock,
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-- int => INT,
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leds => LEDS,
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iobits => IOBITS
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);
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Is7I61: if (BoardNameHigh = BoardName7i61) generate
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ClockMult0 : DCM
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generic map (
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CLKDV_DIVIDE => 2.0,
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CLKFX_DIVIDE => 4,
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CLKFX_MULTIPLY =>2, -- 4/2 for 100 MHz
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CLKIN_DIVIDE_BY_2 => FALSE,
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CLKIN_PERIOD => 19.5,
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CLKOUT_PHASE_SHIFT => "NONE",
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CLK_FEEDBACK => "1X",
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DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
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DFS_FREQUENCY_MODE => "LOW",
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DLL_FREQUENCY_MODE => "LOW",
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DUTY_CYCLE_CORRECTION => TRUE,
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FACTORY_JF => X"C080",
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PHASE_SHIFT => 0,
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STARTUP_WAIT => FALSE)
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port map (
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CLK0 => clk0, --
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CLKFB => clk0, -- DCM clock feedback
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CLKFX => clk0fx,
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CLKIN => hm2fastclock, -- cascaded clock input (from IBUFG, BUFG or DCM) fails on spartan 3
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PSCLK => '0', -- Dynamic phase adjust clock input
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PSEN => '0', -- Dynamic phase adjust enable input
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PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
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RST => '0' -- DCM asynchronous reset input
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);
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BUFG0_inst : BUFG
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port map (
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O => procclk, -- Clock buffer output
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I => clk0fx -- Clock buffer input
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);
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ClockMult1 : DCM
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generic map (
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CLKDV_DIVIDE => 2.0,
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CLKFX_DIVIDE => 2,
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CLKFX_MULTIPLY =>8, -- 8/2 for 200 MHz
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CLKIN_DIVIDE_BY_2 => FALSE,
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CLKIN_PERIOD => 19.5,
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CLKOUT_PHASE_SHIFT => "NONE",
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CLK_FEEDBACK => "1X",
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DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
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DFS_FREQUENCY_MODE => "LOW",
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DLL_FREQUENCY_MODE => "LOW",
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DUTY_CYCLE_CORRECTION => TRUE,
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FACTORY_JF => X"C080",
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PHASE_SHIFT => 0,
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STARTUP_WAIT => FALSE)
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port map (
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CLK0 => clk1, --
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CLKFB => clk1, -- DCM clock feedback
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CLKFX => clk1fx,
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CLKIN => CLK, -- Clock input (from IBUFG, BUFG or DCM)
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PSCLK => '0', -- Dynamic phase adjust clock input
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PSEN => '0', -- Dynamic phase adjust enable input
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PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
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RST => '0' -- DCM asynchronous reset input
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);
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BUFG1_inst : BUFG
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port map (
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O => hm2fastclock, -- Clock buffer output
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I => clk1fx -- Clock buffer input
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);
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-- End of DCM_inst instantiation
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end generate;
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Isnot7I61: if (BoardNameHigh /= BoardName7i61) generate
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ClockMult0 : DCM
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generic map (
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CLKDV_DIVIDE => 2.0,
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CLKFX_DIVIDE => 2,
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CLKFX_MULTIPLY =>3, -- 3/2 FOR 75 MHz
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CLKIN_DIVIDE_BY_2 => FALSE,
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CLKIN_PERIOD => 19.5,
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CLKOUT_PHASE_SHIFT => "NONE",
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CLK_FEEDBACK => "1X",
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DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
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DFS_FREQUENCY_MODE => "LOW",
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DLL_FREQUENCY_MODE => "LOW",
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DUTY_CYCLE_CORRECTION => TRUE,
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FACTORY_JF => X"C080",
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PHASE_SHIFT => 0,
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STARTUP_WAIT => FALSE)
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port map (
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CLK0 => clk0, --
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CLKFB => clk0, -- DCM clock feedback
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CLKFX => clk0fx,
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CLKIN => CLK, -- External clock input (from IBUFG, BUFG or DCM) not possible on SP6 7I61
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PSCLK => '0', -- Dynamic phase adjust clock input
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PSEN => '0', -- Dynamic phase adjust enable input
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PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
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RST => '0' -- DCM asynchronous reset input
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);
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BUFG0_inst : BUFG
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port map (
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O => procclk, -- Clock buffer output
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I => clk0fx -- Clock buffer input
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);
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ClockMult1 : DCM
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generic map (
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CLKDV_DIVIDE => 2.0,
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CLKFX_DIVIDE => 2,
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CLKFX_MULTIPLY =>4, -- 4/2 for 100 MHz
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CLKIN_DIVIDE_BY_2 => FALSE,
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CLKIN_PERIOD => 19.5,
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CLKOUT_PHASE_SHIFT => "NONE",
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CLK_FEEDBACK => "1X",
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DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
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DFS_FREQUENCY_MODE => "LOW",
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DLL_FREQUENCY_MODE => "LOW",
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DUTY_CYCLE_CORRECTION => TRUE,
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FACTORY_JF => X"C080",
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PHASE_SHIFT => 0,
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STARTUP_WAIT => FALSE)
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port map (
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CLK0 => clk1, --
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CLKFB => clk1, -- DCM clock feedback
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CLKFX => clk1fx,
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CLKIN => CLK, -- Clock input (from IBUFG, BUFG or DCM)
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PSCLK => '0', -- Dynamic phase adjust clock input
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PSEN => '0', -- Dynamic phase adjust enable input
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PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
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RST => '0' -- DCM asynchronous reset input
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);
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BUFG1_inst : BUFG
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port map (
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O => hm2fastclock, -- Clock buffer output
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I => clk1fx -- Clock buffer input
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);
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-- End of DCM_inst instantiation
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end generate;
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asimplspi: entity work.simplespi8
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generic map
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(
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buswidth => 8,
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div => 2, -- for divide by 3
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bits => 8
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)
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port map
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(
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clk => procclk,
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ibus => mobus,
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obus => mibus_io,
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loaddata => LoadSPIReg,
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readdata => ReadSPIReg,
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loadcs => LoadSPICS,
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readcs => ReadSPICS,
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spiclk => SPIClk,
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spiin => SPIIn,
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spiout => SPIOut,
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spics =>SPICS
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);
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processor: entity work.DumbAss8sq
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port map (
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clk => procclk,
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reset => '0',
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iabus => iabus, -- program address bus
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idbus => idbus, -- program data bus
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mradd => mradd, -- memory read address
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mwadd => mwadd, -- memory write address
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mibus => mibus, -- memory data in bus
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mobus => mobus, -- memory data out bus
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mwrite => mwrite, -- memory write signal
|
|
mread => mread -- memory read signal
|
|
-- carryflg => -- carry flag
|
|
);
|
|
|
|
|
|
|
|
programROM : entity work.usbrom
|
|
port map(
|
|
addr => iabus,
|
|
clk => procclk,
|
|
din => x"0000",
|
|
dout => idbus,
|
|
we => '0'
|
|
);
|
|
|
|
DataRam : entity work.usbram
|
|
port map(
|
|
addra => pagedmwadd,
|
|
addrb => pagedmradd,
|
|
clk => procclk,
|
|
dina => mobus,
|
|
-- douta =>
|
|
doutb => mibus_ram,
|
|
wea => pagedmwrite
|
|
);
|
|
|
|
MiscProcFixes : process (procclk, mradd, mwadd, mwrite) -- need to match BlockRAM address pipeline register for I/O
|
|
begin -- and map memory/IO so 1K IO,1K memory, 1K IO, 1K memory
|
|
if rising_edge(procclk) then
|
|
ioradd <= mradd;
|
|
end if;
|
|
pagedmradd <= mradd(11) & mradd(9 downto 0);
|
|
pagedmwadd <= mwadd(11) & mwadd(9 downto 0);
|
|
pagedmwrite <= mwrite and mwadd(10);
|
|
end process;
|
|
|
|
ram_iomux : process (ioradd(10),mibus_ram,mibus_io)
|
|
begin
|
|
if ioradd(10) = '1' then
|
|
mibus <= mibus_ram;
|
|
else
|
|
mibus <= mibus_io;
|
|
end if;
|
|
end process;
|
|
|
|
iodecode: process(ioradd,mwadd,mwrite,rseladd,wseladd,extaddress0,writeextdata,readextdata)
|
|
begin
|
|
rseladd <= ioradd(7 downto 0);
|
|
wseladd <= mwadd(7 downto 0);
|
|
|
|
if rseladd (7 downto 3) = "01100" and riosel = '0' then -- 0x60 through 0x67
|
|
ReadExtData <= '1';
|
|
else
|
|
ReadExtData <= '0';
|
|
end if;
|
|
|
|
if wseladd (7 downto 3) = "01100" and wiosel = '0' and mwrite = '1' then -- 0x60 through 0x67
|
|
WriteExtData <= '1';
|
|
else
|
|
WriteExtData <= '0';
|
|
end if;
|
|
|
|
if rseladd = x"68" and riosel = '0' then
|
|
ReadExtAddLow <= '1';
|
|
else
|
|
ReadExtAddLow <= '0';
|
|
end if;
|
|
|
|
if wseladd = x"68" and wiosel = '0' and mwrite= '1' then
|
|
WriteExtAddLow <= '1';
|
|
else
|
|
WriteExtAddLow <= '0';
|
|
end if;
|
|
|
|
if rseladd = x"69" and riosel = '0' then
|
|
ReadExtAddHigh <= '1';
|
|
else
|
|
ReadExtAddHigh <= '0';
|
|
end if;
|
|
|
|
if wseladd = x"69" and wiosel = '0' and mwrite= '1' then
|
|
WriteExtAddHigh <= '1';
|
|
else
|
|
WriteExtAddHigh <= '0';
|
|
end if;
|
|
|
|
if wseladd = x"6D" and wiosel = '0' and mwrite = '1' then
|
|
StartExtRead <= '1';
|
|
else
|
|
StartExtRead <= '0';
|
|
end if;
|
|
|
|
if wseladd = x"6E" and wiosel = '0' and mwrite= '1' then
|
|
StartExtWrite <= '1';
|
|
else
|
|
StartExtWrite <= '0';
|
|
end if;
|
|
|
|
if rseladd = x"6F" and riosel = '0' then
|
|
ReadEIOCookie <= '1';
|
|
else
|
|
ReadEIOCookie <= '0';
|
|
end if;
|
|
|
|
if wseladd = x"7A" and wiosel = '0' and mwrite = '1'then
|
|
WriteLEDs <= '1';
|
|
else
|
|
WriteLEDs <= '0';
|
|
end if;
|
|
|
|
if wseladd = x"7B" and wiosel = '0' and mwrite = '1'then
|
|
LoadUSBControlReg <= '1';
|
|
else
|
|
LoadUSBControlReg <= '0';
|
|
end if;
|
|
|
|
if rseladd = x"7B" and riosel = '0' then
|
|
ReadUSBStatus <= '1';
|
|
else
|
|
ReadUSBStatus <= '0';
|
|
end if;
|
|
|
|
if wseladd = x"7C" and wiosel = '0' and mwrite = '1'then
|
|
LoadUSBDataReg <= '1';
|
|
else
|
|
LoadUSBDataReg <= '0';
|
|
end if;
|
|
|
|
if rseladd = x"7C" and riosel = '0' then
|
|
ReadUSBData <= '1';
|
|
else
|
|
ReadUSBData <= '0';
|
|
end if;
|
|
|
|
if wseladd = x"007D" and wiosel = '0' and mwrite = '1' then
|
|
LoadSPICS <= '1';
|
|
else
|
|
LoadSPICS <= '0';
|
|
end if;
|
|
|
|
if rseladd = x"007D" and riosel = '0' then
|
|
ReadSPICS <= '1';
|
|
else
|
|
ReadSPICS <= '0';
|
|
end if;
|
|
|
|
if wseladd = x"007E" and wiosel = '0' and mwrite = '1'then
|
|
LoadSPIReg <= '1';
|
|
else
|
|
LoadSPIReg <= '0';
|
|
end if;
|
|
|
|
if rseladd = x"007E" and riosel = '0' then
|
|
ReadSPIReg <= '1';
|
|
else
|
|
ReadSPIReg <= '0';
|
|
end if;
|
|
|
|
if ExtAddress0 = x"7F7F" and WriteExtData = '1' and wiosel = '0' and mwrite = '1' then
|
|
ReconfigSel <= '1';
|
|
else
|
|
ReconfigSel <= '0';
|
|
end if;
|
|
|
|
end process iodecode;
|
|
|
|
doreconfig: process (procclk,ReConfigreg)
|
|
begin
|
|
if rising_edge(procclk) then
|
|
if ReconfigSel = '1' then
|
|
if mobus = x"5A" then
|
|
ReConfigreg <= '1';
|
|
end if;
|
|
end if;
|
|
end if;
|
|
RECONFIG <= not ReConfigreg;
|
|
HRECONFIG <= not ReConfigreg; -- for 7I43H
|
|
end process doreconfig;
|
|
|
|
HM2InterfaceShim: process (procclk,CLK,startextreaddel,
|
|
startextwritedel,readextdata,rseladd,
|
|
HM2ReadBuffer1,extaddress0,readextaddhigh,
|
|
extaddress0,readeiocookie,readextaddlow)
|
|
begin
|
|
if rising_edge(procclk) then
|
|
if WriteLEDS = '1' then
|
|
LocalLEDs <= mobus;
|
|
end if;
|
|
|
|
HM2ReadBuffer1 <= HM2ReadBuffer0;
|
|
if WriteExtData = '1' then
|
|
case wseladd(1 downto 0) is
|
|
when "00" => HM2WriteBuffer0( 7 downto 0) <= mobus;
|
|
when "01" => HM2WriteBuffer0(15 downto 8) <= mobus;
|
|
when "10" => HM2WriteBuffer0(23 downto 16) <= mobus;
|
|
when "11" => HM2WriteBuffer0(31 downto 24) <= mobus;
|
|
when others => null;
|
|
end case;
|
|
end if;
|
|
|
|
if StartExtRead = '1' then -- set read request - this is to sync processor I/O to
|
|
StartExtReadRq <= '1'; -- slower HM2 base clock
|
|
end if;
|
|
if StartExtWrite = '1' then -- set write request - this is to sync processor I/O to
|
|
StartExtWriteRq <= '1'; -- slower HM2 base clock
|
|
end if;
|
|
|
|
if WriteExtAddLow = '1' then
|
|
ExtAddress0(7 downto 0) <= mobus;
|
|
end if;
|
|
if WriteExtAddHigh = '1' then
|
|
ExtAddress0(15 downto 8) <= mobus;
|
|
end if;
|
|
|
|
end if; -- procclk
|
|
|
|
if rising_edge(CLK) then
|
|
HM2WriteBuffer1 <= HM2WriteBuffer0;
|
|
ExtAddress1 <= ExtAddress0;
|
|
StartExtReadDel <= StartExtReadDel(0) & StartExtReadRq;
|
|
StartExtWriteDel <= StartExtWriteDel(0) & StartExtWriteRq;
|
|
if Read32 = '1' then
|
|
HM2ReadBuffer0 <= HM2OBus;
|
|
end if;
|
|
end if;
|
|
|
|
if StartExtReadDel = "11" then
|
|
Read32 <= '1';
|
|
else
|
|
Read32 <= '0';
|
|
end if;
|
|
|
|
if StartExtWriteDel = "11" then
|
|
Write32 <= '1';
|
|
else
|
|
Write32 <= '0';
|
|
end if;
|
|
|
|
if StartExtReadDel(1) = '1' then -- asynchronous clear read request
|
|
StartExtReadRq <= '0';
|
|
end if;
|
|
|
|
if StartExtWriteDel(1) = '1' then -- asynchronous clear write request
|
|
StartExtWriteRq <= '0';
|
|
end if;
|
|
|
|
mibus_io <= "ZZZZZZZZ";
|
|
|
|
if ReadExtData = '1' then
|
|
case rseladd(1 downto 0) is
|
|
when "00" => mibus_io <= HM2ReadBuffer1( 7 downto 0);
|
|
when "01" => mibus_io <= HM2ReadBuffer1(15 downto 8);
|
|
when "10" => mibus_io <= HM2ReadBuffer1(23 downto 16);
|
|
when "11" => mibus_io <= HM2ReadBuffer1(31 downto 24);
|
|
when others => null;
|
|
end case;
|
|
end if;
|
|
|
|
if ReadExtAddLow = '1' then
|
|
mibus_io <= ExtAddress0( 7 downto 0);
|
|
end if;
|
|
if ReadExtAddHigh = '1' then
|
|
mibus_io <= ExtAddress0(15 downto 8);
|
|
end if;
|
|
|
|
if ReadEIOCookie = '1' then
|
|
mibus_io <= EIOCookie;
|
|
end if;
|
|
-- LEDS <= HM2WriteBuffer1(7 downto 0); -- debug kludge
|
|
end process;
|
|
|
|
USBInterfaceDrive: process (procclk, USBDataReg, DATABUS, USB_TSEn,
|
|
ReadUSBData, ReadUSBStatus, USB_RXF, USB_TXE)
|
|
begin
|
|
|
|
DATABUS <= "ZZZZZZZZ";
|
|
if USB_TSEn = '1' then
|
|
DATABUS <= USBDataReg;
|
|
end if;
|
|
|
|
mibus_io <= "ZZZZZZZZ";
|
|
if ReadUSBData = '1' and ReadUSBStatus = '0' then
|
|
mibus_io <= DATABUS;
|
|
end if;
|
|
|
|
if ReadUSBStatus = '1' and ReadUSBData = '0' then
|
|
mibus_io(0) <= USB_RXF; -- active low receiver has data
|
|
mibus_io(1) <= USB_TXE; -- active low xmit buffer has space
|
|
mibus_io(7 downto 2) <= "101010";
|
|
end if;
|
|
|
|
if rising_edge(procclk) then
|
|
if LoadUSBControlReg = '1' then
|
|
USBContReg <= mobus(2 downto 0);
|
|
end if;
|
|
|
|
if LoadUSBDataReg = '1' then
|
|
USBDataReg <= mobus;
|
|
end if;
|
|
|
|
end if;
|
|
USB_RD <= USB_RdReg;
|
|
USB_WRITE <= USB_WriteReg;
|
|
-- LEDS <= not LocalLEDs; -- debug kludge
|
|
-- LEDS <= not ExtAddress0(7 downto 0); -- debug kludge
|
|
-- LEDS <= not ExtAddress0(15 downto 8); -- debug kludge
|
|
-- LEDS <= not HM2WriteBuffer0(7 downto 0); -- debug kludge
|
|
PARACONFIG <= '0';
|
|
end process USBInterfaceDrive;
|
|
|
|
|
|
end Behavioral;
|