178 lines
5.7 KiB
VHDL
Executable File
178 lines
5.7 KiB
VHDL
Executable File
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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entity wordpr is
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generic (
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size : integer;
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buswidth : integer
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);
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port (
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clear: in STD_LOGIC;
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clk: in STD_LOGIC;
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ibus: in STD_LOGIC_VECTOR (buswidth-1 downto 0);
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obus: out STD_LOGIC_VECTOR (buswidth-1 downto 0);
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loadport: in STD_LOGIC;
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loadddr: in STD_LOGIC;
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loadaltdatasrc: in STD_LOGIC;
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loadopendrainmode: in STD_LOGIC;
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loadinvert: in STD_LOGIC;
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readddr: in STD_LOGIC;
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portdata: out STD_LOGIC_VECTOR (size-1 downto 0);
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altdata: in STD_LOGIC_VECTOR (size-1 downto 0)
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);
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end wordpr;
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architecture behavioral of wordpr is
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signal outreg: std_logic_vector (size-1 downto 0);
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signal ddrreg: std_logic_vector (size-1 downto 0):= (others => '0');
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signal tsoutreg: std_logic_vector (size-1 downto 0);
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signal opendrainsel: std_logic_vector (size-1 downto 0):= (others => '0');
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signal altdatasel: std_logic_vector (size-1 downto 0):= (others => '0');
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signal invertsel: std_logic_vector (size-1 downto 0):= (others => '0') ;
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signal tdata: std_logic_vector (size-1 downto 0);
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signal tddr: std_logic_vector (size-1 downto 0);
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begin
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awordioport: process (
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clk,
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ibus,
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loadport,
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loadddr,
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readddr,
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outreg,
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ddrreg,
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altdatasel,
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invertsel,
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altdata,
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tdata,
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tsoutreg,
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opendrainsel)
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begin
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if rising_edge(clk) then
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if loadport = '1' then
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outreg <= ibus(size-1 downto 0);
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end if;
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if loadddr = '1' then
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ddrreg <= ibus(size-1 downto 0);
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end if;
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if loadaltdatasrc = '1' then
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altdatasel <= ibus(size-1 downto 0);
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end if;
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if loadopendrainmode = '1' then
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opendrainsel <= ibus(size-1 downto 0);
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end if;
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if loadinvert = '1' then
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invertsel <= ibus(size-1 downto 0);
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end if;
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if clear = '1' then
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ddrreg <= (others => '0');
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opendrainsel <= (others => '0');
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end if;
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end if; -- clk
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for i in 0 to size-1 loop
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if altdatasel(i) = '0' then
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if invertsel(i) = '0' then -- normal output data, normal outputs can be inverted
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tdata(i) <= outreg(i);
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else
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tdata(i) <= not outreg(i);
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end if;
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else
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if invertsel(i) = '0' then -- alternate output data, alternate outputs can be inverted
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tdata(i) <= altdata(i);
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else
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tdata(i) <= not altdata(i);
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end if;
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end if;
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if opendrainsel(i) = '0' then -- normal DDR
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if (ddrreg(i) = '1') then
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tsoutreg(i) <= tdata(i);
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else
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tsoutreg(i) <= 'Z';
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end if;
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else
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if tdata(i) = '0' then -- open drain option = active pulldown
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tsoutreg(i) <= '0';
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else
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tsoutreg(i) <= 'Z';
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end if;
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end if;
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end loop;
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portdata <= tsoutreg;
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obus <= (others => 'Z');
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if readddr = '1' then
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obus(size-1 downto 0) <= ddrreg;
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obus(buswidth -1 downto size) <= (others => '0');
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end if;
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end process;
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end behavioral;
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