399 lines
12 KiB
VHDL
Executable File
399 lines
12 KiB
VHDL
Executable File
library IEEE;
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use IEEE.std_logic_1164.ALL;
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use IEEE.std_logic_ARITH.ALL;
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use IEEE.std_logic_UNSIGNED.ALL;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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entity qcounterd is
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generic (
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buswidth : integer := 32
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);
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port (
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obus: out std_logic_vector (buswidth-1 downto 0);
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ibus: in std_logic_vector (buswidth-1 downto 0);
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quada: in std_logic;
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quadb: in std_logic;
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index: in std_logic;
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loadccr: in std_logic;
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readccr: in std_logic;
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readcount: in std_logic;
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countclear: in std_logic;
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timestamp: in std_logic_vector (15 downto 0);
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indexmask: in std_logic;
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filterrate: in std_logic;
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timer : in std_logic;
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timerenable : in std_logic;
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clk: in std_logic
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);
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end qcounterd;
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architecture behavioral of qcounterd is
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signal count: std_logic_vector (15 downto 0);
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signal up: std_logic;
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signal down: std_logic;
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signal countlatch: std_logic_vector (15 downto 0);
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signal timestamplatch: std_logic_vector (15 downto 0);
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signal sampleddata: std_logic_vector (31 downto 0);
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signal sampledcont: std_logic_vector (31 downto 0);
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signal quadadel: std_logic;
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signal quada1: std_logic;
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signal quada2: std_logic;
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signal quadacnt: std_logic_vector (3 downto 0);
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signal quadafilt: std_logic;
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signal quadbdel: std_logic;
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signal quadb1: std_logic;
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signal quadb2: std_logic;
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signal quadbcnt: std_logic_vector (3 downto 0);
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signal quadbfilt: std_logic;
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signal indexdel: std_logic;
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signal index1: std_logic;
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signal index2: std_logic;
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signal indexdet: std_logic;
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signal indexcnt: std_logic_vector (3 downto 0);
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signal indexfilt: std_logic;
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signal qcountup: std_logic;
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signal qcountdown: std_logic;
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signal udcountup: std_logic;
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signal udcountdown: std_logic;
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signal doclear: std_logic;
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signal clearonindex: std_logic; -- ccr register bits...
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signal latchonindex:std_logic;
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signal justonce: std_logic;
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signal abgateindex: std_logic;
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signal indexsrc: std_logic;
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signal quadfilter: std_logic;
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signal countermode: std_logic;
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signal quaderror: std_logic;
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signal indexpol: std_logic;
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signal fixedindexmask: std_logic;
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signal indexmaskpol: std_logic;
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signal useindexmask: std_logic;
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signal abmaskpol: std_logic;
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signal flimit: std_logic_vector(3 downto 0);
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signal dtimer: std_logic;
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signal sample: std_logic;
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begin
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aqcounter: process (clk,abgateindex, indexpol, indexdel, abmaskpol,
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quadadel, quadbdel, indexmaskpol, indexmask,
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quadfilter, countermode, doclear, quada2, dtimer,
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quada1, quadb2, quadb1, index1, index2, timer,timerenable,
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useindexmask, readcount, timestamplatch, count,
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readccr, countlatch, quaderror, justonce, qcountdown,
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clearonindex, latchonindex, fixedindexmask, qcountup,
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udcountup,udcountdown,sampledcont,sampleddata)
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begin
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-- new index logic 02/09/2006 PCW
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if abgateindex = '0' then -- not gated by A,B
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if indexpol = '1' then
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indexsrc <= indexdel;
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else
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indexsrc <= not indexdel;
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end if;
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else -- gated by A,B
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if indexpol = '1' then -- normal index
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if abmaskpol = '1' then
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indexsrc <= quadadel and quadbdel and indexdel; -- enable by A,B high
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else
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indexsrc <= (not (quadadel or quadbdel)) and indexdel; -- enable by A,B low
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end if;
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else -- inverted index
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if abmaskpol = '1' then
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indexsrc <= quadadel and quadbdel and (not indexdel); -- enable by A,B high
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else
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indexsrc <= (not (quadadel or quadbdel)) and (not indexdel);-- enable by A,B low
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end if;
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end if;
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end if;
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if indexmaskpol = '1' then
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fixedindexmask <= indexmask;
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else
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fixedindexmask <= not indexmask;
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end if;
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if quadfilter = '1' then
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flimit <= "1111";
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else
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flimit <= "0011";
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end if;
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if countermode = '0' and doclear = '0' and (
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(quada2 = '0' and quada1 = '1' and quadb2 = '0' and quadb1 = '0') or
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(quada2 = '0' and quada1 = '0' and quadb2 = '1' and quadb1 = '0') or
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(quada2 = '1' and quada1 = '1' and quadb2 = '0' and quadb1 = '1') or
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(quada2 = '1' and quada1 = '0' and quadb2 = '1' and quadb1 = '1')) then
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qcountup <= '1';
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else
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qcountup <= '0';
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end if;
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if (countermode = '1' and doclear = '0' and
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quadb2 = '1' and quada2 = '0' and quada1 = '1') then -- up down mode: count up on rising edge of A when B is high
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udcountup <= '1';
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else
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udcountup <= '0';
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end if;
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if countermode = '0' and doclear = '0' and (
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(quada2 = '0' and quada1 = '0' and quadb2 = '0' and quadb1 = '1') or
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(quada2 = '0' and quada1 = '1' and quadb2 = '1' and quadb1 = '1') or
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(quada2 = '1' and quada1 = '0' and quadb2 = '0' and quadb1 = '0') or
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(quada2 = '1' and quada1 = '1' and quadb2 = '1' and quadb1 = '0')) then
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qcountdown <= '1';
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else
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qcountdown <= '0';
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end if;
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if (countermode = '1' and doclear = '0' and
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quadb2 = '0' and quada2 = '0' and quada1 = '1') then
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udcountdown <= '1';
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else
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udcountdown <= '0';
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end if;
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if rising_edge(clk) then
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quadadel <= quada;
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quada1 <= quadafilt;
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quada2 <= quada1;
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quadbdel <= quadb;
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quadb1 <= quadbfilt;
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quadb2 <= quadb1;
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indexdel <= index;
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index1 <= indexfilt;
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index2 <= index1;
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if filterrate = '1' then
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-- deadended counter for A input filter --
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if (quadadel = '1') and (quadacnt < flimit) then
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quadacnt <= quadacnt + 1;
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end if;
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if (quadadel = '0') and (quadacnt /= 0) then
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quadacnt <= quadacnt -1;
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end if;
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if quadacnt >= flimit then
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quadafilt<= '1';
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end if;
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if quadacnt = 0 then
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quadafilt<= '0';
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end if;
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-- deadended counter for A input filter --
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if (quadbdel = '1') and (quadbcnt < flimit ) then
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quadbcnt <= quadbcnt + 1;
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end if;
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if (quadbdel = '0') and (quadbcnt /= 0) then
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quadbcnt <= quadbcnt -1;
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end if;
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if quadbcnt >= flimit then
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quadbfilt<= '1';
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end if;
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if quadbcnt = 0 then
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quadbfilt <= '0';
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end if;
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-- deadended counter for index input filter --
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if (indexsrc = '1') and (indexcnt < flimit ) then
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indexcnt <= indexcnt + 1;
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end if;
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if (indexsrc = '0') and (indexcnt /= 0) then
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indexcnt <= indexcnt -1;
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end if;
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if indexcnt >= flimit then
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indexfilt<= '1';
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end if;
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if indexcnt = 0 then
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indexfilt<= '0';
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end if;
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end if;
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if (countclear = '1') or
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((clearonindex = '1') and (indexdet = '1')) then -- rising edge of conditioned index
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doclear <= '1';
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if justonce = '1' then
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clearonindex <= '0';
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end if;
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else
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doclear <= '0';
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end if;
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if ((latchonindex = '1') and (indexdet = '1') ) then -- rising edge of conditioned index
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countlatch <= count;
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if justonce = '1' then
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latchonindex <= '0';
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end if;
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end if;
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if countermode = '0' and (
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(quada2 = '0' and quada1 = '1' and quadb2 = '0' and quadb1 = '1') or -- any time both a,b change at same time
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(quada2 = '1' and quada1 = '0' and quadb2 = '1' and quadb1 = '0') or -- indicates a quadrature count error
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(quada2 = '0' and quada1 = '1' and quadb2 = '1' and quadb1 = '0') or
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(quada2 = '1' and quada1 = '0' and quadb2 = '0' and quadb1 = '1')) then
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quaderror <= '1';
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end if;
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if up /= down then
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timestamplatch <= timestamp; -- time stamp whenever we count
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if up = '1' then
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count <= count + 1;
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else
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count <= count - 1;
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end if;
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end if;
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if doclear = '1' then
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count <= x"0000";
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end if;
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if loadccr = '1' then
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if ibus(15) = '1' then
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quaderror <= '0';
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end if;
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abmaskpol <= ibus(14);
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-- latchonprobe (bit 13);
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-- probepol (bit 12);
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quadfilter <= ibus(11);
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countermode <= ibus(10);
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useindexmask <= ibus(9);
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indexmaskpol <= ibus(8);
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abgateindex <= ibus(7);
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justonce <= ibus(6);
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clearonindex <= ibus(5);
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latchonindex <= ibus(4);
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indexpol <= ibus(3);
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end if;
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if (sample = '1') then
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sampleddata(31 downto 16) <= timestamplatch;
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sampleddata(15 downto 0) <= count;
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sampledcont(31 downto 16) <= countlatch;
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sampledcont(15) <= quaderror;
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sampledcont(14) <= abmaskpol;
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sampledcont(11) <= quadfilter;
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sampledcont(10) <= countermode;
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sampledcont(9) <= useindexmask;
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sampledcont(8) <= indexmaskpol;
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sampledcont(7) <= abgateindex;
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sampledcont(6) <= justonce;
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sampledcont(5) <= clearonindex;
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sampledcont(4) <= latchonindex;
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sampledcont(3) <= indexpol;
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sampledcont(2) <= index1;
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sampledcont(1) <= quadb1;
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sampledcont(0) <= quada1;
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end if;
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dtimer <= timer;
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end if; --(clock edge)
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if (timer = '1' and dtimer = '0') or (timerenable = '0') then -- rising edge of selected timer
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sample <= '1';
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else
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sample <= '0';
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end if;
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if (index1 = '1') and (index2 = '0') and ((fixedindexmask = '1') or (useindexmask = '0')) then
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indexdet <= '1';
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else
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indexdet <= '0';
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end if;
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if (qcountup = '1' or udcountup = '1' ) and doclear = '0' then
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up <= '1';
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else
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up <= '0';
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end if;
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if (qcountdown = '1' or udcountdown = '1' ) and doclear = '0' then
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down <= '1';
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else
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down <= '0';
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end if;
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obus <= (others => 'Z');
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if (readcount = '1') then
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obus <= sampleddata;
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end if;
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if (readccr = '1') then
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obus <= sampledcont;
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end if;
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end process;
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end behavioral;
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