368 lines
12 KiB
VHDL
Executable File
368 lines
12 KiB
VHDL
Executable File
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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entity stepgen is
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generic (
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buswidth : integer;
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timersize : integer;
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tablewidth : integer;
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asize : integer;
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rsize : integer
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);
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Port ( clk : in std_logic;
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ibus : in std_logic_vector(buswidth-1 downto 0);
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obus : out std_logic_vector(buswidth-1 downto 0);
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loadsteprate : in std_logic;
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loadaccum : in std_logic;
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loadstepmode : in std_logic;
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loaddirsetuptime : in std_logic;
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loaddirholdtime : in std_logic;
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loadpulseactivetime : in std_logic;
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loadpulseidletime : in std_logic;
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loadtable : in std_logic;
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loadtablemax : in std_logic;
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readsteprate : in std_logic;
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readaccum : in std_logic;
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readstepmode : in std_logic;
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readdirsetuptime : in std_logic;
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readdirholdtime : in std_logic;
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readpulseactivetime : in std_logic;
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readpulseidletime : in std_logic;
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readtable : in std_logic;
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readtablemax : in std_logic;
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basicrate : in std_logic;
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hold : in std_logic;
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stout : out std_logic_vector(tablewidth-1 downto 0)
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);
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end stepgen;
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architecture Behavioral of stepgen is
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-- Step Generator related signals
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signal stepaccum: std_logic_vector(asize-1 downto 0);
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signal nextaccum: std_logic_vector(asize-1 downto 0);
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alias stepmsbs: std_logic_vector(1 downto 0) is stepaccum(rsize-1 downto rsize -2);
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alias stepmsb: std_logic is stepaccum(rsize -1);
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alias nextmsb: std_logic is nextaccum(rsize -1);
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signal dstepmsb : std_logic;
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signal ddshold : std_logic;
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signal steprate: std_logic_vector(rsize -1 downto 0);
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alias stepdir: std_logic is steprate(rsize -1);
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signal dstepdir : std_logic;
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signal stepdirout : std_logic;
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signal pulsewait : std_logic;
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signal steppulse : std_logic := '0';
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signal dpulsewait : std_logic := '0';
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signal dirsetupwait : std_logic;
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signal dirholdwait : std_logic;
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signal dirshwait : std_logic;
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signal dirhold : std_logic;
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signal dirshcount: std_logic_vector(timersize-1 downto 0);
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signal pulsewidthcount: std_logic_vector(timersize-1 downto 0);
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signal dirsetuptime: std_logic_vector(timersize -1 downto 0);
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signal dirholdtime: std_logic_vector(timersize -1 downto 0);
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signal pulseactivetime: std_logic_vector(timersize -1 downto 0);
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signal pulseidletime: std_logic_vector(timersize -1 downto 0);
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signal stepmode: std_logic_vector(2 downto 0);
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alias swapoutputs : std_logic is stepmode(2);
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signal localout: std_logic_vector(tablewidth-1 downto 0);
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signal wewouldcount : std_logic;
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signal dirchange : std_logic;
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signal waitforhold : std_logic;
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signal waitforpulse : std_logic;
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signal tableptr: std_logic_vector(3 downto 0);
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signal tablemax: std_logic_vector(3 downto 0);
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signal tabledata: std_logic_vector(tablewidth-1 downto 0);
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component SRL16E
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--
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generic (INIT : bit_vector);
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--
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port (D : in std_logic;
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CE : in std_logic;
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CLK : in std_logic;
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A0 : in std_logic;
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A1 : in std_logic;
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A2 : in std_logic;
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A3 : in std_logic;
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Q : out std_logic);
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end component;
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begin
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steptable: for i in 0 to tablewidth -1 generate
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asr16e: SRL16E generic map (x"0000") port map(
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D => ibus(i),
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CE => loadtable,
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CLK => clk,
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A0 => tableptr(0),
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A1 => tableptr(1),
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A2 => tableptr(2),
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A3 => tableptr(3),
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Q => tabledata(i)
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);
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end generate;
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astepgen: process (clk,stepdirout, steprate, nextaccum, stepaccum,dirshwait,
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dirholdwait, pulsewait, dpulsewait,dirchange,wewouldcount,waitforpulse,
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dirsetupwait, pulsewidthcount, dirshcount, dirhold, waitforhold,
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readaccum, tabledata, stepmode, steppulse, stepmsbs,localout)
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begin
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if rising_edge(clk) then
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if basicrate = '1' and hold = '0' and ddshold = '0' then -- our basic step rate DDS
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stepaccum <= nextaccum;
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dstepdir <= stepdir; -- only updated when we add
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end if;
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if pulsewait = '1' then -- our two timers
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pulsewidthcount <= pulsewidthcount -1; -- we share dirshcount between setup and hold functions
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end if;
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if (pulsewait = '0') and (dpulsewait = '1') and (steppulse = '1') then
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pulsewidthcount <= pulseidletime; -- output pulse idle time
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steppulse <= '0'; -- clear our output pulse
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end if;
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if dirshwait = '1' then
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dirshcount <= dirshcount -1;
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end if;
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if (stepmsb = '0' and dstepmsb = '1' and dstepdir = '0') -- overflow = we counted up
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or (stepmsb = '1' and dstepmsb = '0' and dstepdir = '1') then -- underflow = we counted down -- the output of the DDS
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pulsewidthcount <= pulseactivetime; -- output pulse active time
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steppulse <= '1';
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dirshcount <= dirholdtime; -- set pulse to dir change hold timer
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dirhold <= '1'; -- set our flag to indicate
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else
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if dirholdwait = '0' then -- no change during hold time
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if dirchange = '1' then -- we need to change the external direction signal
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dirshcount <= dirsetuptime; -- set dir change to next pulse setup time
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dirhold <= '0'; -- set our flag to indicate
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stepdirout <= stepdir; -- update the output direction
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end if; -- our timer is for setup time
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end if;
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end if; -- our timer is for hold time
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if (stepmsb = '0' and dstepmsb = '1' and dstepdir = '0') then -- we counted up
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if (tableptr = tablemax) then
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tableptr <= x"0";
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else
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tableptr <= tableptr +1;
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end if;
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end if;
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if (stepmsb = '1' and dstepmsb = '0' and dstepdir = '1') then -- we counted down
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if (tableptr = x"0") then
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tableptr <= tablemax;
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else
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tableptr <= tableptr -1;
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end if;
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end if;
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if loadstepmode = '1' then -- our register writes
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stepmode <= ibus(2 downto 0);
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end if;
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if loadsteprate = '1' then
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steprate <= ibus(rsize -1 downto 0);
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end if;
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if loadaccum = '1' then
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stepaccum(asize -1 downto asize-buswidth) <= ibus;
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dstepmsb <= ibus(buswidth-1); -- avoid generating a step when loading accumulator
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end if;
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if loaddirsetuptime = '1' then
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dirsetuptime <= ibus(timersize -1 downto 0);
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end if;
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if loaddirholdtime = '1' then
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dirholdtime <= ibus(timersize -1 downto 0);
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end if;
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if loadpulseactivetime = '1' then
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pulseactivetime <= ibus(timersize -1 downto 0);
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end if;
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if loadpulseidletime = '1' then
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pulseidletime <= ibus(timersize -1 downto 0);
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end if;
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if loadtablemax = '1' then
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tablemax <= ibus(3 downto 0);
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tableptr <= x"0";
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end if;
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dpulsewait <= pulsewait;
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dstepmsb <= stepmsb;
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end if; -- clk
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dirchange <= stepdirout xor stepdir;
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if (stepmsb = '1' and nextmsb = '0' and stepdir = '0') -- overflow = we would count up
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or (stepmsb = '0' and nextmsb = '1' and stepdir = '1') then -- underflow = we would count down
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wewouldcount <= '1';
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else
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wewouldcount <= '0';
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end if;
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waitforhold <= dirholdwait and dirchange;
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waitforpulse <= pulsewait or dpulsewait;
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nextaccum <= signed(stepaccum)+ signed(steprate); -- to lookahead
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if (wewouldcount = '1') and
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-- (((waitforhold = '1') or (dirsetupwait = '1') or (waitforpulse = '1'))) -- misses the case where Dirhold has timed out!
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(((waitforhold = '1') or (dirsetupwait = '1') or (waitforpulse = '1') or (dirchange = '1')))
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then -- need to pause
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ddshold <= '1';
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else
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ddshold <= '0';
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end if;
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if pulsewidthcount = 0 then
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pulsewait <= '0';
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else
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pulsewait <= '1';
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end if;
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if dirshcount = 0 then
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dirshwait <= '0';
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else
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dirshwait <= '1';
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end if;
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dirholdwait <= (dirhold and dirshwait);
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dirsetupwait <= (not dirhold) and dirshwait;
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obus <= (others => 'Z');
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-- if readsteprate = '1' then
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-- obus(rsize -1 downto 0) <= steprate;
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-- end if;
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if readaccum = '1' then
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obus <= stepaccum(asize -1 downto asize-buswidth);
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end if;
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-- if readstepmode = '1' then -- register readbacks commented out for size
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-- obus(3 downto 0) <= stepmode;
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-- obus(31 downto 4) <= (others => '0');
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-- end if;
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-- if readdirsetuptime = '1' then
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-- obus(timersize -1 downto 0) <= dirsetuptime;
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-- obus(31 downto timersize) <= (others => '0');
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-- end if;
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-- if readdirholdtime = '1' then
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-- obus(timersize -1 downto 0) <= dirholdtime;
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-- obus(31 downto timersize) <= (others => '0');
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-- end if;
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-- if readpulseactivetime = '1' then
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-- obus(timersize -1 downto 0) <= pulsewidth;
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-- obus(31 downto timersize) <= (others => '0');
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-- end if;
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-- if readpulseidletime = '1' then
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-- obus(timersize -1 downto 0) <= pulseidle;
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-- obus(31 downto timersize) <= (others => '0');
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-- end if;
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localout <= tabledata; -- this is the default unless:
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case stepmode(1 downto 0) is
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when "00" =>
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localout(0) <= steppulse; -- step
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localOut(1) <= stepdirout; -- dir
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when "01" =>
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localout(0) <= steppulse and (not stepdirout); -- count up
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localOut(1) <= steppulse and stepdirout; -- count down
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when "10" =>
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case stepmsbs is
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when "00" => localout(1 downto 0) <= "00"; -- quadrature
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when "01" => localout(1 downto 0) <= "01";
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when "10" => localout (1 downto 0)<= "11";
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when "11" => localout(1 downto 0) <= "10";
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when others => null;
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end case;
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when others => null;
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end case;
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if swapoutputs = '0' then
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stout <= localout;
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else
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stout(0) <= localout(1);
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stout(1) <= localout(0);
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end if;
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end process astepgen;
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end Behavioral;
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