418 lines
13 KiB
VHDL
Executable File
418 lines
13 KiB
VHDL
Executable File
library IEEE;
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use IEEE.std_logic_1164.all; -- defines std_logic types
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use IEEE.std_logic_ARITH.ALL;
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use IEEE.std_logic_UNSIGNED.ALL;
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Library UNISIM;
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use UNISIM.vcomponents.all;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- dont change these:
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use work.IDROMConst.all;
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-------------------- option selection area ----------------------------
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-------------------- select one card type------------------------------
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--use work.@Card@.all;
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--use work.i20card.all; -- needs 5i20.ucf and SP2 200K 208 pin
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use work.i65card.all; -- needs 4i65.ucf and SP2 200K 208 pin
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-----------------------------------------------------------------------
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-------------------- select (or add) one pinout ---------------------------------
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--use work.@Pin@.all;
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use work.PIN_SVSmithy_72.all;
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--use work.PIN_SVST8_4IM2_72.all;
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--use work.PIN_SVST8_4_72.all;
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--use work.PIN_SVST6_6_7I48_72.all;
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--use work.PIN_SVST2_4_7I47_72.all;
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--use work.PIN_SSSVST2_2_4_7I47_72.all; -- mshaver
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--use work.PIN_SVST2_8_72.all;
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--use work.PIN_SV12_72.all;
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--use work.PIN_2X7I65_72.all;
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--use work.PIN_SV12IM_2X7I48_72.all;
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--use work.PIN_TPEN6_6_72.all;
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--use work.PIN_SVST1_4_7I47S_72.all;
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--use work.PIN_SVSS4_4_72.all;
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--use work.PIN_SVSS6_6_72.all;
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--use work.PIN_SVST6_6_7I52S_72.all;
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--use work.PIN_SVSS8_8_72.all;
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--use work.PIN_SVSS4_8_72.all;
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--use work.PIN_SVSS6_8_72.all;
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--use work.PIN_SVTP6_7I39_72.all;
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--use work.PIN_SVST6_1_72.all;
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--use work.PIN_SV6_7I52S_72.all;
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--use work.PIN_SVST1_4_7I47DA_72.all;
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--use work.PIN_SVST12_12_7I52S_72.all;
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--use work.PIN_7I77_72.all; -- 7i77 with adapter
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-- custom and specials
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--use work.PIN_SS8_72.all;
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--use work.PIN_SV12_3X7I47_72.all;
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--use work.PIN_SVSP8_6_7I46_72.all;
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--use work.PIN_SVST8_4P_72.all;
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--use work.PIN_SVST8_3P_72.all;
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--use work.PIN_SVST4_4IM2SI_72.all;
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--use work.PIN_SVTW4_1_10_72.all;
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--use work.PIN_SVUA8_4_72.all;
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--use work.PIN_UASVST2_2_4_7I47_72.all;
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--use work.PIN_24XQCTRONLY_72.all;
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--use work.PIN_SVTW8_24_24_72.all;
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--use work.PIN_SVWG8_2IM2_72.all;
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--use work.PIN_PW64_72.all;
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--use work.PIN_MG_72.all;
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--use work.PIN_SV6_7I49_72.all; -- no fit without high magic
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--use work.PIN_SVST2_8_GREG_72.all;
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--use work.PIN_SVST6_6_RUDY_72.all;
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--use work.PIN_SV_4LA_7I47S_72.all;
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--use work.PIN_SVST6_4_7I52S_72.all;
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--use work.PIN_SSSV2_12_7i53_72.all;
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------------------------------------------------------------------------
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-- dont change anything below unless you know what you are doing -------
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entity Top9030HostMot2 is -- for 5I20 and 4I65 PCI 9030 based cards
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generic
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(
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ThePinDesc: PinDescType := PinDesc;
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TheModuleID: ModuleIDType := ModuleID;
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PWMRefWidth: integer := 13; -- PWM resolution is PWMRefWidth-1 bits
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IDROMType: integer := 3;
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UseIRQLogic: boolean := true;
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UseWatchDog: boolean := true;
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OffsetToModules: integer := 64;
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OffsetToPinDesc: integer := 448;
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BusWidth: integer := 32;
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AddrWidth: integer := 16;
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InstStride0: integer := 4; -- instance stride 0 = 4 bytes = 1 x 32 bit
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InstStride1: integer := 64; -- instance stride 1 = 64 bytes = 16 x 32 bit registers (UART needs 16)
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RegStride0: integer := 256; -- register stride 0 = 256 bytes = 64 x 32 bit registers
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RegStride1: integer := 256 -- register stride 1 = 256 bytes - 64 x 32 bit
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);
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port
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(
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-- bus interface signals --
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-- LRD: in std_logic;
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-- LWR: in std_logic;
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LW_R: in std_logic;
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-- ALE: in std_logic;
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ADS: in std_logic;
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BLAST: in std_logic;
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-- WAITOUT: in std_logic;
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-- LOCKO: in std_logic;
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-- CS0: in std_logic;
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-- CS1: in std_logic;
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READY: out std_logic;
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INT: out std_logic;
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-- HOLD: in std_logic;
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-- HOLDA: inout std_logic;
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-- CCS: out std_logic;
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RESET: in std_logic;
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-- DISABLECONF: out std_logic;
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LAD: inout std_logic_vector (31 downto 0); -- data/address bus
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-- LA: in std_logic_vector (8 downto 2); -- non-muxed address bus
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LBE: in std_logic_vector (3 downto 0); -- byte enables
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IOBITS: inout std_logic_vector (IOWidth -1 downto 0);
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LCLK: in std_logic;
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SYNCLK: in std_logic;
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-- led bits
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LEDS: out std_logic_vector(LEDCount -1 downto 0)
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);
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end Top9030HostMot2;
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architecture dataflow of Top9030HostMot2 is
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-- alias SYNCLK: std_logic is LCLK;
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-- misc global signals --
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signal D: std_logic_vector (BusWidth-1 downto 0); -- internal data bus
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signal DPipe: std_logic_vector (BusWidth-1 downto 0); -- read pipeline reg
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signal LADPipe: std_logic_vector (BusWidth-1 downto 0); -- write pipeline reg
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signal LW_RPipe: std_logic;
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signal A: std_logic_vector (15 downto 2);
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signal ReadStb: std_logic;
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signal ReadTSEn: std_logic;
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signal WriteStb: std_logic;
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signal Burst: std_logic;
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signal BurstCount: std_logic_vector (7 downto 0);
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signal NextA: std_logic_vector (15 downto 2);
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signal ReadyFF: std_logic;
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signal EnableHS: std_logic;
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-- CLK multiplier DLL signals
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signal FClk: std_logic; -- high speed clock = 100 MHz
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signal Clk0: std_logic;
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signal CLK2X: std_logic;
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signal clkmed: std_logic;
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begin
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CombinedClock: if (not Sepclocks) generate
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CLKDLL_inst3 : CLKDLL
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generic map (
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CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,4.0,5.0,8.0 or 16.0
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DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
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FACTORY_JF => X"C080", -- FACTORY JF Values
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STARTUP_WAIT => FALSE) -- Delay config DONE until DLL LOCK, TRUE/FALSE
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port map (
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CLK0 => CLK0, -- 0 degree DLL CLK output
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CLKFB =>FClk, -- DLL feedback
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CLK2X => CLK2X, -- 2X DLL CLK output
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CLKIN => LCLK, -- Clock input (from IBUFG, BUFG or DLL)
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RST => '0' -- DLL asynchronous reset input
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);
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BUFG_inst3 : BUFG
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port map (
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O => FClk, -- HS Clock buffer output
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I => CLK2X -- Clock buffer input
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);
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BUFG_inst1 : BUFG
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port map (
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O => clkmed, -- Processor Clock buffer output
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I => CLK0 -- Clock buffer input
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);
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end generate;
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SeparateClock: if Sepclocks generate
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CLKDLL_inst3 : CLKDLL
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generic map (
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CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,4.0,5.0,8.0 or 16.0
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DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
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FACTORY_JF => X"C080", -- FACTORY JF Values
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STARTUP_WAIT => FALSE) -- Delay config DONE until DLL LOCK, TRUE/FALSE
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port map (
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CLK0 => CLK0, -- 0 degree DLL CLK output
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CLKFB =>clkmed, -- DLL feedback
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CLK2X => CLK2X, -- 2X DLL CLK output
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CLKIN => SYNCLK, -- Clock input (from IBUFG, BUFG or DLL)
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RST => '0' -- DLL asynchronous reset input
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);
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BUFG_inst3 : BUFG
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port map (
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O => FClk, -- HS Clock buffer output
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I => CLK2X -- Clock buffer input
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);
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BUFG_inst1 : BUFG
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port map (
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O => clkmed, -- Processor Clock buffer output
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I => CLK0 -- Clock buffer input
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);
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end generate;
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ahostmot2: entity HostMot2
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generic map (
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thepindesc => ThePinDesc,
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themoduleid => TheModuleID,
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idromtype => IDROMType,
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sepclocks => SepClocks,
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onews => OneWS,
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useirqlogic => UseIRQLogic,
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pwmrefwidth => PWMRefWidth,
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usewatchdog => UseWatchDog,
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offsettomodules => OffsetToModules,
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offsettopindesc => OffsetToPinDesc,
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clockhigh => ClockHigh,
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clockmed => ClockMed,
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clocklow => ClockLow,
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boardnamelow => BoardNameLow,
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boardnamehigh => BoardNameHigh,
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fpgasize => FPGASize,
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fpgapins => FPGAPins,
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ioports => IOPorts,
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iowidth => IOWidth,
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liowidth => LIOWidth,
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portwidth => PortWidth,
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buswidth => BusWidth,
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addrwidth => AddrWidth,
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inststride0 => InstStride0,
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inststride1 => InstStride1,
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regstride0 => RegStride0,
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regstride1 => RegStride1,
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ledcount => LEDCount
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)
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port map (
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ibus => LADPipe,
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obus => D,
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addr => NextA,
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readstb => ReadStb,
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writeStb => WriteStb,
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clklow => LCLK, -- local bus clock 33.3 MHz
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clkmed => clkmed, -- processor clock 50 MHz
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clkhigh => FClk, -- high speed clock 100 MHz
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int => INT,
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iobits => IOBITS,
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leds => LEDS
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);
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OneWaitStateDPath: if OneWS generate
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WSLADDrivers: process (DPipe,ReadTSEn,LCLK)
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begin
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if rising_edge(LCLK) then
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DPipe <= D;
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LADPipe <= LAD;
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end if;
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if ReadTSEn ='1' then
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LAD <= DPipe;
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else
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LAD <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
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end if;
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end process WSLADDrivers;
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end generate;
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NoWaitStateDPath: if not OneWS generate
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NoWSLADDrivers: process (D)
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begin
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LADPipe <= LAD;
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if ReadTSEn ='1' then
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LAD <= D;
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else
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LAD <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
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end if;
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end process NoWSLADDrivers;
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end generate;
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BusCycleGen: process (LCLK,ADS, LAD, ReadyFF, A, Burst, LW_RPipe) -- added 1 wait state (read/write)
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begin
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if rising_edge(LCLK) then
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A <= NextA; -- always update our latched address
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if ADS = '0' then -- if *ADS then latch address & indicate start of burst
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Burst <= '1';
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ReadyFF <= '0'; -- always start off not ready
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end if;
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if BLAST = '0' and ReadyFF= '1' then -- end of burst
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Burst <= '0';
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end if;
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if OneWS then
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if Burst = '1' then
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ReadyFF <= not ReadyFF; -- just one wait state so toggle ReadyFF
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end if;
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else
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ReadyFF <= '1'; -- always ready if OneWS not used (not complete)
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end if;
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LW_RPipe <= LW_R;
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end if; -- lclk
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if ADS = '0' then -- NextA is combinatorial next address
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NextA <= LAD(15 downto 2); -- we need this for address lookahead for block RAM
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else
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if ReadyFF = '1' then
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NextA <= A+1;
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else
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NextA <= A;
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end if;
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end if;
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WriteStb <= Burst and LW_RPipe and ReadyFF; -- A write is any time during burst when LW_R is high and ReadyFF is high
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-- Note that write writes the data from the LADPipe register to the destination
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ReadTSEn <= Burst and not LW_RPipe; -- ReadTSEn is any time during burst when LW_R is low = tri state enable on DPipe output
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if OneWS then
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ReadStb <= Burst and not LW_RPipe and not ReadyFF; -- A read is any time during burst when LW_R is low and ReadyFF is low = internal read data enable to DPipe input
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else
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ReadStb <= ReadTSEn;
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end if;
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READY <= not ReadyFF; -- note: target only!
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end process BusCycleGen;
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-- DoHandshake: process (HOLD,EnableHS)
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-- begin
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-- if EnableHS = '1' then
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-- HOLDAHOLD;
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-- else
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-- HOLDA'Z';
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-- end if;
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-- end process DoHandShake;
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end dataflow;
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