210 lines
6.6 KiB
VHDL
Executable File
210 lines
6.6 KiB
VHDL
Executable File
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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use work.log2.all;
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entity OutputInteg is -- 8 channel integrator/accumulator with accumlators readable by host
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port ( dspdin : in std_logic_vector (31 downto 0);
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dspdout : out std_logic_vector (31 downto 0);
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hostdout : out std_logic_vector (31 downto 0);
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dspraddr : in std_logic_vector (2 downto 0);
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dspwaddr : in std_logic_vector (2 downto 0);
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hostaddr : in std_logic_vector (2 downto 0);
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loadvel : in std_logic;
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loadrate : in std_logic;
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dspread : in std_logic;
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hostread : in std_logic;
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testout : out std_logic;
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clk : in std_logic);
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end OutputInteg;
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architecture Behavioral of OutputInteg is
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constant divwidth :integer := 16;
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constant channels : integer := 8;
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constant offset : integer := 8; -- accumulator runs 256 times faster than host sample rate so sr by 8
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constant csize : integer := log2(channels);
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constant width : integer := 32;
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signal acca: std_logic_vector(width-1 downto 0);
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signal accb: std_logic_vector(width-1 downto 0);
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signal accsum: std_logic_vector(width-1 downto 0);
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signal rawhostdout: std_logic_vector(width-1 downto 0);
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signal rawdspdout: std_logic_vector(width-1 downto 0);
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signal offsetdin: std_logic_vector(width-1 downto 0);
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signal smaddr: std_logic_vector(log2(channels)-1 downto 0);
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signal smwrite: std_logic;
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signal run: std_logic;
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signal ratereg: std_logic_vector(divwidth-1 downto 0);
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signal ratediv: std_logic_vector(divwidth-1 downto 0);
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alias ratedivmsb: std_logic is ratediv(divwidth-1);
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signal oldratedivmsb: std_logic;
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begin
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inputdpram: entity work.dpram
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generic map (
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width => width,
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depth => channels
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)
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port map(
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addra => dspwaddr,
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addrb => smaddr,
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clk => clk,
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dina => offsetdin,
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-- douta =>
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doutb => acca,
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wea => loadvel
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);
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feedbackdpram: entity work.dpram
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generic map (
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width => width,
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depth => channels
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)
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port map(
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addra => smaddr,
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addrb => dspraddr,
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clk => clk,
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dina => accsum,
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douta => accb,
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doutb => rawdspdout,
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wea => smwrite
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);
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outputdpram: entity work.dpram
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generic map (
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width => width,
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depth => channels
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)
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port map(
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addra => smaddr,
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addrb => hostaddr,
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clk => clk,
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dina => accsum,
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-- douta => snugglebunnies,
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doutb => rawhostdout,
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wea => smwrite
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);
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accumulator: process(clk,acca,accb, dspdin, hostread,
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rawhostdout, dspread, rawdspdout, smwrite) -- multi channel accumulator
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begin
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if rising_edge(clk) then
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ratediv <= ratediv + ratereg;
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if ratedivmsb /= oldratedivmsb then
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smaddr <= conv_std_logic_vector(0,csize);
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smwrite <= '0'; -- start channel processing at channel 0 read
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run <= '1';
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end if;
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if run = '1' then
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if smwrite = '1' then -- if write asserted, increment channel
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if smaddr = conv_std_logic_vector(channels -1,csize) then
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run <= '0'; -- if last channel stop till next rate req
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else
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smaddr <= smaddr +1;
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end if;
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end if;
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smwrite <= not smwrite; -- alternate read/write per channel
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end if;
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oldratedivmsb <= ratedivmsb;
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if loadrate = '1' then
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ratereg <= dspdin(divwidth-1 downto 0);
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end if;
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end if; -- clk
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accsum <= acca + accb;
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offsetdin(width-offset-1 downto 0) <= dspdin(width-1 downto offset);
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if dspdin(width -1) = '1' then -- sign extend
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offsetdin(width-1 downto width-offset) <= (others => '1');
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else
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offsetdin(width-1 downto width-offset) <= (others => '0');
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end if;
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hostdout <= (others => 'Z');
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if hostread = '1' then
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hostdout <= rawhostdout;
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end if;
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dspdout <= (others => 'Z');
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if dspread = '1' then
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dspdout <= rawdspdout;
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end if;
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testout <= smwrite;
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end process;
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end Behavioral;
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