195 lines
6.4 KiB
VHDL
Executable File
195 lines
6.4 KiB
VHDL
Executable File
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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entity simplespi is
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generic (
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buswidth : integer
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);
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port (
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clk : in std_logic;
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ibus : in std_logic_vector(buswidth-1 downto 0);
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obus : out std_logic_vector(buswidth-1 downto 0);
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loadbitcount : in std_logic;
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loadbitrate : in std_logic;
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loaddata : in std_logic;
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readdata : in std_logic;
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readbitcount : in std_logic;
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readbitrate : in std_logic;
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spiclk : out std_logic;
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spiin : in std_logic;
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spiout: out std_logic;
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spiframe: out std_logic;
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davout: out std_logic
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);
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end simplespi;
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architecture behavioral of simplespi is
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constant DivWidth: integer := 8;
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-- ssi interface related signals
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signal RateDivReg : std_logic_vector(DivWidth -1 downto 0);
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signal RateDiv : std_logic_vector(DivWidth -1 downto 0);
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signal ModeReg : std_logic_vector(8 downto 0);
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alias BitcountReg : std_logic_vector(5 downto 0) is ModeReg(5 downto 0);
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alias CPOL : std_logic is ModeReg(6);
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alias CPHA : std_logic is ModeReg(7);
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alias DontClearFrame : std_logic is ModeReg(8);
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signal BitCount : std_logic_vector(5 downto 0);
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signal ClockFF: std_logic;
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signal SPISreg: std_logic_vector(buswidth-1 downto 0);
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signal Frame: std_logic;
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signal EFrame: std_logic;
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signal Dav: std_logic;
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signal SPIInLatch: std_logic;
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signal FirstLeadingEdge: std_logic;
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begin
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aspiinterface: process (clk, readdata, ModeReg, ClockFF, Frame,
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SPISreg, readbitcount, BitcountReg,
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Dav, readbitrate, RateDivReg)
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begin
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if rising_edge(clk) then
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if loaddata = '1' then
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SPISreg <= ibus;
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BitCount <= BitCountReg;
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Frame <= '1';
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EFrame <= '1';
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Dav <= '0';
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ClockFF <= '0';
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FirstLeadingEdge <= '1';
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RateDiv <= RateDivReg;
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end if;
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if Frame = '1' then
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if RateDiv = 0 then
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RateDiv <= RateDivReg;
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SPIInLatch <= spiin; -- sample every edge
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if ClockFF = '0' then
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if BitCount(5) = '1' then
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Frame <= '0'; -- frame cleared 1/2 SPI clock after GO
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if DontClearFrame = '0' then
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EFrame <= '0';
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end if;
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Dav <= '1';
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else
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ClockFF <= '1';
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end if;
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if CPHA = '1' and FirstLeadingEdge = '0' then -- shift out on leading edge for CPHA = 1 case
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SPISreg <= SPISreg(30 downto 0) & (SPIInLatch); -- note shift in data is always one clock edge behind
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end if;
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FirstLeadingEdge <= '0';
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else
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ClockFF <= '0';
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BitCount <= BitCount -1;
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if CPHA = '0' then -- shift out on trailing edge for CPHA = 0 case
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SPISreg <= SPISreg(30 downto 0) & (SPIInLatch); -- note shift in data is always one clock edge behind
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end if;
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end if;
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else
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RateDiv <= RateDiv -1;
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end if;
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end if;
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if loadbitcount = '1' then
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ModeReg <= ibus(8 downto 0);
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end if;
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if loadbitrate = '1' then
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RateDivReg <= ibus(DivWidth -1 downto 0);
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end if;
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end if; -- clk
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obus <= (others => 'Z');
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if readdata = '1' then
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obus <= SPISReg;
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end if;
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if readbitcount = '1' then
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obus(8 downto 0) <= ModeReg;
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obus(buswidth -1) <= Dav;
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end if;
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if readbitrate = '1' then
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obus(DivWidth-1 downto 0) <= RateDivReg;
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end if;
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spiclk <= ClockFF xor CPOL;
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spiframe <= not EFrame;
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davout <= Dav;
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-- for i in 0 to buswidth -1 loop
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-- if i = BitCountReg then
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-- spiout <= SPISReg(i);
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-- end if;
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-- end loop;
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spiout <= SPISReg(conv_integer(BitCountReg(4 downto 0))); -- select the MSB of the current size
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end process aspiinterface;
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end Behavioral;
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