446 lines
13 KiB
VHDL
Executable File
446 lines
13 KiB
VHDL
Executable File
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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entity dpainterd is
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generic (
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buswidth : integer;
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asize : integer;
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rsize : integer;
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usedpll : boolean
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);
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Port ( clk : in std_logic;
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ibus : in std_logic_vector(buswidth-1 downto 0);
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obus : out std_logic_vector(buswidth-1 downto 0);
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loadrate : in std_logic;
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loadaccum : in std_logic;
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loadmode0 : in std_logic;
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loadmode1 : in std_logic;
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loadstartcomp : in std_logic;
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loadstopcomp : in std_logic;
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push : in std_logic;
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readrate : in std_logic;
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readaccum : in std_logic;
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readmode0 : in std_logic;
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readmode1 : in std_logic;
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readstartcomp : in std_logic;
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readstopcomp : in std_logic;
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timers : in std_logic_vector;
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videodataout : out std_logic;
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videoclkout : out std_logic
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);
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end dpainterd;
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architecture Behavioral of dpainterd is
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-- data painter related signals
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signal rateaccum: std_logic_vector(asize-1 downto 0);
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signal ratelatch: std_logic_vector(buswidth-1 downto 0);
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signal countlatch: std_logic_vector(buswidth-1 downto 0);
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signal nextaccum: std_logic_vector(asize-1 downto 0);
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signal startcomp: std_logic_vector(asize-1 downto rsize);
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signal stopcomp: std_logic_vector(asize-1 downto rsize);
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alias ratemsb: std_logic is nextaccum(rsize);
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alias fiftypc: std_logic is rateaccum(rsize-1);
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alias pwmref: std_logic_vector(7 downto 0) is rateaccum(rsize-1 downto rsize-8);
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signal pwmval: std_logic_vector(7 downto 0);
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signal apwmval: std_logic_vector(7 downto 0);
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signal sapwmval: std_logic_vector(16 downto 0);
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signal pwmout: std_logic;
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signal dratemsb: std_logic;
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alias bitcount: std_logic_vector(asize-rsize-1 downto 0) is rateaccum(asize-1 downto rsize);
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signal shiftcount: std_logic_vector(4 downto 0);
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signal datagate: std_logic;
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signal rawdata: std_logic;
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signal videodata: std_logic;
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signal videoclk: std_logic;
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signal underrunerror: std_logic;
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-- mode register bits
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signal modereg0: std_logic_vector(31 downto 0);
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alias programmode: std_logic is modereg0(0);
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alias programgate: std_logic is modereg0(1);
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alias offdata: std_logic is modereg0(2);
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alias hardpwmgate: std_logic is modereg0(3);
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alias enablestart: std_logic is modereg0(4);
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alias enablestop: std_logic is modereg0(5);
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alias clearfifo: std_logic is modereg0(6);
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alias pwmscale: std_logic_vector(8 downto 0) is modereg0(31 downto 23);
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signal modereg1: std_logic_vector(31 downto 0); -- room for expansion
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alias vclkwidth: std_logic_vector(11 downto 0) is modereg1(11 downto 0);
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signal vclktimer: std_logic_vector(11 downto 0);
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alias timerselect: std_logic_vector(3 downto 0) is modereg1(15 downto 12);
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alias pwmmode: std_logic is modereg1(16);
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alias fiftypcclk: std_logic is modereg1(17);
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alias debugloop: std_logic is modereg1(23);
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alias offpwm: std_logic_vector(7 downto 0) is modereg1(31 downto 24);
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-- DPLL related signals
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signal timer : std_logic;
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signal dtimer : std_logic;
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signal sample : std_logic;
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-- FIFO related signals
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signal pushdata: std_logic_vector(31 downto 0);
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signal popadd: std_logic_vector(4 downto 0) := "11111";
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signal popdata: std_logic_vector(31 downto 0);
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signal datacounter: std_logic_vector(5 downto 0);
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-- signal push: std_logic;
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signal pop: std_logic;
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signal fifohasdata: std_logic;
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signal overrunerror: std_logic;
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component SRLC32E
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--
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generic (INIT : bit_vector);
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--
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port (D : in std_logic;
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CE : in std_logic;
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CLK : in std_logic;
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A0 : in std_logic;
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A1 : in std_logic;
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A2 : in std_logic;
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A3 : in std_logic;
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A4 : in std_logic;
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Q : out std_logic;
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Q31 : out std_logic);
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end component;
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begin
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fifosrl: for i in 0 to 31 generate
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asr32e: SRLC32E generic map (x"00000000") port map(
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D => ibus(i),
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CE => push,
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CLK => clk,
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A0 => popadd(0),
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A1 => popadd(1),
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A2 => popadd(2),
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A3 => popadd(3),
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A4 => popadd(4),
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Q => popdata(i)
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);
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end generate;
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afifo: process (clk,popdata,datacounter)
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begin
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if rising_edge(clk) then
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if push = '1' and pop = '0' then
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if datacounter /= 32 then -- a push
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-- always increment the data counter if not full
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datacounter <= datacounter +1;
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popadd <= popadd +1; -- popadd must follow data down shiftreg
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else
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overrunerror <= '1'; -- push when full error
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end if;
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end if;
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if (pop = '1') and (push = '0') and (fifohasdata = '1') then -- a pop
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-- always decrement the data counter if not empty
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datacounter <= datacounter -1;
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popadd <= popadd -1;
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end if;
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-- the other cases = if push=pop we dont change either counter
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if clearfifo = '1' then -- a clear fifo
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popadd <= (others => '1');
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datacounter <= (others => '0');
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overrunerror <= '0';
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end if;
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end if; -- clk rise
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if datacounter = 0 then
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fifohasdata <= '0';
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else
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fifohasdata <= '1';
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end if;
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end process afifo;
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adpainterd: process (clk )
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begin
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if rising_edge(clk) then
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rateaccum <= nextaccum;
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if (ratemsb /= dratemsb) then -- up or down
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if datagate = '1' then
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if shiftcount = 0 then
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if fifohasdata = '1' then
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if debugloop = '0' then --dont pop data if debug mode
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pop <= '1';
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end if;
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else -- data empty
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underrunerror <= '1';
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datagate <= '0';
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programgate <= '0';
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end if;
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if pwmmode = '0' then
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shiftcount <= "11111";
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else
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shiftcount <= "00011";
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end if;
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else
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shiftcount <= shiftcount -1;
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end if; -- shiftcount = 0
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case shiftcount(1 downto 0) is
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when "11" => pwmval <= popdata(31 downto 24);
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when "10" => pwmval <= popdata(23 downto 16);
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when "01" => pwmval <= popdata(15 downto 8);
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when "00" => pwmval <= popdata(7 downto 0);
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when others => pwmval <= (others => '0');
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end case;
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end if; -- datagate = 1
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vclktimer <= vclkwidth;
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end if;
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if datagate = '1' then
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apwmval <= pwmval;
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if pwmmode = '0' then
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rawdata <= popdata(conv_integer(shiftcount));
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else
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rawdata <= pwmout;
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end if;
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else -- gate off
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if pwmmode = '0' then
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rawdata <= offdata; -- replace with off state data
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else -- if gated off in pwm mode chose offpwm
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apwmval <= offpwm;
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if hardpwmgate = '0' then
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rawdata <= pwmout; -- idle pwmdata if not hard gate mode
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else
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rawdata <= offdata; -- otherwise use the single bit idle state
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end if;
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end if;
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end if;
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sapwmval <= (UNSIGNED(apwmval) * UNSIGNED(pwmscale));
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if (UNSIGNED(pwmref) < UNSIGNED(sapwmval(15 downto 8))) then -- do we need to futz with this depending on direction?
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pwmout <= '1';
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else
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pwmout <= '0';
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end if;
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if pop = '1' then -- just one clock
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pop <= '0';
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end if;
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if vclktimer /= 0 then -- setpulse width
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vclktimer <= vclktimer -1;
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videoclk <= '1';
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else
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videoclk <= '0';
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end if;
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if programmode = '1' then
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datagate <= programgate;
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else
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if enablestart = '1' and (bitcount = startcomp) then
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datagate <= '1';
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enablestart <= '0';
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end if;
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if enablestop = '1' and (bitcount = stopcomp) then
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datagate <= '0';
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enablestop <= '0';
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end if;
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end if;
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if sample = '1' then
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countlatch <= rateaccum(asize -1 downto asize-buswidth);
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end if;
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if loadrate = '1' then
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ratelatch <= ibus(rsize -1 downto 0);
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end if;
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if loadaccum = '1' then
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rateaccum(asize -1 downto asize-buswidth) <= ibus;
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dratemsb <= ibus(buswidth-1); -- avoid generating a count when loading accumulator
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end if;
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if loadstartcomp = '1' then
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startcomp <= ibus((asize-rsize)-1 downto 0);
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end if;
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if loadstopcomp = '1' then
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stopcomp <= ibus((asize-rsize)-1 downto 0);
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end if;
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if loadmode0 = '1' then
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modereg0 <= ibus(31 downto 0);
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end if;
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if usedpll then
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if loadmode1 = '1' then
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modereg1 <= ibus(31 downto 0);
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end if;
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else
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if loadmode1 = '1' then
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modereg1(11 downto 0) <= ibus(11 downto 0);
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modereg1(15 downto 12) <= (others => '0');
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modereg1(31 downto 16) <= ibus(31 downto 16);
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end if;
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end if;
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if clearfifo = '1' then
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underrunerror <= '0';
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if pwmmode = '0' then
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shiftcount <= "11111";
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else
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shiftcount <= "00011";
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end if;
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clearfifo <= '0';
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end if;
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dratemsb <= ratemsb;
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dtimer <= timer;
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videodata <= rawdata;
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end if; -- clk
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nextaccum <= signed(rateaccum)+ signed(ratelatch); -- to lookahead
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case timerselect(2 downto 0) is
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when "000" => timer <= timers(0);
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when "001" => timer <= timers(1);
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when "010" => timer <= timers(2);
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when "011" => timer <= timers(3);
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when "100" => timer <= timers(4);
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when others => timer <= timers(0);
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end case;
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if (timer = '1' and dtimer = '0') or (timerselect(3) = '0') then -- rising edge of selected timer
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sample <= '1';
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else
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sample <= '0';
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end if;
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obus <= (others => 'Z');
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if readrate = '1' then
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obus <= ratelatch;
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end if;
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if readaccum = '1' then
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obus <= countlatch;
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end if;
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if readmode0 = '1' then
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obus(6 downto 0) <= modereg0(6 downto 0);
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obus(7) <= datagate;
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obus(13 downto 8) <= datacounter;
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obus(15 downto 14) <= (others => '0');
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obus(20 downto 16) <= shiftcount;
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obus(21) <= underrunerror;
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obus(22) <= overrunerror;
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obus(31 downto 23) <= pwmscale;
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end if;
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if readmode1 = '1' then
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obus <= modereg1;
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end if;
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if readstartcomp = '1' then
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obus(15 downto 0) <= startcomp;
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obus(31 downto 16) <= (others => '0');
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end if;
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if readstopcomp = '1' then
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obus(15 downto 0) <= stopcomp;
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obus(31 downto 16) <= (others => '0');
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end if;
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videodataout <= videodata;
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if fiftypcclk = '0' then
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videoclkout <= videoclk;
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else
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videoclkout <= fiftypc;
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end if;
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end process adpainterd;
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end Behavioral;
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