532 lines
17 KiB
VHDL
Executable File
532 lines
17 KiB
VHDL
Executable File
library IEEE;
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use IEEE.std_logic_1164.all; -- defines std_logic types
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use IEEE.std_logic_ARITH.ALL;
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use IEEE.std_logic_UNSIGNED.ALL;
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Library UNISIM;
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use UNISIM.vcomponents.all;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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use work.IDROMConst.all;
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-------------------- option selection area ----------------------------
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-------------------- select one card type------------------------------
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use work.@Card@.all;
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--use work.i22_1000card.all; -- needs 5i22.ucf and SP3 1000K 320 pin
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--use work.i22_1500card.all; -- needs 5i22.ucf and SP3 1500K 320 pin
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--use work.i68card.all; -- needs 4i68.ucf and SP3 400K 208 pin
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--use work.i23card.all; -- needs 5i23.ucf and SP3 400K 208 pin
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--use work.i21card.all; -- needs 5i21.ucf and SP3 400K 208 pin
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--use work.x20_1000card.all; -- needs 7I68.ucf and SP3 1000K 456 pin
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--use work.x20_1500card.all; -- needs 7I68.ucf and SP3 1500K 456 pin
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--use work.x20_2000card.all; -- needs 7I68.ucf and SP3 2000K 456 pin. Note: ISE only
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--use work.i69_x16card.all; -- needs 4i69.ucf and SP6 x16K 256 pin.
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--use work.i69_x25card.all; -- needs 4i69.ucf and SP6 x25K 256 pin.
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-----------------------------------------------------------------------
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-------------------- select (or add) one pinout ---------------------------------
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use work.@Pin@.all;
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-- 64 I/O pinouts for the 5I21
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-- use work.PIN_STUA8_4_64.all;
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-- use work.PIN_BI8_64.all;
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-- 72 I/O pinouts for 4I68, 4I69, 5I23:
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--use work.PIN_SVST8_4IM2_72.all;
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--use work.PIN_SVST8_4_72.all;
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--use work.PIN_SVST4_8_72.all;
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--use work.PIN_SVST4_8_ADO_72.all;
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--use work.PIN_SVST8_8IM2_72.all;
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--use work.PIN_SVST1_4_7I47S_72.all;
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--use work.PIN_SVST2_4_7I47_72.all;
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--use work.PIN_SVST1_5_7I47_72.all;
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--use work.PIN_2X7I65_72.all;
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--use work.PIN_ST12_72.all;
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--use work.PIN_SV12_72.all;
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--use work.PIN_SVST8_12_2x7I47_72.all;
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--use work.PIN_SVSP8_6_7I46_72.all;
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--use work.PIN_24XQCTRONLY_72.all;
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--use work.PIN_2X7I65_72.all;
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--use work.PIN_SV12IM_2X7I48_72.all;
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--use work.PIN_SVST6_6_7I48_72.all;
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--use work.PIN_SV6_7I49_72.all;
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--use work.PIN_SVUA8_4_72.all;
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--use work.PIN_SVUA8_8_72.all; -- 7I44 pinout UARTS
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--use work.PIN_DA2_72.all;
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--use work.PIN_SVST4_8_ADO_72.all;
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--use work.PIN_SVSS8_8_72.all;
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--use work.PIN_SSSVST8_8_8_72.all;
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--use work.PIN_SVSS6_6_72.all;
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--use work.PIN_SVST6_6_7I52S_72.all;
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--use work.PIN_SVSSST6_6_12_72.all;
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--use work.PIN_SVSS6_8_72.all;
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--use work.PIN_SSSVST8_1_5_7I47_72.all;
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--use work.PIN_SVSS8_44_72.all;
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--use work.PIN_RMSVSS6_8_72.all;
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--use work.PIN_RMSVSS6_12_8_72.all; -- 4i69 5i24 7I80 only
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--use work.PIN_RMSVSS6_10_8_72.all;
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--use work.PIN_ST8_PLASMA_72.all;
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--use work.PIN_SV4_7I47S_72.all;
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--use work.PIN_SVSTUA6_6_6_7I48_72.all;
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--use work.PIN_SVSTTP6_6_7I39_72.all;
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--use work.PIN_ST18_72.all;
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--use work.PIN_PktUARTTest_72.all;
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--use work.PIN_SSSV10_12_72.all;
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--use work.PIN_SVSS12_6_7I48_7I52_72.all;
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--use work.PIN_SVTP6_2_7I52S_72.all;
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-- custom and special
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--use work.PIN_FA1_72.all;
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--use work.PIN_MIKA2_CPR_72.all;
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--use work.PIN_HARRISON_72.all;
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--use work.PIN_MAUROPON.all;
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--use work.PIN_Andy1_72.all;
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--use work.PIN_BASACKWARDS_SVSS6_8_72.all;
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--use work.PIN_SVSTTP6_5_7I39_72.all;
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--use work.PIN_RMSVSS7_7_72.all;
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--use work.PIN_SVFASS6_6_8_72.all;
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--use work.PIN_SVTP2_SI2_72.all;
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-- 96 I/O pinouts for 5I22:
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--use work.PIN_SV16_96.all;
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--use work.PIN_SV12_7I48_7I49_96.all;
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--use work.PIN_SVST8_8_96.all;
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--use work.PIN_SVST8_24_96.all;
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--use work.PIN_ST36_96.all;
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--use work.PIN_ST48_96.all;
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--use work.PIN_SVSTSP8_12_6_96.all;
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--use work.PIN_SV12_2X7I49_96.all;
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--use work.PIN_SV12_7I48_7I49_96.all;
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--use work.PIN_SVSS6_8_96.all;
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--use work.PIN_SVST12_12_2X7I48_96.all;
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--use work.PIN_SV12_2X7I48_96.all;
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--use work.PIN_SSSVST8_1_5_7I47_96.all;
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--use work.PIN_SSSV6_36_96.all;
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--use work.PIN_SSSV8_48_96.all;
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--use work.PIN_SVSS8_16_96.all;
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--use work.PIN_SS32_96.all;
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--use work.PIN_SI36_3X7I47_96.all;
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--use work.PIN_SISS36_8_3X7I47_7I44_96.all;
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--use work.PIN_4x7I65_96.all;
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--use work.PIN_3x7I65_1x7I44_96.all;
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--use work.PIN_SVST10_6_7I49_7I33_7I47_96.all;
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--use work.PIN_SVST2_4_7I47_96.all;
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--custom and special
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--use work.PIN_SVSS8_3_96.all;
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--use work.PIN_MIKA2_CPR_96.all;
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--use work.PIN_SVST10_6_7I49_7I33_7I47_96.all;
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--use work.PIN_SVSTTP6_6_12_96.all;
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--use work.PIN_georgeconf_96.all;
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-- 144 I/O pinouts for 3X20
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--use work.PIN_SVST24_24_7I52S_144.all;
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--use work.PIN_TP48_144.all;
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--use work.PIN_SV24_144.all;
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-- use work.PIN_SVST16_24_144.all;
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-- use work.PIN_SSSVSTRM8_10_144.all;
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------------------------------------------------------------------------
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-- dont change anything below unless you know what you are doing -------
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entity Top9054HostMot2 is -- for 5I21, 5I22, 5I23, 4I68, 4I69 PCI9054 based cards
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generic -- and 3X20 PEX8311 (PCI9056) based cards
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(
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ThePinDesc: PinDescType := PinDesc;
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TheModuleID: ModuleIDType := ModuleID;
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PWMRefWidth: integer := 13; -- PWM resolution is PWMRefWidth-1 bits, MSB is for symmetrical mode
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IDROMType: integer := 3;
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UseIRQLogic: boolean := true;
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UseWatchDog: boolean := true;
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OffsetToModules: integer := 64;
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OffsetToPinDesc: integer := 448;
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BusWidth: integer := 32;
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AddrWidth: integer := 16;
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InstStride0: integer := 4; -- 4..7 -- channel stride
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InstStride1: integer := 64; -- 4..7 64 for sserial Ick double Ick
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-- InstStride1: integer := 16; -- 4..7 16 for BSPI/UART Ick double Ick
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RegStride0: integer := 256; -- 0..3 standard
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RegStride1: integer := 256 -- 0..3 never used
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);
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port
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(
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-- bus interface signals --
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-- LRD: in std_logic;
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-- LWR: in std_logic;
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LW_R: in std_logic;
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-- ALE: in std_logic;
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ADS: in std_logic;
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BLAST: in std_logic;
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-- WAITOUT: in std_logic;
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-- LOCKO: in std_logic;
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-- CS0: in std_logic;
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-- CS1: in std_logic;
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READY: out std_logic;
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BTERM: out std_logic;
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INT: out std_logic;
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DREQ: out std_logic;
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HOLD: in std_logic;
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HOLDA: inout std_logic;
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CCS: out std_logic;
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-- RESET: in std_logic;
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DISABLECONF: out std_logic;
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LAD: inout std_logic_vector (31 downto 0); -- data/address bus
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-- LA: in std_logic_vector (8 downto 2); -- non-muxed address bus
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-- LBE: in std_logic_vector (3 downto 0); -- byte enables
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IOBITS: inout std_logic_vector (IOWidth -1 downto 0); -- external I/O bits
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LIOBITS: inout std_logic_vector (LIOWidth -1 downto 0); -- local I/O bits
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LCLK: in std_logic;
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-- led bits
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LEDS: out std_logic_vector(LEDCount -1 downto 0)
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);
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end Top9054HostMot2;
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architecture dataflow of Top9054HostMot2 is
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-- alias SYNCLK: std_logic is LCLK;
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-- misc global signals --
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signal D: std_logic_vector (BusWidth-1 downto 0); -- internal data bus
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signal DPipe: std_logic_vector (BusWidth-1 downto 0); -- read pipeline reg
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signal LADPipe: std_logic_vector (BusWidth-1 downto 0); -- write pipeline reg
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signal LW_RPipe: std_logic;
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signal A: std_logic_vector (15 downto 2);
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signal Read: std_logic;
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signal ReadTSEn: std_logic;
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signal Write: std_logic;
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signal Burst: std_logic;
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signal NextA: std_logic_vector (15 downto 2);
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signal ReadyFF: std_logic;
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signal LDREQ: std_logic;
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signal DemandMode: std_logic;
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-- CLK multiplier DCM signals
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signal fclk : std_logic;
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signal clkfx0: std_logic;
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signal clk0: std_logic;
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signal clkmed : std_logic;
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signal clkfx1: std_logic;
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signal clk1: std_logic;
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begin
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ClockMult0 : DCM
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generic map (
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CLKDV_DIVIDE => 2.0,
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CLKFX_DIVIDE => 2,
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CLKFX_MULTIPLY => 4, -- 4 FOR 96 MHz/100, 5 for 120/125, 6 for 144/150
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CLKIN_DIVIDE_BY_2 => FALSE,
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CLKIN_PERIOD => 20.0,
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CLKOUT_PHASE_SHIFT => "NONE",
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CLK_FEEDBACK => "1X",
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DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
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DFS_FREQUENCY_MODE => "LOW",
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DLL_FREQUENCY_MODE => "LOW",
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DUTY_CYCLE_CORRECTION => TRUE,
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FACTORY_JF => x"8080",
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PHASE_SHIFT => 0,
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STARTUP_WAIT => FALSE)
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port map (
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CLK0 => clk0, --
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CLKFB => clk0, -- DCM clock feedback
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CLKFX => clkfx0,
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CLKIN => LCLK, -- Clock input (from IBUFG, BUFG or DCM)
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PSCLK => '0', -- Dynamic phase adjust clock input
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PSEN => '0', -- Dynamic phase adjust enable input
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PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
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RST => '0' -- DCM asynchronous reset input
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);
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BUFG_inst : BUFG
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port map (
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O => FClk, -- Clock buffer output
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I => clkfx0 -- Clock buffer input
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);
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-- End of DCM_inst instantiation
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-- CLK multiplier DCM signals
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ClockMult1 : DCM -- This takes LCLK and multiplies it by 3/2 for 72/75 MHz ClockMed
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generic map ( -- but note: async (to bus interface) processor clocks donrt work
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CLKDV_DIVIDE => 2.0, -- in spartan 3 for some reason ( so this is unused for now
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CLKFX_DIVIDE => 2,
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CLKFX_MULTIPLY => 3, -- 3/2 FOR 72/75 MHz
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CLKIN_DIVIDE_BY_2 => FALSE,
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CLKIN_PERIOD => 20.0,
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CLKOUT_PHASE_SHIFT => "NONE",
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CLK_FEEDBACK => "1X",
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DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
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DFS_FREQUENCY_MODE => "LOW",
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DLL_FREQUENCY_MODE => "LOW",
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DUTY_CYCLE_CORRECTION => TRUE,
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FACTORY_JF => x"8080",
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PHASE_SHIFT => 0,
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STARTUP_WAIT => FALSE)
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port map (
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CLK0 => clk1, --
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CLKFB => clk1, -- DCM clock feedback
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CLKFX => clkfx1,
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CLKIN => LCLK, -- Clock input (from IBUFG, BUFG or DCM)
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PSCLK => '0', -- Dynamic phase adjust clock input
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PSEN => '0', -- Dynamic phase adjust enable input
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PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
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RST => '0' -- DCM asynchronous reset input
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);
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BUFG_inst1 : BUFG
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port map (
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O => clkmed, -- Clock buffer output - clock med
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I => clkfx1 -- Clock buffer input
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);
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-- End of DCM_inst instantiation
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ahostmot2: entity work.HostMot2
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generic map (
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thepindesc => ThePinDesc,
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themoduleid => TheModuleID,
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idromtype => IDROMType,
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sepclocks => SepClocks,
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onews => OneWS,
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useirqlogic => UseIRQLogic,
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pwmrefwidth => PWMRefWidth,
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usewatchdog => UseWatchDog,
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offsettomodules => OffsetToModules,
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offsettopindesc => OffsetToPinDesc,
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clockhigh => ClockHigh,
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clockmed => ClockMed,
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clocklow => ClockLow,
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boardnamelow => BoardNameLow,
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boardnamehigh => BoardNameHigh,
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fpgasize => FPGASize,
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fpgapins => FPGAPins,
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ioports => IOPorts,
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iowidth => IOWidth,
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liowidth => LIOWidth,
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portwidth => PortWidth,
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buswidth => BusWidth,
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addrwidth => AddrWidth,
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inststride0 => InstStride0,
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inststride1 => InstStride1,
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regstride0 => RegStride0,
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regstride1 => RegStride1,
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ledcount => LEDCount
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)
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port map (
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ibus => LADPipe,
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obus => D,
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addr => NextA,
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readstb => Read,
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writestb => Write,
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clklow => LCLK,
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clkmed => clkmed,
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clkhigh => FClk,
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int => INT,
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dreq => LDREQ,
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demandmode => DemandMode,
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iobits => IOBITS,
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liobits => LIOBITS,
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leds => LEDS
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);
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LADDrivers: process (DPipe,ReadTSEn,LCLK)
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begin
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if rising_edge(LCLK) then
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DPipe <= D;
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LADPipe <= LAD;
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end if;
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if ReadTSEn ='1' then
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LAD <= DPipe;
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else
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LAD <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
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end if;
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end process LADDrivers;
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BusCycleGen: process (LCLK,ADS, LAD, ReadyFF, A, Burst, LW_RPipe) -- added 1 wait state (read/write)
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begin
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if rising_edge(LCLK) then
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A <= NextA; -- always update our latched address
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if ADS = '0' then -- if *ADS then latch address & indicate start of burst
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Burst <= '1';
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ReadyFF <= '0'; -- always start off not ready
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end if;
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if BLAST = '0' and ReadyFF= '1' then -- end of burst
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Burst <= '0';
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end if;
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if OneWS then
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if Burst = '1' then
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ReadyFF <= not ReadyFF; -- just one wait state so toggle ReadyFF
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end if;
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else
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ReadyFF <= '1'; -- always ready if OneWS not used
|
|
end if;
|
|
LW_RPipe <= LW_R;
|
|
end if; -- lclk
|
|
|
|
if ADS = '0' then -- NextA is combinatorial next address
|
|
NextA <= LAD(15 downto 2); -- we need this for address lookahead for block RAM
|
|
else
|
|
if ReadyFF = '1' then
|
|
NextA <= A+1;
|
|
else
|
|
NextA <= A;
|
|
end if;
|
|
end if;
|
|
|
|
Write <= Burst and LW_RPipe and ReadyFF; -- A write is any time during burst when LW_R is high and ReadyFF is high
|
|
-- Note that write writes the data from the LADPipe register to the destination
|
|
ReadTSEn <= Burst and not LW_RPipe; -- ReadTSEn is any time during burst when LW_R is low = tri state enable on DPipe output
|
|
Read <= Burst and not LW_RPipe and not ReadyFF; -- A read is any time during burst when LW_R is low and ReadyFF is low = internal read data enable to DPipe input
|
|
|
|
READY <= not ReadyFF; -- note: target only!
|
|
|
|
end process BusCycleGen;
|
|
|
|
Is5I2x: if (BoardNameHigh = BoardName5I22) or (BoardNameHigh = BoardName5I23) generate
|
|
DoHandshake: process (HOLD,DemandMode, LDREQ)
|
|
begin
|
|
HOLDA <= HOLD;
|
|
CCS <= '1';
|
|
DISABLECONF <= DemandMode;
|
|
BTERM <= '1';
|
|
DREQ <= not LDREQ;
|
|
end process DoHandShake;
|
|
end generate;
|
|
|
|
Is4I68: if (BoardNameHigh = BoardName4I68) generate -- because the standard 4I68 does not have CCS connected
|
|
DoHandshake: process (HOLD,DemandMode, LDREQ)
|
|
begin
|
|
HOLDA <= HOLD;
|
|
if DemandMode = '1' then
|
|
DISABLECONF <= '1';
|
|
else
|
|
DISABLECONF <= 'Z';
|
|
end if;
|
|
BTERM <= '1';
|
|
DREQ <= not LDREQ;
|
|
end process DoHandShake;
|
|
end generate;
|
|
|
|
Is5I21: if (BoardNameHigh = BoardName5I21) generate -- just like 4I68 but 5I21 has CCS
|
|
DoHandshake: process (HOLD,DemandMode, LDREQ)
|
|
begin
|
|
HOLDA <= HOLD;
|
|
CCS <= '1';
|
|
if DemandMode = '1' then
|
|
DISABLECONF <= '1';
|
|
else
|
|
DISABLECONF <= 'Z';
|
|
end if;
|
|
BTERM <= '1';
|
|
DREQ <= not LDREQ;
|
|
end process DoHandShake;
|
|
end generate;
|
|
|
|
Is4I69: if (BoardNameHigh = BoardName4I69) generate
|
|
DoHandshake: process (HOLD,DemandMode, LDREQ)
|
|
begin
|
|
HOLDA <= HOLD;
|
|
CCS <= '1';
|
|
DISABLECONF <= DemandMode;
|
|
BTERM <= '1';
|
|
DREQ <= not LDREQ;
|
|
end process DoHandShake;
|
|
end generate;
|
|
|
|
Is3X20: if (BoardNameHigh = BoardName3X20) generate -- because 3X20 does not have DISABLECONF connected
|
|
DoHandshake: process (HOLD, LDREQ) -- 3X20 has no DISABLECONF
|
|
begin
|
|
HOLDA <= HOLD;
|
|
CCS <= '1';
|
|
BTERM <= '1';
|
|
DREQ <= not LDREQ;
|
|
end process DoHandShake;
|
|
end generate;
|
|
|
|
end dataflow;
|
|
|
|
|