638 lines
21 KiB
VHDL
Executable File
638 lines
21 KiB
VHDL
Executable File
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.MATH_REAL.ALL;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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Library UNISIM;
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use UNISIM.vcomponents.all;
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-- dont change these:
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use work.IDROMConst.all;
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use work.decodedstrobe.all;
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use work.FixICap.all;
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-------------------- option selection area ----------------------------
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-------------------- select one card type------------------------------
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use work.@Card@.all;
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--use work.i90_x9card.all; -- needs 7i90spi.ucf and SP6 x9 144 pin
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--use work.c80_x9card.all; -- needs 7c80spi.ucf and SP6 x9 144 pin
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--use work.c81_x9card.all; -- needs 7c81spi.ucf and SP6 x9 144 pin
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-----------------------------------------------------------------------
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--use work.@Pin@.all;
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--72 pin pinouts for 7I90
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--use work.PIN_JUSTIO_72.all;
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--use work.PIN_SVST8_4IM2_72.all;
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--use work.PIN_SVST8_4_72.all;
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--use work.PIN_SVST4_8_72.all;
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--use work.PIN_SVST4_8_ADO_72.all;
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--use work.PIN_SVST8_8IM2_72.all;
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--use work.PIN_SVST1_4_7I47S_72.all;
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--use work.PIN_SVST2_4_7I47_72.all;
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--use work.PIN_SVST1_5_7I47_72.all;
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--use work.PIN_2X7I65_72.all;
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--use work.PIN_ST12_72.all;
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--use work.PIN_SV12_72.all;
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--use work.PIN_SVST8_12_2x7I47_72.all;
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--use work.PIN_SVSP8_6_7I46_72.all;
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--use work.PIN_24XQCTRONLY_72.all;
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--use work.PIN_2X7I65_72.all;
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--use work.PIN_SV12IM_2X7I48_72.all;
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--use work.PIN_SV6_7I49_72.all;
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--use work.PIN_SVUA8_4_72.all;
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--use work.PIN_SVUA8_8_72.all; -- 7I44 pinout UARTS
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--use work.PIN_DA2_72.all;
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--use work.PIN_SVST4_8_ADO_72.all;
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--use work.PIN_SVSS8_8_72.all;
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--use work.PIN_SSSVST8_8_8_72.all;
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--use work.PIN_SVSS6_6_72.all;
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--use work.PIN_SVSSST6_6_12_72.all;
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--use work.PIN_SVSS6_8_72.all;
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--use work.PIN_SSSVST8_1_5_7I47_72.all;
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--use work.PIN_SVSS8_44_72.all;
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--use work.PIN_RMSVSS6_8_72.all;
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--use work.PIN_RMSVSS6_12_8_72.all; -- 4i69 5i24 only
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--use work.PIN_ST8_PLASMA_72.all;
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--use work.PIN_SV4_7I47S_72.all;
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--use work.PIN_SVSTUA6_6_6_7I48_72.all;
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--use work.PIN_SVSTTP6_6_7I39_72.all;
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--use work.PIN_ST18_72.all;
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--use work.PIN_SSST8_6_72.all;
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--use work.PIN_STSVSS6_6_4_72.all;
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-- 54 pin pinouts for 7C80
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--use work.PIN_7C80D_54.all;
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-- 57 pin pinouts for 7C81
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--use work.PIN_JUSTIO_57.all;
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--use work.PIN_5ABOBx3D_57.all;
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--use work.PIN_5ABOBx2D_57.all;
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--use work.PIN_MX3660x2D_57.all;
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--use work.PIN_C11Gx2D_57.all;
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--use work.PIN_G540x2D_57.all;
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--use work.PIN_7I76x2D_57.all;
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--use work.PIN_7I76x2_7I89D_57.all;
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--use work.PIN_7I77x2D_57.all;
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--use work.PIN_7I77x1_7I76x1D_57.all;
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----------------------------------------------------------------------
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-- dont change anything below unless you know what you are doing -----
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entity TopGCSPIHostMot2 is -- for 7I90/7C80/7C81 in SPI mode
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generic
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(
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ThePinDesc: PinDescType := PinDesc;
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TheModuleID: ModuleIDType := ModuleID;
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PWMRefWidth: integer := 13; -- PWM resolution is PWMRefWidth-1 bits
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IDROMType: integer := 3;
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UseIRQLogic: boolean := true;
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UseWatchDog: boolean := true;
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OffsetToModules: integer := 64;
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OffsetToPinDesc: integer := 448;
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BusWidth: integer := 32;
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AddrWidth: integer := 16;
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InstStride0: integer := 4; -- instance stride 0 = 4 bytes = 1 x 32 bit
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InstStride1: integer := 64; -- instance stride 1 = 64 bytes = 16 x 32 bit registers
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RegStride0: integer := 256; -- register stride 0 = 256 bytes = 64 x 32 bit registers
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RegStride1: integer := 256; -- register stride 1 = 256 bytes - 64 x 32 bit
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FallBack: boolean := false -- is this a fallback config?
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);
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Port ( CLK : in std_logic;
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LEDS : out std_logic_vector(LEDCount -1 downto 0);
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IOBITS : inout std_logic_vector(IOWidth -1 downto 0);
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COM_SPICLK : in std_logic; -- host interface SPI ( FPGA is slave)
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COM_SPIIN : in std_logic;
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COM_SPIOUT : out std_logic;
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COM_SPICS : in std_logic;
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TEST0 : out std_logic;
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RECONFIG : out std_logic;
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NINIT : out std_logic;
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SPICLK : out std_logic; -- config flash spi interface (FPGA is master)
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SPIIN : in std_logic;
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SPIOUT : out std_logic;
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SPICS : out std_logic
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);
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end TopGCSPIHostMot2;
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architecture Behavioral of TopGCSPIHostMot2 is
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constant SPIRead : std_logic_vector(3 downto 0) := x"A";
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constant SPIWrite : std_logic_vector(3 downto 0) := x"B";
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constant SPITimeoutR : real := round(real(ClockLow)*0.000050); -- 50 usec default SPI timeout
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constant SPITimeout : std_logic_vector(15 downto 0) := std_logic_vector(to_unsigned(integer(SPITimeoutR),16));
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signal obus : std_logic_vector(31 downto 0);
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signal translateaddr : std_logic_vector(AddrWidth-1 downto 0);
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alias translatestrobe : std_logic is translateaddr(AddrWidth-1);
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signal loadtranslateram : std_logic;
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signal readtranslateram : std_logic;
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signal translateramsel : std_logic;
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signal loadspics : std_logic;
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signal readspics : std_logic;
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signal loadspireg : std_logic;
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signal readspireg : std_logic;
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signal Read32 : std_logic;
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signal Write32Pipe : std_logic_vector(3 downto 0);
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alias Write32: std_logic is Write32Pipe(3);
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signal ReconfigSel : std_logic;
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signal fooidata: std_logic_vector(7 downto 0);
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signal ReConfigreg : std_logic := '0';
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signal blinkcount : std_logic_vector(25 downto 0);
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-- SPI interface signals
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signal SPIRegIn : std_logic_vector(31 downto 0);
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signal SPIRegOut : std_logic_vector(31 downto 0);
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signal HM2DataOut : std_logic_vector(31 downto 0);
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signal HM2DataOutL : std_logic_vector(31 downto 0);
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signal HM2DataInL : std_logic_vector(31 downto 0);
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signal AddrPtr : std_logic_vector(15 downto 0);
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signal SyncAddrPtr : std_logic_vector(15 downto 0);
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signal SPIBitCount : std_logic_vector(4 downto 0);
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signal SPIHeader : std_logic;
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signal DCOM_SPICS : std_logic;
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signal SPICommand : std_logic_vector(3 downto 0);
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signal SPIBurstCount : std_logic_vector(6 downto 0);
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signal SPIAutoInc : std_logic;
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signal FrameTimer : std_logic_vector(15 downto 0);
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alias FrameTimerMSB : std_logic is FrameTimer(15);
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signal FrameTimerMSBD : std_logic;
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signal SPIReadRequest : std_logic;
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signal SPIReadRequest1 : std_logic;
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signal SPIReadRequest2 : std_logic;
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signal SPIWriteRequest : std_logic;
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signal SPIWriteRequest1 : std_logic;
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signal SPIWriteRequest2 : std_logic;
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signal SPIHeaderFlag : std_logic;
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signal SPIHeaderFlag1 : std_logic;
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signal SPIHeaderFlag2 : std_logic;
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signal UpdateSPIReg : std_logic;
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signal UpdateSPIRegD : std_logic;
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signal NeedWrite : std_logic;
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-- ICap interface
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signal LoadICap : std_logic;
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signal ReadICapCookie : std_logic;
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signal ICapI : std_logic_vector(15 downto 0);
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signal ICapClock : std_logic;
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signal ICapTimer : std_logic_vector(5 downto 0) := "000000";
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signal fclk : std_logic;
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signal clkfx0: std_logic;
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signal clk0_0: std_logic;
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signal clklow : std_logic;
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signal clkfx1: std_logic;
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signal clk0_1: std_logic;
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begin
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ahostmot2: entity work.HostMot2
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generic map (
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thepindesc => ThePinDesc,
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themoduleid => TheModuleID,
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idromtype => IDROMType,
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sepclocks => SepClocks,
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onews => OneWS,
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useirqlogic => UseIRQLogic,
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pwmrefwidth => PWMRefWidth,
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usewatchdog => UseWatchDog,
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offsettomodules => OffsetToModules,
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offsettopindesc => OffsetToPinDesc,
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clockhigh => ClockHigh,
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clockmed => ClockMed,
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clocklow => ClockLow,
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boardnamelow => BoardNameLow,
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boardnamehigh => BoardNameHigh,
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fpgasize => FPGASize,
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fpgapins => FPGAPins,
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ioports => IOPorts,
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iowidth => IOWidth,
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liowidth => LIOWidth,
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portwidth => PortWidth,
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buswidth => BusWidth,
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addrwidth => AddrWidth,
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inststride0 => InstStride0,
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inststride1 => InstStride1,
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regstride0 => RegStride0,
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regstride1 => RegStride1,
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ledcount => LEDCount )
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port map (
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ibus => HM2DataInL,
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obus => HM2DataOut,
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addr => SyncAddrPtr(AddrWidth-1 downto 2),
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readstb => read32,
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writestb => write32,
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clklow => clklow, -- I/O clock
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clkmed => clklow, -- Processor clock
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clkhigh => fclk, -- PWM clock
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-- int => INT,
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iobits => IOBITS,
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leds => LEDS
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);
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ClockMultH : DCM
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generic map (
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CLKDV_DIVIDE => 2.0,
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CLKFX_DIVIDE => 2,
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CLKFX_MULTIPLY => 8, -- 8 FOR 200 MHz
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CLKIN_DIVIDE_BY_2 => FALSE,
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CLKIN_PERIOD => 20.0,
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CLKOUT_PHASE_SHIFT => "NONE",
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CLK_FEEDBACK => "1X",
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DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
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DFS_FREQUENCY_MODE => "LOW",
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DLL_FREQUENCY_MODE => "LOW",
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DUTY_CYCLE_CORRECTION => TRUE,
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FACTORY_JF => X"C080",
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PHASE_SHIFT => 0,
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STARTUP_WAIT => FALSE)
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port map (
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CLK0 => clk0_0, --
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CLKFB => clk0_0, -- DCM clock feedback
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CLKFX => clkfx0,
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CLKIN => CLK, -- Clock input (from IBUFG, BUFG or DCM)
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PSCLK => '0', -- Dynamic phase adjust clock input
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PSEN => '0', -- Dynamic phase adjust enable input
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PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
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RST => '0' -- DCM asynchronous reset input
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);
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BUFG_inst0 : BUFG
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port map (
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O => fclk, -- Clock buffer output
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I => clkfx0 -- Clock buffer input
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);
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ClockMultM : DCM
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generic map (
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CLKDV_DIVIDE => 2.0,
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CLKFX_DIVIDE => 2,
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CLKFX_MULTIPLY => 4, -- 4 FOR 100 MHz
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CLKIN_DIVIDE_BY_2 => FALSE,
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CLKIN_PERIOD => 20.0,
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CLKOUT_PHASE_SHIFT => "NONE",
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CLK_FEEDBACK => "1X",
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DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
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DFS_FREQUENCY_MODE => "LOW",
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DLL_FREQUENCY_MODE => "LOW",
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DUTY_CYCLE_CORRECTION => TRUE,
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FACTORY_JF => X"C080",
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PHASE_SHIFT => 0,
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STARTUP_WAIT => FALSE)
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port map (
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CLK0 => clk0_1, --
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CLKFB => clk0_1, -- DCM clock feedback
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CLKFX => clkfx1,
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CLKIN => CLK, -- Clock input (from IBUFG, BUFG or DCM)
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PSCLK => '0', -- Dynamic phase adjust clock input
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PSEN => '0', -- Dynamic phase adjust enable input
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PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
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RST => '0' -- DCM asynchronous reset input
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);
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BUFG_inst1 : BUFG
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port map (
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O => clklow, -- Clock buffer output
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I => clkfx1 -- Clock buffer input
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);
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-- End of DCM_inst instantiation
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ICAP_SPARTAN6_inst : ICAP_SPARTAN6
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generic map (
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DEVICE_ID => X"2000093", -- Specifies the pre-programmed Device ID value
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SIM_CFG_FILE_NAME => "NONE" -- Specifies the Raw Bitstream (RBT) file to be parsed by the simulation
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-- model
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)
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port map (
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-- BUSY => BUSY, -- 1-bit output: Busy/Ready output
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-- O => ICapO, -- 16-bit output: Configuration data output bus
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CE => '0', -- 1-bit input: Active-Low ICAP Enable input
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CLK => ICapClock, -- 1-bit input: Clock input
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I => ICapI, -- 16-bit input: Configuration data input bus
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WRITE => '0' -- 1-bit input: Read/Write control input
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);
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gcspi: process(clklow,COM_SPICLK) -- SPI interface with separate GClk SPI clock CPOL 0 CPHA 0
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begin
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if Rising_edge(COM_SPICLK) then -- sample the SPI data in on rising edge
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if UpdateSPIReg = '1' then
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UpdateSPIReg <= '0';
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end if;
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if COM_SPICS= '0' then
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SPIRegIn <= SPIRegIN(30 downto 0) & COM_SPIIn; -- shift left (MSB first)
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SPIBitCount <= SPIBitCount +1;
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if SPIHeader= '1' then
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if SPIBitCount = "01000" then -- clear command etc at 8
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AddrPtr <= x"0000";
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SPICommand <= "0000";
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SPIBurstCount <= "0000000";
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SPIAutoInc <= '0';
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end if;
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if SPIBitCount = "10000" then
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AddrPtr <= SPIRegIn(15 downto 0); -- grab address on the fly at 16
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end if;
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if SPIBitCount = "10100" then
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SPICommand <= SPIRegIn(3 downto 0); -- grab command on the fly at 20
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end if;
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if SPIBitCount = "10101" then
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SPIAutoInc <= SPIRegIn(0); -- grab autoinc on the fly at 21
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SPIHeaderFlag <= '1'; -- signal HM2 clock domain process
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end if;
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if SPIBitCount = "11100" then -- grab burst count at 28
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SPIBurstCount <= SPIRegIn(6 downto 0);
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end if;
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if SPIBitCount = "11111" then
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SPIHeader <= '0';
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end if;
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else -- not header
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if SPIBitCount = "11111" then
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if SPIBurstCount = 1 then
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SPIHeader <= '1';
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else
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SPIBurstCount <= SPIBurstCount -1;
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end if;
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end if;
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end if; --header
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if (SPICommand = SPIRead) and (SPIBitCount = "10110") and (SPIBurstCount /= 1) then -- read request at bit 22
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SPIReadRequest <= '1';
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UpdateSPIReg <= '1';
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end if;
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end if; -- CS = 0
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end if; -- clk rising edge
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if Falling_edge(COM_SPICLK) then -- shift data out on falling edge
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if COM_SPICS = '0' then
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if (SPICommand = SPIWrite) and (SPIBitCount = "10110") and SPIHeader = '0' then -- write request at bit 22
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NeedWrite <= '1';
|
|
end if;
|
|
if NeedWrite = '1' and SPIBitCount = "00000" then
|
|
SPIWriteRequest <= '1';
|
|
HM2DataInL <= SPIRegIn;
|
|
NeedWrite <= '0';
|
|
end if;
|
|
if UpDateSPIReg = '1' then
|
|
UpDateSPIRegD <= '1';
|
|
end if;
|
|
SPIRegOut <= SPIRegOut(30 downto 0) & '0';
|
|
if SPIBitCount = "00000" and UpdateSPIRegD = '1' then
|
|
SPIRegOut <= HM2DataOutL;
|
|
UpdateSPIRegD <= '0';
|
|
end if;
|
|
end if;
|
|
end if;
|
|
|
|
if rising_edge(ClkLow) then
|
|
|
|
SPIReadRequest2 <= SPIReadRequest1;
|
|
SPIWriteRequest2 <= SPIWriteRequest1;
|
|
SPIHeaderFlag2 <= SPIHeaderFlag1;
|
|
|
|
SPIReadRequest1 <= SPIReadRequest;
|
|
SPIWriteRequest1 <= SPIWriteRequest;
|
|
SPIHeaderFlag1 <= SPIHeaderFlag;
|
|
|
|
FrameTimerMSBD <= FrameTimerMSB;
|
|
|
|
DCOM_SPICS <= COM_SPICS;
|
|
if DCOM_SPICS = '1' then
|
|
if FrameTimerMSB = '0' then
|
|
FrameTimer <= FrameTimer -1;
|
|
end if;
|
|
else
|
|
FrameTimer <= SPITimeout;
|
|
end if;
|
|
|
|
if Read32 = '1' then
|
|
HM2DataOutL <= HM2DataOut;
|
|
if SPIAutoInc = '1' then
|
|
SyncAddrPtr <= SyncAddrPtr +4;
|
|
end if;
|
|
end if;
|
|
|
|
Write32Pipe <= Write32Pipe(2 downto 0) & (SPIWriteRequest1 and SPIWriteRequest2) ;
|
|
|
|
if Write32 = '1' then
|
|
if SPIAutoInc = '1' then
|
|
SyncAddrPtr <= SyncAddrPtr +4;
|
|
end if;
|
|
end if;
|
|
|
|
if (SPIHeaderFlag1 = '1') and (SPIHeaderFlag2 = '1') then
|
|
SyncAddrPtr <= AddrPtr;
|
|
end if;
|
|
|
|
end if; -- clock low
|
|
|
|
if (FrameTimerMSB = '1') and (FrameTimerMSBD = '0') then -- always set header on frame timeout
|
|
SPIHeader <= '1'; -- async set header
|
|
SPIRegOut <= x"AAAAAAAA";
|
|
end if;
|
|
|
|
if (SPIReadRequest1 = '1') and (SPIReadRequest2 = '1') then
|
|
SPIReadRequest <= '0'; -- async clear request
|
|
Read32 <= '1';
|
|
else
|
|
Read32 <= '0';
|
|
end if;
|
|
|
|
|
|
if (SPIWriteRequest1 = '1') and (SPIWriteRequest2 = '1') then
|
|
SPIWriteRequest <= '0'; -- async clear request
|
|
end if;
|
|
|
|
if (SPIHeaderFlag1 = '1') and (SPIHeaderFlag2 = '1') then
|
|
SPIHeaderFlag <= '0'; -- async clear request
|
|
end if;
|
|
|
|
if COM_SPICS = '1' then -- need filter!
|
|
SPIBitCount <= "00000"; -- async clear bit count
|
|
end if;
|
|
|
|
COM_SPIOUT <= SPIRegOut(31);
|
|
TEST0 <= SPIReadRequest;
|
|
end process;
|
|
|
|
|
|
|
|
ConfigDecode : process(AddrPtr,Read32,Write32)
|
|
begin
|
|
LoadSPICS <= decodedstrobe(AddrPtr(AddrWidth-1 downto 2)&"00",x"0070",Write32);
|
|
ReadSPICS <= decodedstrobe(AddrPtr(AddrWidth-1 downto 2)&"00",x"0070",Read32);
|
|
LoadSPIReg <= decodedstrobe(AddrPtr(AddrWidth-1 downto 2)&"00",x"0074",Write32);
|
|
ReadSPIReg <= decodedstrobe(AddrPtr(AddrWidth-1 downto 2)&"00",x"0074",Read32);
|
|
end process ConfigDecode;
|
|
|
|
doreconfig: process (clklow,ReConfigreg, AddrPtr)
|
|
begin
|
|
if AddrPtr = x"7F7F" then
|
|
ReconfigSel <= '1';
|
|
else
|
|
ReconfigSel <= '0';
|
|
end if;
|
|
if rising_edge(clklow) then
|
|
if Write32 = '1' and ReconfigSel = '1' then
|
|
if HM2DataInL(7 downto 0) = x"5A" then
|
|
ReConfigReg <= '1';
|
|
end if;
|
|
end if;
|
|
end if;
|
|
RECONFIG <= not ReConfigReg;
|
|
end process doreconfig;
|
|
|
|
asimplspi: entity work.simplespi8 -- configuration serial EEPROM access SPI port
|
|
generic map
|
|
(
|
|
buswidth => 8,
|
|
div => 7, -- for divide by 8 -- 12.5 MHz
|
|
bits => 8
|
|
)
|
|
port map
|
|
(
|
|
clk => clklow,
|
|
ibus => HM2DataInL(7 downto 0),
|
|
obus => HM2DataOut(7 Downto 0),
|
|
loaddata => LoadSPIReg,
|
|
readdata => ReadSPIReg,
|
|
loadcs => LoadSPICS,
|
|
readcs => ReadSPICS,
|
|
spiclk => SPICLK,
|
|
spiin => SPIIN,
|
|
spiout => SPIOUT,
|
|
spics =>SPICS
|
|
);
|
|
|
|
ICapDecode : process(Addrptr,Write32)
|
|
begin
|
|
LoadICap <= decodedstrobe(AddrPtr(AddrWidth-1 downto 2)&"00",x"0078",Write32);
|
|
ReadICapCookie <= decodedstrobe(AddrPtr(AddrWidth-1 downto 2)&"00",x"0078",Read32);
|
|
end process ICAPDecode;
|
|
|
|
ICapSupport: process (clklow,LoadICap)
|
|
begin
|
|
if rising_edge(clklow) then
|
|
if LoadICap = '1' then
|
|
ICapI <= FixICap(HM2DataInL(15 downto 0));
|
|
ICapTimer <= "111111";
|
|
end if;
|
|
if ICapTimer /= "000000" then
|
|
ICapTimer <= ICapTimer -1;
|
|
end if;
|
|
ICapClock <= ((not ICapTImer(5)) and ICapTimer(4)); -- 16 counts wide , 32 counts late
|
|
end if;
|
|
HM2DataOut <= (others => 'Z');
|
|
if ReadICAPCookie = '1' then
|
|
HM2DataOut <= x"1CAB1CAB";
|
|
end if;
|
|
end process ICapSupport;
|
|
|
|
dofallback: if fallback generate -- do blinky red light to indicate failure to load primary bitfile
|
|
Fallbackmode : process(clklow)
|
|
begin
|
|
if rising_edge(clklow) then
|
|
blinkcount <= blinkcount +1;
|
|
end if;
|
|
NINIT <= blinkcount(25);
|
|
end process;
|
|
end generate;
|
|
|
|
donormal: if not fallback generate
|
|
NormalMode : process(clklow)
|
|
begin
|
|
NINIT <= 'Z';
|
|
end process;
|
|
end generate;
|
|
|
|
end;
|
|
|