library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; -- Created from etherhm2.bin -- On 9/14/2023 entity etherhm2 is port ( addr: in std_logic_vector(11 downto 0); clk: in std_logic; din: in std_logic_vector(23 downto 0); dout: out std_logic_vector(23 downto 0); we: in std_logic); end etherhm2; architecture syn of etherhm2 is type ram_type is array (0 to 4095) of std_logic_vector(23 downto 0); signal RAM : ram_type := ( x"000000", x"000000", x"000000", x"010000", x"8F0000", x"10025A", x"10039C", x"1003FF", x"100318", x"100239", x"40013A", x"330000", x"40012C", x"330011", x"010000", x"B00079", x"200013", x"010001", x"B00079", x"4B0000", x"B0007A", x"4000B0", x"330019", x"400031", x"33000C", x"40007C", x"B00150", x"01017F", x"850000", x"1000A0", x"32000C", x"010180", x"850000", x"000000", x"000000", x"010800", x"060000", x"E90006", x"320040", x"010806", x"060000", x"E90006", x"32002E", x"000000", x"000000", x"20000C", x"4000A8", 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