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This commit is contained in:
Thaddeus-Maximus
313
5i24/configs/hostmot2/source/uartr8b.vhd
Executable file
313
5i24/configs/hostmot2/source/uartr8b.vhd
Executable file
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.math_real.all;
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use ieee.numeric_std.all;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Simple 8 bit UART RX 32 deep FIFO version
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entity uartr8b is
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generic( clock : integer);
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port (
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clk : in std_logic;
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ibus : in std_logic_vector(7 downto 0);
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obus : out std_logic_vector(7 downto 0);
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popfifo : in std_logic;
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loadbitratel : in std_logic;
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loadbitratem : in std_logic;
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loadbitrateh : in std_logic;
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readbitratel : in std_logic;
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readbitratem : in std_logic;
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readbitrateh : in std_logic;
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clrfifo : in std_logic;
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readfifocount : in std_logic;
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loadmode : in std_logic;
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readmode : in std_logic;
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loadfilter : in std_logic;
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fifohasdata : out std_logic;
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rxmask : in std_logic;
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rxdata : in std_logic
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);
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end uartr8b;
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architecture Behavioral of uartr8b is
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-- FIFO related signals
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signal pushdata: std_logic_vector(7 downto 0);
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signal popadd: std_logic_vector(4 downto 0) := "11111";
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signal popdata: std_logic_vector(7 downto 0);
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signal datacounter: std_logic_vector(5 downto 0);
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signal push: std_logic;
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signal pop: std_logic;
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signal clear: std_logic;
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signal lfifoempty: std_logic;
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signal lfifohasdata: std_logic;
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-- uart interface related signals
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constant defaultfilter : real := round((real(clock)/5000000.0)); --default filter TC is 200 ns
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constant DDSWidth : integer := 20;
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signal BitrateDDSReg : std_logic_vector(DDSWidth-1 downto 0);
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signal BitrateDDSAccum : std_logic_vector(DDSWidth-1 downto 0);
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alias DDSMSB : std_logic is BitrateDDSAccum(DDSWidth -1);
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signal OldDDSMSB: std_logic;
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signal SampleTime: std_logic;
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signal BitCount : std_logic_vector(3 downto 0);
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signal SReg: std_logic_vector(9 downto 0);
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alias SregData: std_logic_vector(7 downto 0)is SReg(8 downto 1);
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alias StartBit: std_logic is Sreg(0);
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alias StopBit: std_logic is Sreg(9);
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signal RXPipe : std_logic_vector(1 downto 0);
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signal Go: std_logic;
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signal DAV: std_logic;
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signal ModeReg: std_logic_vector(3 downto 0);
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alias FalseStart: std_logic is ModeReg(0);
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alias OverRun: std_logic is ModeReg(1);
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alias RXMaskEn: std_logic is ModeReg(3);
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signal FilterReg: std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(integer(defaultfilter),8));
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signal FilterCount: std_logic_vector(7 downto 0);
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signal rxdatad: std_logic;
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signal RXDataFilt: std_logic;
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component SRLC32E
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--
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generic (INIT : bit_vector);
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--
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port (D : in std_logic;
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CE : in std_logic;
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CLK : in std_logic;
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A : in std_logic_vector(4 downto 0);
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Q : out std_logic);
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end component;
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begin
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fifosrl: for i in 0 to 7 generate
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asr32e: SRLC32E generic map (x"00000000") port map(
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D => pushdata(i),
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CE => push,
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CLK => clk,
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A => popadd,
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Q => popdata(i)
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);
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end generate;
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afifo: process (clk,popdata,datacounter,lfifoempty)
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begin
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if rising_edge(clk) then
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if push = '1' and pop = '0' and datacounter /= 32 then -- a push
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-- always increment the data counter if not full
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datacounter <= datacounter +1;
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popadd <= popadd +1; -- popadd must follow data down shiftreg
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end if;
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if (pop = '1') and (push = '0') and (lfifoempty = '0') then -- a pop
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datacounter <= datacounter - 1;
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popadd <= popadd -1;
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end if;
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if clear = '1' then -- a clear fifo
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popadd <= (others => '1');
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datacounter <= (others => '0');
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end if;
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end if; -- clk rise
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if datacounter = 0 then
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lfifoempty <= '1';
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else
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lfifoempty <= '0';
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end if;
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fifohasdata <= not lfifoempty;
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end process afifo;
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asimpleuartrx: process (clk,OldDDSMSB, BitrateDDSAccum, SReg, DAV,
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popfifo, clrfifo, readfifocount, datacounter,
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readbitratel, BitrateDDSReg, readbitratem,
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readbitrateh, popdata, readmode, ModeReg, rxmask, lfifoempty)
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begin
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report "Default FilterReg = " & integer'image(integer(defaultfilter));
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if rising_edge(clk) then
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RXDataD <= rxdata;
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RXPipe <= RXPipe(0) & RXDataFilt; -- Two stage rx data pipeline to compensate for
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-- two clock delay from start bit detection to acquire loop startup
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if (RXDataD = '1') and (FilterCount < FilterReg) then -- simple digital filter on rxdata
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FilterCount <= FilterCount + 1;
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end if;
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if (RXDataD = '0') and (FilterCount /= 0) then
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FilterCount <= FilterCount -1;
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end if;
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if FilterCount >= FilterReg then
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RXDataFilt<= '1';
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end if;
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if FilterCount = 0 then
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RXDataFilt<= '0';
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end if;
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if Go = '1' then
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BitRateDDSAccum <= BitRateDDSAccum + BitRateDDSReg;
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if SampleTime = '1' then
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if BitCount = 0 then
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Go <= '0';
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DAV <= '1';
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if RXPipe(1) = '0' then
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OverRun <= '1';
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end if;
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end if;
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if BitCount = "1001" then -- false start bit check
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if RXPipe(1) = '1' then
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Go <= '0';
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FalseStart <= '1';
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end if;
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end if;
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SReg <= RXPipe(1) & SReg(9 downto 1); -- right shift = LSb first
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BitCount <= BitCount -1;
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end if;
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else
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BitRateDDSAccum <= (others => '0');
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BitCount <= "1001";
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end if;
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if Go = '0' and RXDataFilt = '0' and (rxmask and RXMaskEn) = '0' then -- start bit detection
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Go <= '1';
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end if;
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if DAV = '1' then -- DAV is just one clock wide
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DAV <= '0';
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end if;
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OldDDSMSB <= DDSMSB; -- for Phase accumulator MSB edge detection
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if loadbitratel = '1' then
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BitRateDDSReg(7 downto 0) <= ibus;
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end if;
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if loadbitratem = '1' then
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BitRateDDSReg(15 downto 8) <= ibus;
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end if;
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if loadbitrateh = '1' then
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BitRateDDSReg(19 downto 16) <= ibus(3 downto 0);
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end if;
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if loadmode= '1' then
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ModeReg <= ibus(3 downto 0);
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end if;
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if loadfilter= '1' then
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FilterReg <= ibus;
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end if;
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end if; -- clk
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SampleTime <= (not OldDDSMSB) and DDSMSB; -- sample on rising edge of DDS MSB
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pushdata <= SRegData;
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push <= DAV;
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pop <= popfifo;
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clear <= clrfifo;
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obus <= (others => 'Z');
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if readfifocount = '1' then
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obus(5 downto 0) <= datacounter;
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obus(7 downto 6) <= (others => '0');
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end if;
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if readbitratel = '1' then
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obus <= BitRateDDSReg(7 downto 0);
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end if;
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if readbitratem = '1' then
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obus <= BitRateDDSReg(15 downto 8);
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end if;
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if readbitrateh = '1' then
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obus(3 downto 0) <= BitRateDDSReg(19 downto 16);
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end if;
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if popfifo = '1' then
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obus <= popdata;
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end if;
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if readmode = '1' then
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obus(3 downto 0) <= ModeReg;
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obus(6) <= rxmask;
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obus(7) <= not lfifoempty;
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end if;
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fifohasdata <= not lfifoempty;
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end process asimpleuartrx;
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end Behavioral;
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