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This commit is contained in:
Thaddeus-Maximus
359
5i24/configs/hostmot2/source/uartr.vhd
Executable file
359
5i24/configs/hostmot2/source/uartr.vhd
Executable file
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- Simple UART with 32 bit bus interface
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-- 16 byte deep receive FIFO
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-- Can read 4,3,2,1 bytes from FIFO depending on data register read offset
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-- Base Address = 1 byte
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-- Base Address +1 = 2 bytes
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-- Base Address +2 = 3 bytes
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-- Base Address +3 = 4 bytes
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entity uartr is
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port (
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clk : in std_logic;
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ibus : in std_logic_vector(31 downto 0);
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obus : out std_logic_vector(31 downto 0);
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addr : in std_logic_vector(1 downto 0);
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popfifo : in std_logic;
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loadbitrate : in std_logic;
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readbitrate : in std_logic;
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clrfifo : in std_logic;
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readfifocount : in std_logic;
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loadmode : in std_logic;
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readmode : in std_logic;
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fifohasdata : out std_logic;
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rxmask : in std_logic;
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rxdata : in std_logic
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);
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end uartr;
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architecture Behavioral of uartr is
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-- FIFO related signals
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signal pushdata: std_logic_vector(7 downto 0);
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signal popadd0: std_logic_vector(3 downto 0) := x"f";
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signal popadd1: std_logic_vector(3 downto 0) := x"f";
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signal popadd2: std_logic_vector(3 downto 0) := x"f";
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signal popadd3: std_logic_vector(3 downto 0) := x"f";
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signal popdata: std_logic_vector(31 downto 0);
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signal datacounter: std_logic_vector(4 downto 0);
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signal push: std_logic;
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signal pop: std_logic;
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signal popsize: std_logic_vector(2 downto 0);
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signal clear: std_logic;
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signal lfifoempty: std_logic;
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signal lfifohasdata: std_logic;
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-- uart interface related signals
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constant DDSWidth : integer := 20;
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signal BitrateDDSReg : std_logic_vector(DDSWidth-1 downto 0);
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signal BitrateDDSAccum : std_logic_vector(DDSWidth-1 downto 0);
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alias DDSMSB : std_logic is BitrateDDSAccum(DDSWidth-1);
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signal OldDDSMSB: std_logic;
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signal SampleTime: std_logic;
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signal BitCount : std_logic_vector(3 downto 0);
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signal BytePointer : std_logic_vector(2 downto 0) := "000";
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signal SReg: std_logic_vector(9 downto 0);
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alias SregData: std_logic_vector(7 downto 0)is SReg(8 downto 1);
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alias StartBit: std_logic is Sreg(0);
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alias StopBit: std_logic is Sreg(9);
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signal RXPipe : std_logic_vector(1 downto 0);
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signal Go: std_logic;
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signal DAV: std_logic;
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signal ModeReg: std_logic_vector(5 downto 0);
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alias FalseStart: std_logic is ModeReg(0);-- started recieve but middle of start bit is '1'
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alias OverRun: std_logic is ModeReg(1); -- '0' where stop bit should be
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alias RXMaskEn: std_logic is ModeReg(3); -- enable TXEN of transmit side to disable receive
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alias FIFOError: std_logic is ModeReg(4); -- pop with no or not enough data
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alias LostData: std_logic is ModeReg(5); -- data overrun
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component SRL16E
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--
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generic (INIT : bit_vector);
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--
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port (D : in std_logic;
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CE : in std_logic;
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CLK : in std_logic;
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A0 : in std_logic;
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A1 : in std_logic;
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A2 : in std_logic;
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A3 : in std_logic;
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Q : out std_logic);
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end component;
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begin
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fifosrl0: for i in 0 to 7 generate
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asr16e: SRL16E generic map (x"0000") port map(
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D => pushdata(i),
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CE => push,
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CLK => clk,
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A0 => popadd0(0),
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A1 => popadd0(1),
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A2 => popadd0(2),
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A3 => popadd0(3),
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Q => popdata(i)
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);
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end generate;
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fifosrl1: for i in 0 to 7 generate
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asr16e: SRL16E generic map (x"0000") port map(
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D => pushdata(i),
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CE => push,
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CLK => clk,
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A0 => popadd1(0),
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A1 => popadd1(1),
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A2 => popadd1(2),
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A3 => popadd1(3),
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Q => popdata(8+i)
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);
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end generate;
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fifosrl2: for i in 0 to 7 generate
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asr16e: SRL16E generic map (x"0000") port map(
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D => pushdata(i),
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CE => push,
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CLK => clk,
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A0 => popadd2(0),
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A1 => popadd2(1),
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A2 => popadd2(2),
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A3 => popadd2(3),
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Q => popdata(16+i)
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);
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end generate;
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fifosrl3: for i in 0 to 7 generate
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asr16e: SRL16E generic map (x"0000") port map(
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D => pushdata(i),
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CE => push,
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CLK => clk,
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A0 => popadd3(0),
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A1 => popadd3(1),
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A2 => popadd3(2),
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A3 => popadd3(3),
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Q => popdata(24+i)
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);
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end generate;
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afifo: process (clk,popdata,datacounter)
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begin
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if rising_edge(clk) then
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if push = '1' and pop = '0' then
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if datacounter /= 16 then -- a push
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-- always increment the data counter if not full
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datacounter <= datacounter +1;
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popadd0 <= popadd0 +1; -- popadd must follow data down shiftreg
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else
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LostData <= '1';
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end if;
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end if;
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if (pop = '1') and (push = '0') then -- a pop
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if datacounter >= popsize then
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datacounter <= datacounter - popsize;
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popadd0 <= popadd0 - popsize;
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else
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FIFOError <= '1';
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end if;
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end if;
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if (pop = '1') and (push = '1') then -- simultaneaous pop and push
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if datacounter >= popsize then -- note pushdata was not available
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-- when read occured so compare datacounter with popsize
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datacounter <= datacounter - (addr);
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popadd0 <= popadd0 - (addr);
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else -- if pop is not valid, just do push part
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datacounter <= datacounter +1;
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popadd0 <= popadd0 +1;
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FIFOError <= '1';
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end if;
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end if;
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if clear = '1' then -- a clear fifo
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popadd0 <= (others => '1');
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datacounter <= (others => '0');
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LostData <= '0';
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FIFOError <= '0';
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end if;
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end if; -- clk rise
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-- The way this mess works is that we have 4 byte wide FIFOs with duplicated data
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-- but the readout point is shifted by one byte for each succeeding FIFO so we can read up to
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-- 32 bits (4 bytes) at once. Wasteful, but SRL16s are cheap
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popadd1 <= popadd0 -1; -- note that these are not forced to 0 on underflow
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popadd2 <= popadd0 -2; -- so unused bytes of a less than 4 byte read
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popadd3 <= popadd0 -3; -- will be stale recv data - not good for security reasons!
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-- if this matters, force to 0 on underflow will result in duplicated
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-- current data on unused bytes.
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popsize <= ('0'&addr) +1;
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if datacounter = 0 then
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lfifoempty <= '1';
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else
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lfifoempty <= '0';
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end if;
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fifohasdata <= not lfifoempty;
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end process afifo;
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asimpleuartrx: process (clk)
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begin
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if rising_edge(clk) then
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RXPipe <= RXPipe(0) & rxdata; -- Two stage rx data pipeline to compensate for
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-- two clock delay from start bit detection to acquire loop startup
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if Go = '1' then
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BitRateDDSAccum <= BitRateDDSAccum + BitRateDDSReg;
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if SampleTime = '1' then
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if BitCount = 0 then
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Go <= '0';
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DAV <= '1';
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if RXPipe(1) = '0' then
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OverRun <= '1';
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end if;
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end if;
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if BitCount = "1001" then -- false start bit check
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if RXPipe(1) = '1' then
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Go <= '0'; -- abort receive
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FalseStart <= '1';
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end if;
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end if;
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SReg <= RXPipe(1) & SReg(9 downto 1); -- right shift = LSb first
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BitCount <= BitCount -1;
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end if;
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else
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BitRateDDSAccum <= (others => '0');
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BitCount <= "1001";
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end if;
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if Go = '0' and rxdata = '0' and (rxmask and RXMaskEn) = '0' then -- start bit detection
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Go <= '1';
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end if;
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if DAV = '1' then -- DAV is just one clock wide
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DAV <= '0';
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end if;
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OldDDSMSB <= DDSMSB; -- for Phase accumulator MSB edge detection
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if loadbitrate = '1' then
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BitRateDDSReg <= ibus(DDSWidth-1 downto 0);
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end if;
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if loadmode= '1' then
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ModeReg(3 downto 0) <= ibus(3 downto 0);
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end if;
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end if; -- clk
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SampleTime <= (not OldDDSMSB) and DDSMSB; -- sample on rising edge of DDS MSB
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pushdata <= SRegData;
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push <= DAV;
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pop <= popfifo;
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clear <= clrfifo;
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obus <= (others => 'Z');
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if readfifocount = '1' then
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obus(4 downto 0) <= datacounter;
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-- obus(31 downto 5) <= (others => '0');
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end if;
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if readbitrate = '1' then
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obus(DDSWidth-1 downto 0) <= BitRateDDSReg;
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end if;
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if popfifo = '1' then
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obus <= popdata;
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end if;
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if readmode = '1' then
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obus(5 downto 0) <= ModeReg;
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obus(6) <= rxmask;
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obus(7) <= not lfifoempty;
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end if;
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fifohasdata <= not lfifoempty;
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end process asimpleuartrx;
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end Behavioral;
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