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This commit is contained in:
Thaddeus-Maximus
858
5i24/configs/hostmot2/source/sserialwa.vhd
Executable file
858
5i24/configs/hostmot2/source/sserialwa.vhd
Executable file
@@ -0,0 +1,858 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--
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-- Copyright (C) 2010, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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||||
-- licensing terms:
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--
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||||
-- * GNU General Public License (GPL), version 2.0 or later
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||||
-- * 3-clause BSD License
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||||
--
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--
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||||
-- The GNU GPL License:
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--
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||||
-- This program is free software; you can redistribute it and/or modify
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||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
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||||
-- (at your option) any later version.
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||||
--
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||||
-- This program is distributed in the hope that it will be useful,
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||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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||||
-- GNU General Public License for more details.
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||||
--
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||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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||||
--
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||||
--
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||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
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||||
--
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||||
-- * Redistributions of source code must retain the above copyright
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||||
-- notice, this list of conditions and the following disclaimer.
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||||
--
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||||
-- * Redistributions in binary form must reproduce the above
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||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
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||||
-- provided with the distribution.
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||||
--
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-- * Neither the name of Mesa Electronics nor the names of its
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||||
-- contributors may be used to endorse or promote products
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||||
-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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use work.log2.all;
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use work.decodedstrobe.all;
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use work.oneofndecode.all;
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entity sserialwa is
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generic (
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Ports : integer;
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InterfaceRegs : integer; -- must be power of 2
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BaseClock : integer;
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NeedCRC8 : boolean
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);
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port (
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clk : in std_logic;
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clkmed : in std_logic;
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ibus : in std_logic_vector(31 downto 0);
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obus : out std_logic_vector(31 downto 0);
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hloadcommand : in std_logic;
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hreadcommand : in std_logic;
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hloaddata : in std_logic;
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hreaddata : in std_logic;
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regaddr : in std_logic_vector(log2(InterfaceRegs) -1 downto 0);
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hloadregs0 : in std_logic;
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hreadregs0 : in std_logic;
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hloadregs1 : in std_logic;
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hreadregs1 : in std_logic;
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hloadregs2 : in std_logic;
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hreadregs2 : in std_logic;
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hloadregs3 : in std_logic;
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hreadregs3 : in std_logic;
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rxserial : in std_logic_vector(Ports -1 downto 0);
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txserial : out std_logic_vector(Ports -1 downto 0);
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txenable : out std_logic_vector(Ports -1 downto 0);
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ntxenable : out std_logic_vector(Ports -1 downto 0);
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testbit : out std_logic
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);
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end sserialwa;
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architecture Behavioral of sserialwa is
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signal iabus: std_logic_vector(10 downto 0);
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signal idbus: std_logic_vector(15 downto 0);
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signal mradd: std_logic_vector(11 downto 0);
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signal mwadd: std_logic_vector(11 downto 0);
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signal fixedmra: std_logic_vector(9 downto 0);
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signal fixedmwa: std_logic_vector(9 downto 0);
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signal mobus: std_logic_vector(7 downto 0);
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signal mwrite: std_logic;
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signal mread: std_logic;
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-- data memory partitioning--
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signal muxedmibus: std_logic_vector(7 downto 0); -- the data input path to the processor
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signal ramdata: std_logic_vector(7 downto 0); -- and its sources
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signal iodata: std_logic_vector(7 downto 0);
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signal ioradd: std_logic_vector(11 downto 0);
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signal writedram: std_logic;
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-- host interface signals
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signal hcommandreg: std_logic_vector(15 downto 0);
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alias romwrena : std_logic is hcommandreg(14); -- if high, reset CPU and allow read/write CPU ROM access
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signal syncromwrena : std_logic;
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signal hdatareg: std_logic_vector(7 downto 0);
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signal lloadcommand: std_logic;
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signal lloadcommand1: std_logic;
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signal lreadcommandl: std_logic;
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signal lreadcommandh: std_logic;
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signal lclrhdoorbell: std_logic;
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signal lreadhdoorbell: std_logic;
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signal clrhdoorbellreq1: std_logic;
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signal clrhdoorbellreq2: std_logic;
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signal hdoorbell: std_logic;
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signal ldatareg: std_logic_vector(7 downto 0);
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signal lloaddata: std_logic;
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signal lreaddata: std_logic;
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signal romdata: std_logic_vector(15 downto 0);
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signal romdatabuf: std_logic_vector(15 downto 0);
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signal loadrom: std_logic;
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signal hloadrom: std_logic;
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signal loadromreq1: std_logic;
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signal loadromreq2: std_logic;
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-- UART interface signals (RX)
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signal loadrxfiltersel: std_logic;
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signal readrxdatasel: std_logic;
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signal loadrxbitratelsel: std_logic;
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signal loadrxbitratemsel: std_logic;
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signal loadrxbitratehsel: std_logic;
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signal clearrxfifosel: std_logic;
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signal readrxfifocountsel: std_logic;
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signal readrxmodesel: std_logic;
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signal loadrxmodesel: std_logic;
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signal loadrxfilter: std_logic_vector(Ports-1 downto 0);
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signal readrxdata: std_logic_vector(Ports-1 downto 0);
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signal loadrxbitratel: std_logic_vector(Ports-1 downto 0);
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signal loadrxbitratem: std_logic_vector(Ports-1 downto 0);
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signal loadrxbitrateh: std_logic_vector(Ports-1 downto 0);
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signal clearrxfifo: std_logic_vector(Ports-1 downto 0);
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signal readrxfifocount: std_logic_vector(Ports-1 downto 0);
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signal readrxmode: std_logic_vector(Ports-1 downto 0);
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signal loadrxmode: std_logic_vector(Ports-1 downto 0);
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signal rxfifohasdata: std_logic_vector(Ports-1 downto 0);
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signal drven: std_logic_vector(Ports-1 downto 0); -- for half duplex rx mask
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signal rxdata: std_logic_vector(Ports-1 downto 0);
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-- UART interface signals (TX)
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signal loadtxdatasel: std_logic;
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signal loadtxbitratelsel: std_logic;
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signal loadtxbitratemsel: std_logic;
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signal loadtxbitratehsel: std_logic;
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signal readtxbitratelsel: std_logic;
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signal readtxbitratemsel: std_logic;
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signal readtxbitratehsel: std_logic;
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signal cleartxfifosel: std_logic;
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signal readtxfifocountsel: std_logic;
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signal loadtxmodesel: std_logic;
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signal readtxmodesel: std_logic;
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signal loadtxdata: std_logic_vector(Ports-1 downto 0);
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signal loadtxbitratel: std_logic_vector(Ports-1 downto 0);
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signal loadtxbitratem: std_logic_vector(Ports-1 downto 0);
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signal loadtxbitrateh: std_logic_vector(Ports-1 downto 0);
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--signal readtxbitratel: std_logic_vector(Ports-1 downto 0);
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--signal readtxbitratem: std_logic_vector(Ports-1 downto 0);
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--signal readtxbitrateh: std_logic_vector(Ports-1 downto 0);
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signal cleartxfifo: std_logic_vector(Ports-1 downto 0);
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signal readtxfifocount: std_logic_vector(Ports-1 downto 0);
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signal loadtxmode: std_logic_vector(Ports-1 downto 0);
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signal readtxmode: std_logic_vector(Ports-1 downto 0);
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signal txfifoempty: std_logic_vector(Ports-1 downto 0);
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signal txdata: std_logic_vector(Ports-1 downto 0);
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-- interface RAM 8-32 shim signals
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signal hibus32_0: std_logic_vector(31 downto 0);
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signal hibus32_1: std_logic_vector(31 downto 0);
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signal hibus32_2: std_logic_vector(31 downto 0);
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signal hibus32_3: std_logic_vector(31 downto 0);
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signal libus32_0: std_logic_vector(31 downto 0);
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signal libus32_1: std_logic_vector(31 downto 0);
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signal libus32_2: std_logic_vector(31 downto 0);
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signal libus32_3: std_logic_vector(31 downto 0);
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signal lobus32: std_logic_vector(31 downto 0);
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signal lobus24: std_logic_vector(23 downto 0);
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signal libuslatch: std_logic_vector(31 downto 8);
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signal latchtop24: std_logic;
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signal writeiram: std_logic;
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signal lwriteiram0: std_logic;
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signal lwriteiram1: std_logic;
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signal lwriteiram2: std_logic;
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signal lwriteiram3: std_logic;
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signal lwriteiram: std_logic;
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signal lreadiram: std_logic;
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-- debug test bit out
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signal ltestbit: std_logic;
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signal lsettestbit: std_logic;
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signal lclrtestbit: std_logic;
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-- timer signals
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signal lreadtimerl: std_logic;
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signal lreadtimerh: std_logic;
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signal lwritetimerl: std_logic;
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signal lwritetimerh: std_logic;
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signal timerdiv: std_logic_vector(15 downto 0);
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signal timeracc: std_logic_vector(15 downto 0);
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signal timerlatch: std_logic_vector(7 downto 0);
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signal timercount: std_logic_vector(15 downto 0);
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alias timermsb: std_logic is timeracc(15);
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-- doorbell signals
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signal doorbellreg: std_logic_vector(InterfaceRegs-1 downto 0);
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signal readdoorbell: std_logic;
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signal cleardoorbell: std_logic;
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-- read back baseclock signals
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signal lreadclock: std_logic;
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signal baseclockslv: std_logic_vector(31 downto 0);
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-- read back # of channels
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signal lreadchannels: std_logic;
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-- crc8 signals
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signal newxor: std_logic_vector(7 downto 0);
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signal lreadcrc: std_logic;
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signal lwritecrc: std_logic;
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signal lclearcrc: std_logic;
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begin
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-- processor: entity work.DumbAss8sqw -- firmware version 36 and below
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processor: entity work.DumbAss8sqws -- firmware version 37 and above
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port map (
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clk => clkmed,
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reset => syncromwrena,
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iabus => iabus, -- program address bus
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idbus => idbus, -- program data bus
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mradd => mradd, -- memory read address
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mwadd => mwadd, -- memory write address
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mibus => muxedmibus,
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-- memory data in bus
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mobus => mobus, -- memory data out bus
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mwrite => mwrite, -- memory write signal
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mread => mread -- memory read signal
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-- carryflg => -- carry flag
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);
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sserialrom: entity work.sslbp
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port map(
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addra => hcommandreg(10 downto 0), -- 2k (x16)
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addrb => iabus(10 downto 0),
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clk => clkmed,
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dina => romdatabuf,
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douta => romdata,
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doutb => idbus,
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wea => loadrom
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);
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DataRam : entity work.sslbpram -- this is for the new pre-initialized RAM with sendstrings
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-- DataRam : entity work.dpram -- this is for the old generic empty RAM
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-- generic map (
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-- width => 8,
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-- depth => 1024
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-- )
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port map(
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addra => fixedmwa,
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addrb => fixedmra,
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clk => clkmed,
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dina => mobus,
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-- douta =>
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doutb => ramdata,
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wea => writedram
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);
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interfaceramout0: entity work.adpram
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generic map (
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width => 32,
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depth => InterFaceRegs
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)
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port map(
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addra => mwadd(log2(InterfaceRegs) +1 downto 2),
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addrb => regaddr,
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clk => clkmed,
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dina => lobus32,
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-- douta =>
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doutb => hibus32_0,
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wea => lwriteiram0
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);
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interfaceramin0: entity work.adpram
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generic map (
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width => 32,
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depth => InterFaceRegs
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)
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port map(
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addra => regaddr,
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addrb => ioradd(log2(InterfaceRegs) +1 downto 2),
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clk => clk,
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dina => ibus,
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-- douta =>
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doutb => libus32_0,
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wea => hloadregs0
|
||||
);
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interfaceramout1: entity work.adpram
|
||||
generic map (
|
||||
width => 32,
|
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depth => InterFaceRegs
|
||||
)
|
||||
port map(
|
||||
addra => mwadd(log2(InterfaceRegs) +1 downto 2),
|
||||
addrb => regaddr,
|
||||
clk => clkmed,
|
||||
dina => lobus32,
|
||||
-- douta =>
|
||||
doutb => hibus32_1,
|
||||
wea => lwriteiram1
|
||||
);
|
||||
|
||||
interfaceramin1: entity work.adpram
|
||||
generic map (
|
||||
width => 32,
|
||||
depth => InterFaceRegs
|
||||
)
|
||||
port map(
|
||||
addra => regaddr,
|
||||
addrb => ioradd(log2(InterfaceRegs) +1 downto 2),
|
||||
clk => clk,
|
||||
dina => ibus,
|
||||
-- douta =>
|
||||
doutb => libus32_1,
|
||||
wea => hloadregs1
|
||||
);
|
||||
|
||||
interfaceramout2: entity work.adpram
|
||||
generic map (
|
||||
width => 32,
|
||||
depth => InterFaceRegs
|
||||
)
|
||||
port map(
|
||||
addra => mwadd(log2(InterfaceRegs) +1 downto 2),
|
||||
addrb => regaddr,
|
||||
clk => clkmed,
|
||||
dina => lobus32,
|
||||
-- douta =>
|
||||
doutb => hibus32_2,
|
||||
wea => lwriteiram2
|
||||
);
|
||||
|
||||
interfaceramin2: entity work.adpram
|
||||
generic map (
|
||||
width => 32,
|
||||
depth => InterFaceRegs
|
||||
)
|
||||
port map(
|
||||
addra => regaddr,
|
||||
addrb => ioradd(log2(InterfaceRegs) +1 downto 2),
|
||||
clk => clk,
|
||||
dina => ibus,
|
||||
-- douta =>
|
||||
doutb => libus32_2,
|
||||
wea => hloadregs2
|
||||
);
|
||||
|
||||
interfaceramout3: entity work.adpram
|
||||
generic map (
|
||||
width => 32,
|
||||
depth => InterFaceRegs
|
||||
)
|
||||
port map(
|
||||
addra => mwadd(log2(InterfaceRegs) +1 downto 2),
|
||||
addrb => regaddr,
|
||||
clk => clkmed,
|
||||
dina => lobus32,
|
||||
-- douta =>
|
||||
doutb => hibus32_3,
|
||||
wea => lwriteiram3
|
||||
);
|
||||
|
||||
interfaceramin3: entity work.adpram
|
||||
generic map (
|
||||
width => 32,
|
||||
depth => InterFaceRegs
|
||||
)
|
||||
port map(
|
||||
addra => regaddr,
|
||||
addrb => ioradd(log2(InterfaceRegs) +1 downto 2),
|
||||
clk => clk,
|
||||
dina => ibus,
|
||||
-- douta =>
|
||||
doutb => libus32_3,
|
||||
wea => hloadregs3
|
||||
);
|
||||
|
||||
makeUARTRs: for i in 0 to Ports -1 generate
|
||||
auarrx: entity work.uartr8
|
||||
generic map (
|
||||
Clock => BaseClock
|
||||
)
|
||||
port map (
|
||||
clk => clkmed,
|
||||
ibus => mobus,
|
||||
obus => iodata,
|
||||
popfifo => readrxdata(i),
|
||||
loadbitratel => loadrxbitratel(i),
|
||||
loadbitratem => loadrxbitratem(i),
|
||||
loadbitrateh => loadrxbitrateh(i),
|
||||
readbitratel => '0',
|
||||
readbitratem => '0',
|
||||
readbitrateh => '0',
|
||||
clrfifo => clearrxfifo(i),
|
||||
readfifocount => readrxfifocount(i),
|
||||
loadmode => loadrxmode(i),
|
||||
readmode => readrxmode(i),
|
||||
loadfilter => loadrxfilter(i),
|
||||
fifohasdata => rxfifohasdata(i),
|
||||
rxmask => drven(i), -- for half duplex rx mask
|
||||
rxdata => rxdata(i)
|
||||
);
|
||||
end generate;
|
||||
|
||||
makeUARTTXs: for i in 0 to Ports -1 generate
|
||||
auartx: entity work.uartx8
|
||||
port map (
|
||||
clk => clkmed,
|
||||
ibus => mobus,
|
||||
obus => iodata,
|
||||
pushfifo => loadtxdata(i),
|
||||
loadbitratel => loadtxbitratel(i),
|
||||
loadbitratem => loadtxbitratem(i),
|
||||
loadbitrateh => loadtxbitrateh(i),
|
||||
readbitratel => '0', -- readtxbitratel(i), for debug
|
||||
readbitratem => '0', -- readtxbitratem(i), for debug
|
||||
readbitrateh => '0', -- readtxbitrateh(i), for debug
|
||||
clrfifo => cleartxfifo(i),
|
||||
readfifocount => readtxfifocount(i),
|
||||
loadmode => loadtxmode(i),
|
||||
readmode => readtxmode(i),
|
||||
fifoempty => txfifoempty(i),
|
||||
txen => '1',
|
||||
drven => drven(i),
|
||||
txdata => txData(i)
|
||||
);
|
||||
end generate;
|
||||
|
||||
iobus: process(clkmed,ioradd,ramdata,iodata,mradd,mwadd)
|
||||
begin
|
||||
if rising_edge(clkmed) then
|
||||
ioradd <= mradd;
|
||||
end if;
|
||||
|
||||
if ioradd(9) = '0' then
|
||||
muxedmibus <= ramdata; -- RAM is 0,1FF and 400,5FF
|
||||
else
|
||||
muxedmibus <= iodata; -- I/O space is 200,3FF and 600,7FF
|
||||
end if;
|
||||
|
||||
fixedmra <= mradd(10)& mradd(8 downto 0);
|
||||
fixedmwa <= mwadd(10)& mwadd(8 downto 0);
|
||||
|
||||
end process iobus;
|
||||
|
||||
|
||||
hostinterface : process (clk, clkmed, hloaddata, romwrena, hreadcommand,lreadhdoorbell,hdoorbell,
|
||||
hreaddata, ldatareg, romdata, lreadcommandl, lloadcommand1,
|
||||
lreadcommandh, hcommandreg, lreaddata, hdatareg, clrhdoorbellreq2, ltestbit)
|
||||
begin
|
||||
-- first host writes
|
||||
if rising_edge(clk) then
|
||||
-- first host writes
|
||||
if hloadcommand = '1' and ibus(31) = '0' then -- disable command regs write if data MSB = 0
|
||||
hcommandreg <= ibus(15 downto 0); -- this is for DMA/TRAM where write side effects
|
||||
hdoorbell <= '1'; -- must be data dependent
|
||||
end if;
|
||||
|
||||
if hloaddata = '1' and romwrena = '1' then -- request to write data to rom on host datareg writes
|
||||
hloadrom <= '1';
|
||||
romdatabuf <= ibus(15 downto 0);
|
||||
else
|
||||
hloadrom <= '0';
|
||||
end if;
|
||||
|
||||
if hloaddata = '1' then
|
||||
hdatareg <= ibus(7 downto 0);
|
||||
end if;
|
||||
end if; -- clk
|
||||
|
||||
-- next local writes and sync logic
|
||||
|
||||
if rising_edge(clkmed) then
|
||||
clrhdoorbellreq2 <= clrhdoorbellreq1;
|
||||
loadromreq2 <= loadromreq1;
|
||||
loadromreq1 <= hloadrom;
|
||||
syncromwrena <= romwrena;
|
||||
lloadcommand1 <= lloadcommand;
|
||||
if (loadromreq2 = '1') and (loadromreq1 = '0') then --write data to ROM on trailig edge of host datareg writes
|
||||
loadrom <= '1';
|
||||
else
|
||||
loadrom <= '0';
|
||||
end if;
|
||||
|
||||
if lclrhdoorbell = '1' then
|
||||
clrhdoorbellreq1 <= '1';
|
||||
end if;
|
||||
|
||||
if lloaddata = '1' then
|
||||
ldatareg <= mobus;
|
||||
end if;
|
||||
|
||||
if lsettestbit = '1' then
|
||||
ltestbit <= '1';
|
||||
end if;
|
||||
|
||||
if lclrtestbit = '1' then
|
||||
ltestbit <= '0';
|
||||
end if;
|
||||
end if; -- clkmed
|
||||
|
||||
if lloadcommand1 = '1' then -- async clear command reg
|
||||
hcommandreg <= (others => '0');
|
||||
end if;
|
||||
|
||||
|
||||
if (clrhdoorbellreq2 = '1') then
|
||||
hdoorbell <= '0';
|
||||
clrhdoorbellreq1 <= '0';
|
||||
end if;
|
||||
|
||||
-- then the reads
|
||||
-- first the host reads
|
||||
obus <= (others => 'Z');
|
||||
if hreaddata = '1' then
|
||||
if romwrena = '0' then -- normally just read the data register
|
||||
obus(7 downto 0) <= ldatareg;
|
||||
obus(31 downto 8) <= (others => '0');
|
||||
else
|
||||
obus(15 downto 0) <= romdata; -- but if romwrena set, read the ROM data
|
||||
obus(31 downto 16) <=(others => '0');
|
||||
end if;
|
||||
end if;
|
||||
if hreadcommand = '1' then
|
||||
obus(15 downto 0) <= hcommandreg; -- host readback command reg
|
||||
obus(31 downto 16) <=(others => '0');
|
||||
end if;
|
||||
|
||||
iodata <= (others => 'Z');
|
||||
if lreadcommandl= '1' then
|
||||
iodata <= hcommandreg(7 downto 0);
|
||||
end if;
|
||||
if lreadcommandh = '1' then
|
||||
iodata <= hcommandreg(15 downto 8);
|
||||
end if;
|
||||
|
||||
if lreaddata = '1' then
|
||||
iodata <= hdatareg;
|
||||
end if;
|
||||
|
||||
if lreadhdoorbell = '1' then
|
||||
iodata(0) <= hdoorbell;
|
||||
iodata(7 downto 1) <= (others => '0');
|
||||
end if;
|
||||
|
||||
|
||||
testbit <= ltestbit;
|
||||
end process hostinterface;
|
||||
|
||||
WidthShim : process (clkmed, lreadiram, ioradd, libus32_0, libus32_1, libus32_2, libuslatch,
|
||||
hreadregs0,hreadregs1, hreadregs2, hibus32_0, hibus32_1, hibus32_2,
|
||||
mwadd, lwriteiram, writeiram, mobus, lobus24, libus32_3, hreadregs3, hibus32_3)
|
||||
begin
|
||||
-- first the writes
|
||||
-- local to host
|
||||
if rising_edge(clkmed) then
|
||||
if writeiram = '1' then
|
||||
lobus24 <= (others => '0'); -- clear the latch after write to RAM
|
||||
end if;
|
||||
if lwriteiram = '1' then -- local write to any of the RAMs
|
||||
case mwadd(1 downto 0) is
|
||||
when "00" => lobus24(7 downto 0) <= mobus;
|
||||
when "01" => lobus24(15 downto 8) <= mobus;
|
||||
when "10" => lobus24(23 downto 16) <= mobus;
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
if latchtop24 = '1' then
|
||||
case ioradd(6 downto 5) is
|
||||
when "00" => libuslatch <= libus32_0(31 downto 8);
|
||||
when "01" => libuslatch <= libus32_1(31 downto 8);
|
||||
when "10" => libuslatch <= libus32_2(31 downto 8);
|
||||
when "11" => libuslatch <= libus32_3(31 downto 8);
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end if; -- clkmed
|
||||
writeiram <= decodedstrobe(mwadd(1 downto 0),"11",lwriteiram); -- write on MS byte
|
||||
lwriteiram0 <= decodedstrobe(mwadd(6 downto 5),"00",writeiram); --
|
||||
lwriteiram1 <= decodedstrobe(mwadd(6 downto 5),"01",writeiram);
|
||||
lwriteiram2 <= decodedstrobe(mwadd(6 downto 5),"10",writeiram);
|
||||
lwriteiram3 <= decodedstrobe(mwadd(6 downto 5),"11",writeiram);
|
||||
lobus32 <= mobus & lobus24;
|
||||
-- then the reads
|
||||
iodata <= (others => 'Z');
|
||||
latchtop24 <= '0';
|
||||
if lreadiram = '1' then
|
||||
if ioradd(1 downto 0) = "00" then -- on a local read we read the bottom 8 bits
|
||||
case ioradd(6 downto 5) is
|
||||
when "00" => iodata <= libus32_0(7 downto 0);
|
||||
when "01" => iodata <= libus32_1(7 downto 0);
|
||||
when "10" => iodata <= libus32_2(7 downto 0);
|
||||
when "11" => iodata <= libus32_3(7 downto 0);
|
||||
when others => null;
|
||||
end case;
|
||||
latchtop24 <= '1'; -- and signal to latch the other 24
|
||||
end if; -- so we sample all 32 bits at once
|
||||
case ioradd(1 downto 0) is
|
||||
when "01" => iodata <= libuslatch(15 downto 8);
|
||||
when "10" => iodata <= libuslatch(23 downto 16);
|
||||
when "11" => iodata <= libuslatch(31 downto 24);
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
obus <= (others => 'Z');
|
||||
if hreadregs0 = '1' then
|
||||
obus <= hibus32_0;
|
||||
end if;
|
||||
if hreadregs1 = '1' then
|
||||
obus <= hibus32_1;
|
||||
end if;
|
||||
if hreadregs2 = '1' then
|
||||
obus <= hibus32_2;
|
||||
end if;
|
||||
if hreadregs3 = '1' then
|
||||
obus <= hibus32_3;
|
||||
end if;
|
||||
end process WidthShim;
|
||||
|
||||
atimer: process(clkmed,lreadtimerl,lreadtimerh,lwritetimerl,
|
||||
lwritetimerh, timeracc, timerlatch, timercount)
|
||||
begin
|
||||
if rising_edge(clkmed) then
|
||||
if lwritetimerl = '1' then
|
||||
timerdiv(7 downto 0) <= mobus;
|
||||
end if;
|
||||
if lwritetimerh = '1' then
|
||||
timerdiv(15 downto 8) <= mobus;
|
||||
end if;
|
||||
timeracc <= timeracc -1;
|
||||
if lreadtimerl = '1' then
|
||||
timerlatch <= timercount(15 downto 8);
|
||||
end if;
|
||||
if timermsb = '1' then
|
||||
timercount <= timercount +1;
|
||||
timeracc <= timerdiv;
|
||||
end if;
|
||||
end if;
|
||||
iodata <= (others => 'Z');
|
||||
if lreadtimerl = '1' then
|
||||
iodata <= timercount(7 downto 0);
|
||||
end if;
|
||||
if lreadtimerh = '1' then
|
||||
iodata <= timerlatch;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
getclock : process (ioradd,lreadclock,baseclockslv)
|
||||
begin
|
||||
baseclockslv <= conv_std_logic_vector(BaseClock,32);
|
||||
iodata <= (others => 'Z');
|
||||
if lreadclock = '1' then
|
||||
case ioradd(1 downto 0) is
|
||||
when "00" => iodata <= baseclockslv(7 downto 0);
|
||||
when "01" => iodata <= baseclockslv(15 downto 8);
|
||||
when "10" => iodata <= baseclockslv(23 downto 16);
|
||||
when "11" => iodata <= baseclockslv(31 downto 24);
|
||||
when others => null;
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
getchannels : process (ioradd,lreadchannels)
|
||||
begin
|
||||
iodata <= (others => 'Z');
|
||||
if lreadchannels = '1' then
|
||||
iodata <= conv_std_logic_vector(Ports,8);
|
||||
end if;
|
||||
end process;
|
||||
|
||||
acrc8 : if NeedCRC8 generate
|
||||
crc8 : process (clkmed,newxor,lreadcrc) -- note Maxim or DOW CRC8 poly = x8,x5,x4,x1
|
||||
variable crc: std_logic_vector(7 downto 0);
|
||||
begin
|
||||
crc := x"00";
|
||||
for i in 0 to 7 loop
|
||||
if newxor(i) = '1' then
|
||||
case i is
|
||||
when 0 => crc := crc xor x"5E"; -- crc of 1
|
||||
when 1 => crc := crc xor x"BC"; -- crc of 2
|
||||
when 2 => crc := crc xor x"61"; -- crc of 4
|
||||
when 3 => crc := crc xor x"C2"; -- crc of 8
|
||||
when 4 => crc := crc xor x"9D"; -- crc of 16
|
||||
when 5 => crc := crc xor x"23"; -- crc of 32
|
||||
when 6 => crc := crc xor x"46"; -- crc of 64
|
||||
when 7 => crc := crc xor x"8C"; -- crc of 128
|
||||
end case;
|
||||
else
|
||||
crc := crc;
|
||||
end if;
|
||||
end loop;
|
||||
if rising_edge(clkmed) then
|
||||
if lwritecrc = '1' then
|
||||
newxor <= crc xor mobus;
|
||||
end if;
|
||||
if lclearcrc = '1' then
|
||||
newxor <= x"00";
|
||||
end if;
|
||||
end if;
|
||||
iodata <= (others => 'Z');
|
||||
if lreadcrc = '1' then
|
||||
iodata <= crc;
|
||||
end if;
|
||||
end process;
|
||||
end generate;
|
||||
|
||||
|
||||
LocalDecode: process (mwadd,mradd,ioradd,mread,mwrite,readrxdatasel,loadtxdatasel,
|
||||
loadrxbitratelsel,loadrxbitratemsel,loadrxbitratehsel,
|
||||
clearrxfifosel,readrxfifocountsel,readrxmodesel,loadrxmodesel,
|
||||
loadtxbitratelsel,loadtxbitratemsel,loadtxbitratehsel,loadrxfiltersel,
|
||||
cleartxfifosel,readtxfifocountsel,loadtxmodesel,readtxmodesel)
|
||||
begin
|
||||
writedram <= (not mwadd(9)) and mwrite;
|
||||
|
||||
lloadcommand <= decodedstrobe(mwadd,x"200",mwrite);
|
||||
lreadcommandl <= decodedstrobe(ioradd,x"200",mread);
|
||||
lreadcommandh <= decodedstrobe(ioradd,x"201",mread);
|
||||
lloaddata <= decodedstrobe(mwadd,x"202",mwrite);
|
||||
lreaddata <= decodedstrobe(ioradd,x"202",mread);
|
||||
lclrhdoorbell <= decodedstrobe(mwadd,x"203",mwrite);
|
||||
lreadhdoorbell <= decodedstrobe(ioradd,x"203",mread);
|
||||
|
||||
lsettestbit <= decodedstrobe(mwadd,x"220",mwrite);
|
||||
lclrtestbit <= decodedstrobe(mwadd,x"221",mwrite);
|
||||
|
||||
lreadtimerl <= decodedstrobe(ioradd,x"222",mread);
|
||||
lreadtimerh <= decodedstrobe(ioradd,x"223",mread);
|
||||
lwritetimerl <= decodedstrobe(mwadd,x"222",mwrite);
|
||||
lwritetimerh <= decodedstrobe(mwadd,x"223",mwrite);
|
||||
|
||||
lreadcrc <= decodedstrobe(ioradd,x"224",mread);
|
||||
lwritecrc <= decodedstrobe(mwadd,x"224",mwrite);
|
||||
lclearcrc <= decodedstrobe(mwadd,x"225",mwrite);
|
||||
|
||||
lreadclock <= decodedstrobe(ioradd(11 downto 2),"0010001100",mread); -- 0x430..0x433
|
||||
lreadchannels <= decodedstrobe(ioradd,x"234",mread);
|
||||
|
||||
lwriteiram <= decodedstrobe(mwadd(11 downto 8),x"3",mwrite); -- 256 bytes max, 32 per reg
|
||||
lreadiram <= decodedstrobe(ioradd(11 downto 8),x"3",mread);
|
||||
|
||||
-- readdoorbell <= decodedstrobe(ioradd(11 downto 6),"011100",mread); -- 0x700 -- 0x7BF
|
||||
-- cleardoorbell <= decodedstrobe( mwadd(11 downto 6),"011100",mwrite); -- 64 bytes max
|
||||
|
||||
|
||||
|
||||
-- UART decodes
|
||||
-- RX
|
||||
loadrxfiltersel <= decodedstrobe(mwadd(11 downto 4),x"27",mwrite);
|
||||
readrxdatasel <= decodedstrobe(ioradd(11 downto 4),x"28",mread);
|
||||
loadrxbitratelsel <= decodedstrobe(mwadd(11 downto 4),x"29",mwrite);
|
||||
loadrxbitratemsel <= decodedstrobe(mwadd(11 downto 4),x"2A",mwrite);
|
||||
loadrxbitratehsel <= decodedstrobe(mwadd(11 downto 4),x"2B",mwrite);
|
||||
clearrxfifosel <= decodedstrobe(mwadd(11 downto 4),x"2C",mwrite);
|
||||
readrxfifocountsel <= decodedstrobe(ioradd(11 downto 4),x"2C",mread);
|
||||
readrxmodesel <= decodedstrobe(ioradd(11 downto 4),x"2D",mread);
|
||||
loadrxmodesel <= decodedstrobe(mwadd(11 downto 4),x"2D",mwrite);
|
||||
|
||||
loadrxfilter <= OneOfNDecode(Ports,loadrxfiltersel,mwrite,mwadd(log2(Ports)-1 downto 0));
|
||||
readrxdata <= OneOfNDecode(Ports,readrxdatasel,mread,ioradd(log2(Ports)-1 downto 0));
|
||||
loadrxbitratel <= OneOfNDecode(Ports,loadrxbitratelsel,mwrite,mwadd(log2(Ports)-1 downto 0));
|
||||
loadrxbitratem <= OneOfNDecode(Ports,loadrxbitratemsel,mwrite,mwadd(log2(Ports)-1 downto 0));
|
||||
loadrxbitrateh <= OneOfNDecode(Ports,loadrxbitratehsel,mwrite,mwadd(log2(Ports)-1 downto 0));
|
||||
clearrxfifo <= OneOfNDecode(Ports,clearrxfifosel,mwrite,mwadd(log2(Ports)-1 downto 0));
|
||||
readrxfifocount <= OneOfNDecode(Ports,readrxfifocountsel,mread,ioradd(log2(Ports)-1 downto 0));
|
||||
readrxmode <= OneOfNDecode(Ports,readrxmodesel,mread,ioradd(log2(Ports)-1 downto 0));
|
||||
loadrxmode <= OneOfNDecode(Ports,loadrxmodesel,mwrite,mwadd(log2(Ports)-1 downto 0));
|
||||
|
||||
-- UART decodes
|
||||
-- TX
|
||||
loadtxdatasel <= decodedstrobe(mwadd(11 downto 4),x"28",mwrite);
|
||||
loadtxbitratelsel <= decodedstrobe(mwadd(11 downto 4),x"29",mwrite); -- note on top of read baud rate select
|
||||
loadtxbitratemsel <= decodedstrobe(mwadd(11 downto 4),x"2A",mwrite);
|
||||
loadtxbitratehsel <= decodedstrobe(mwadd(11 downto 4),x"2B",mwrite);
|
||||
-- readtxbitratelsel <= decodedstrobe(ioradd(11 downto 4),x"29",mread); -- note on top of read baud rate select
|
||||
-- readtxbitratemsel <= decodedstrobe(ioradd(11 downto 4),x"2A",mread); -- note on top of read baud rate select
|
||||
-- readtxbitratehsel <= decodedstrobe(ioradd(11 downto 4),x"2B",mread);
|
||||
cleartxfifosel <= decodedstrobe(mwadd(11 downto 4),x"2E",mwrite);
|
||||
readtxfifocountsel <= decodedstrobe(ioradd(11 downto 4),x"2E",mread);
|
||||
readtxmodesel <= decodedstrobe(ioradd(11 downto 4),x"2F",mread);
|
||||
loadtxmodesel <= decodedstrobe(mwadd(11 downto 4),x"2F",mwrite);
|
||||
|
||||
loadtxdata <= OneOfNDecode(Ports,loadtxdatasel,mwrite,mwadd(log2(Ports)-1 downto 0));
|
||||
loadtxbitratel <= OneOfNDecode(Ports,loadtxbitratelsel,mwrite,mwadd(log2(Ports)-1 downto 0));
|
||||
loadtxbitratem <= OneOfNDecode(Ports,loadtxbitratemsel,mwrite,mwadd(log2(Ports)-1 downto 0));
|
||||
loadtxbitrateh <= OneOfNDecode(Ports,loadtxbitratehsel,mwrite,mwadd(log2(Ports)-1 downto 0));
|
||||
-- readtxbitratel <= OneOfNDecode(Ports,readtxbitratelsel,mread,ioradd(log2(Ports)-1 downto 0));
|
||||
-- readtxbitratem <= OneOfNDecode(Ports,readtxbitratemsel,mread,ioradd(log2(Ports)-1 downto 0));
|
||||
-- readtxbitrateh <= OneOfNDecode(Ports,readtxbitratehsel,mread,ioradd(log2(Ports)-1 downto 0));
|
||||
cleartxfifo <= OneOfNDecode(Ports,cleartxfifosel,mwrite,mwadd(log2(Ports)-1 downto 0));
|
||||
readtxfifocount <= OneOfNDecode(Ports,readtxfifocountsel,mread,ioradd(log2(Ports)-1 downto 0));
|
||||
loadtxmode <= OneOfNDecode(Ports,loadtxmodesel,mwrite,mwadd(log2(Ports)-1 downto 0));
|
||||
readtxmode <= OneOfNDecode(Ports,readtxmodesel,mread,ioradd(log2(Ports)-1 downto 0));
|
||||
end process localdecode;
|
||||
|
||||
looseends: process (drven,txdata,rxserial)
|
||||
begin
|
||||
txenable <= drven;
|
||||
ntxenable <= not drven;
|
||||
-- txenable(Ports-1) <= hdoorbell; -- test kludge to check host command --> serial interface jitter
|
||||
txserial <= txdata;
|
||||
rxdata <= rxserial;
|
||||
end process looseends;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
Reference in New Issue
Block a user