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Thaddeus-Maximus
250
5i24/configs/hostmot2/source/simplessi.vhd
Executable file
250
5i24/configs/hostmot2/source/simplessi.vhd
Executable file
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.math_real.all;
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use ieee.numeric_std.all;
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--
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-- Copyright (C) 2009, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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-- added 200 ns digital filter to SSI data 7/6/18
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-- should skew clock to compensate, next time...
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entity SimpleSSI is
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generic (
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Clock : integer
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);
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Port ( clk : in std_logic;
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ibus : in std_logic_vector(31 downto 0);
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obus : out std_logic_vector(31 downto 0);
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loadcontrol : in std_logic;
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lstart : in std_logic;
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pstart : in std_logic;
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timers : in std_logic_vector(4 downto 0);
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readdata0 : in std_logic;
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readdata1 : in std_logic;
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readcontrol : in std_logic;
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busyout : out std_logic;
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davout : out std_logic;
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ssiclk : out std_logic;
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ssidata : in std_logic
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);
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end SimpleSSI;
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architecture Behavioral of SimpleSSI is
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signal BitrateDDSReg : std_logic_vector(15 downto 0);
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signal BitrateDDSAccum : std_logic_vector(15 downto 0);
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alias DDSMSB : std_logic is BitrateDDSAccum(15);
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signal OldDDSMSB: std_logic;
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signal BitcountReg : std_logic_vector(6 downto 0);
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signal BitCount : std_logic_vector(6 downto 0);
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signal SkewReg : std_logic_vector(3 downto 0);
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signal SSISreg: std_logic_vector(63 downto 0);
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signal SSILatch: std_logic_vector(63 downto 0);
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signal Go: std_logic;
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signal Start: std_logic;
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signal BitZero: std_logic;
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signal OldBitZero: std_logic;
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signal PStartmask: std_logic;
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signal TStartmask: std_logic;
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signal TimerSelect: std_logic_vector(2 downto 0);
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signal Timer: std_logic;
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signal OldTimer: std_logic;
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signal TStart: std_logic;
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signal MaskFirst: std_logic;
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signal SampleTime: std_logic;
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signal DAV: std_logic;
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constant defaultfilter : real := round((real(Clock)/5000000.0)); --default filter TC is 200 ns
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signal FilterReg: std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(integer(defaultfilter),8));
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signal FilterCount: std_logic_vector(7 downto 0);
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signal SSIDataD: std_logic;
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signal FiltSSIData: std_logic;
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begin
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assiinterface: process (clk,go,lstart,pstartmask,tstartmask,bitcountreg,
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readdata0,readdata1,ssilatch,readcontrol,Timer,Timers,
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OldTimer,TimerSelect,TStart,PStart,OldDDSMSB,
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BitRateDDSAccum,DAv,BitRateDDSReg)
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begin
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if clk'event and clk = '1' then
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SSIDataD <= ssidata;
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if (SSIDataD = '1') and (FilterCount < FilterReg) then -- simple digital filter on rxdata
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FilterCount <= FilterCount + 1;
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end if;
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if (SSIDataD = '0') and (FilterCount /= 0) then
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FilterCount <= FilterCount -1;
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end if;
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if FilterCount >= FilterReg then
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FiltSSIData<= '1';
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end if;
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if FilterCount = 0 then
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FiltSSIData<= '0';
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end if;
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if Start = '1' then
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BitCount <= BitCountReg;
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Go <= '1';
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SSISreg <= (Others => '0');
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MaskFirst <= '0';
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BitZero <= '0';
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end if;
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if Go = '1' then
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BitRateDDSAccum <= BitRateDDSAccum + BitRateDDSReg;
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else
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BitRateDDSAccum <= (others => '0');
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end if;
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if SampleTime = '1' then
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if MaskFirst = '1' then
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SSISreg <= SSISreg(62 downto 0) & FiltSSIData;
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end if;
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if BitCount /= "0000000" then
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BitCount <= BitCount -1;
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MaskFirst <= '1'; -- first clock just latches data so dont shift in
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end if;
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if BitCount = "0000001" then
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BitZero <= '1'; -- at bit count of zero, (delayed count of 1);
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else
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BitZero <= '0';
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end if;
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end if;
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if BitZero = '0' and OldBitZero = '1' then
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Go <= '0';
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DAV <= '1';
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SSILatch <= SSISReg;
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end if;
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OldDDSMSB <= DDSMSB;
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OldBitZero <= BitZero;
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if loadcontrol = '1' then
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BitCountReg <= ibus(6 downto 0);
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PStartMask <= ibus(8);
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TStartMask <= ibus(9);
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TimerSelect <= ibus(14 downto 12);
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BitRateDDSReg <= ibus(31 downto 16);
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end if;
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OldTimer <= Timer;
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if readdata0 = '1' then
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DAV <= '0';
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end if;
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end if; -- clk
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if Timer = '1' and OldTimer = '0' then -- rising edge of selected timer
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TStart <= '1';
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else
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TStart <= '0';
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end if;
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case TimerSelect is
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when "000" => Timer <= timers(0);
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when "001" => Timer <= timers(1);
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when "010" => Timer <= timers(2);
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when "011" => Timer <= timers(3);
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when "100" => Timer <= timers(4);
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when others => Timer <= Timers(0);
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end case;
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if lstart = '1' or (TStart = '1' and TStartMask = '1') or (pstart = '1' and PStartMask = '1')then
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Start <= '1';
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else
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Start <= '0';
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end if;
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SampleTime <= OldDDSMSB and not DDSMSB;
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obus <= (others => 'Z');
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if readdata0 = '1' then
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obus <= SSILatch(31 downto 0);
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end if;
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if readdata1 = '1' then
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obus <= SSILatch(63 downto 32);
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end if;
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if readcontrol = '1' then
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obus(6 downto 0) <= BitCountReg;
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obus(7) <= '0';
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obus(8) <= PStartMask;
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obus(9) <= TStartMask;
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obus(10) <= '0';
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obus(11) <= Go;
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obus(14 downto 12) <= TimerSelect;
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obus(15) <= DAV;
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obus(31 downto 16) <= BitRateDDSReg;
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end if;
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ssiclk <= not DDSMSB; -- hold time is guaranteed by two directional propagation delay
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busyout <= Go or (not DAV);
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davout <= DAV;
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end process assiinterface;
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end Behavioral;
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