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Thaddeus-Maximus
300
5i24/configs/hostmot2/source/resolverdaq2.vhd
Executable file
300
5i24/configs/hostmot2/source/resolverdaq2.vhd
Executable file
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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entity resolverdaq2 is -- specific SPI DAQ subsystem for AD7265 type A-D chips for resolver input
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port (
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clk : in std_logic;
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ibus : in std_logic_vector(31 downto 0);
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obus : out std_logic_vector(31 downto 0);
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hostaddr : in std_logic_vector(9 downto 0);
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ioradd0: in std_logic;
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readram : in std_logic;
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loadmode : in std_logic;
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-- readmode : in std_logic;
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clear : in std_logic;
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readstat: in std_logic;
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startburst: in std_logic;
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spiclk : out std_logic;
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spiin0 : in std_logic;
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spiin1 : in std_logic;
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spiframe: out std_logic;
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channelsel0: out std_logic;
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channelsel1: out std_logic;
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channelsel2: out std_logic;
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testout: out std_logic
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);
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end resolverdaq2;
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architecture behavioral of resolverdaq2 is
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constant DivWidth: integer := 4;
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-- spi interface related signals
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signal RateDiv : std_logic_vector(DivWidth -1 downto 0);
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signal ModeReg : std_logic_vector(31 downto 0);
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alias BitcountReg : std_logic_vector(4 downto 0) is ModeReg(4 downto 0); -- bits are N+1
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alias SwapMem : std_logic is ModeReg(5);
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alias CPOL : std_logic is ModeReg(6);
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alias CPHA : std_logic is ModeReg(7);
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alias RateDivReg : std_logic_vector(DivWidth -1 downto 0) is ModeReg(11 downto 8); -- sets SPI shift clock rate CLK/(2*(N+1))
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alias BurstDivReg : std_logic_vector(11 downto 0) is ModeReg(23 downto 12); -- sets A-D conversion rate during burst CLK/(N+2);
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alias BurstCountReg : std_logic_vector(7 downto 0) is ModeReg(31 downto 24); -- sets length of A-D burst (N+2)
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signal fixaddr0 : std_logic;
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signal burstcount: std_logic_vector(7 downto 0);
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signal burstdiv: std_logic_vector(11 downto 0);
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alias burstcountmsb : std_logic is burstcount(7);
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signal oldburstcountmsb: std_logic;
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alias burstdivmsb : std_logic is burstdiv(11);
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signal BitCount : std_logic_vector(4 downto 0);
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alias BitCountMSB : std_logic is BitCount(4);
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signal ClockFF: std_logic;
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signal SPISReg0: std_logic_vector(15 downto 0);
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signal SPISReg1: std_logic_vector(15 downto 0);
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signal LFrame: std_logic := '0';
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signal Dav: std_logic;
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signal SPIIn0Latch: std_logic;
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signal SPIIn1Latch: std_logic;
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signal FirstLeadingEdge: std_logic;
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signal Channel: std_logic_vector(2 downto 0);
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signal BufferHalf: std_logic;
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signal startconv: std_logic;
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signal daqreset: std_logic;
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signal DHostAddr: std_logic;
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signal oldstartburst: std_logic;
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signal muxtime: std_logic;
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signal oldmuxtime: std_logic;
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-- daqram related signals
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signal daqaddr: std_logic_vector(8 downto 0);
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signal daqdata: std_logic_vector(31 downto 0);
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signal hostdata: std_logic_vector(31 downto 0);
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begin
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-- dual ported 512 x 32
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adaqram : entity work.dpram
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generic map(
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width => 32,
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depth => 512
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)
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port map(
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addra => daqaddr,
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addrb => hostaddr(9 downto 1), -- read by host as 1024 16 bit values
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clk => clk, -- sign extended to 32 bits
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dina => daqdata,
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doutb => hostdata,
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wea => Dav
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);
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aresolverdaq2: process (clk,SPISReg1, SPISReg0, Channel, ClockFF,
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ModeReg, LFrame, readram, hostaddr, hostdata,
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BitCount, ioradd0, readstat, daqaddr)
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begin
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if rising_edge(clk) then
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if loadmode = '1' then
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modereg <= ibus;
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end if;
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if startconv = '1' then
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BitCount <= BitCountReg;
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LFrame <= '1';
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ClockFF <= '0';
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FirstLeadingEdge <= '1';
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RateDiv <= RateDivReg;
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startconv <= '0';
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end if;
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if Dav = '1' then -- increment daq address as we write new data
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Dav <= '0';
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daqaddr <= daqaddr +1;
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end if;
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if muxtime = '1' and oldmuxtime = '0' then -- mux at start of spi cycle for maximum settling time
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channel <= channel +1;
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if channel = 5 then -- hardwired for AD7265, 6 channels single ended mode
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channel <= "000";
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if burstcountmsb = '0' then
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burstcount <= burstcount -1;
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end if;
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end if;
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end if;
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if burstcountmsb = '1' and oldburstcountmsb = '0' then -- set ptr reset request at end of burst
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daqreset <= '1';
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end if;
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if startburst = '1' and oldstartburst = '0' then
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burstcount <= burstcountreg;
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end if;
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if burstcountmsb = '0' then -- if burst running
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burstdiv <= burstdiv -1;
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if burstdivmsb = '1' then
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burstdiv <= BurstDivReg;
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startconv <= '1';
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end if;
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end if;
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if dav = '1' and daqreset = '1' then
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if bufferhalf = '0' then
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daqaddr <= (others => '0');
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else
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daqaddr <= "100000000";
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end if;
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bufferhalf <= not bufferhalf;
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daqreset <= '0';
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end if;
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if LFrame = '1' then -- single shift register SPI
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if RateDiv = 0 then -- maybe update to dual later to allow
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RateDiv <= RateDivReg; -- receive data skew adjustment
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SPIIn0Latch <= spiin0;
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SPIIn1Latch <= spiin1;
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if ClockFF = '0' then
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if BitCountMSB = '1' then
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LFrame <= '0'; -- LFrame cleared 1/2 SPI clock after GO
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Dav <= '1'; -- we're done!
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else
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ClockFF <= '1';
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end if;
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if CPHA = '1' and FirstLeadingEdge = '0' then -- shift out on leading edge for CPHA = 1 case
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SPISreg0 <= SPISreg0(14 downto 0) & (SPIIn0Latch); -- left shift
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SPISreg1 <= SPISreg1(14 downto 0) & (SPIIn1Latch);
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end if;
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FirstLeadingEdge <= '0';
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else -- clockff is '1'
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ClockFF <= '0';
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BitCount <= BitCount -1;
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if CPHA = '0' then -- shift out on trailing edge for CPHA = 0 case
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SPISreg0 <= SPISreg0(14 downto 0) & (SPIIn0Latch); -- left shift
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SPISreg1 <= SPISreg1(14 downto 0) & (SPIIn1Latch);
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end if;
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end if;
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else -- ratediv not 0
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RateDiv <= RateDiv -1;
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end if;
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end if; -- LFrame = 1
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if clear = '1' then
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LFrame <= '0';
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ClockFF <= '0';
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Dav <= '0';
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daqaddr <= (others => '0');
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channel <= (others => '0');
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end if;
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oldstartburst <= startburst;
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oldmuxtime <= muxtime;
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oldburstcountmsb <= burstcountmsb;
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end if; -- clk
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if bitcount(3 downto 0) = x"A" then -- change mux 3 clocks into conversion
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muxtime <= '1';
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else
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muxtime <= '0';
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end if;
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daqdata(31 downto 16) <= SPISReg1;
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daqdata(15 downto 0) <= SPISReg0;
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channelsel0 <= channel(0);
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channelsel1 <= channel(1);
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channelsel2 <= channel(2);
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spiclk <= ClockFF xor CPOL;
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spiframe <= not LFrame;
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fixaddr0 <= ioradd0 xor SwapMem; -- swap sin/cos of output data for step response
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obus <= (others => 'Z');
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if readram = '1' then
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-- all this mungeology is to take the signed 12 bit A-D data
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-- and present it to the processor as 12 bit number sign extended to 32 bits
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-- it may get removed if there's enough time at 10 KHz sample frequency
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if fixaddr0 = '0' then
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obus(11 downto 0) <= hostdata(11 downto 0); -- for 7265/66
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else
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obus(11 downto 0) <= hostdata(27 downto 16);
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end if;
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if (hostdata(11) = '0' and fixaddr0 = '0') or (hostdata(27) = '0' and fixaddr0 = '1') then -- sign extend to 32 bits
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obus(31 downto 12) <= (others => '0');
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end if;
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if (hostdata(11) = '1' and fixaddr0 = '0') or (hostdata(27) = '1' and fixaddr0 = '1') then
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obus(31 downto 12) <= (others => '1');
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end if;
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end if;
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if readstat = '1' then
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obus(8 downto 0) <= daqaddr;
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end if;
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testout <= bitcount(2);
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end process aresolverdaq2;
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end Behavioral;
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