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This commit is contained in:
Thaddeus-Maximus
419
5i24/configs/hostmot2/source/pktuartx16.vhd
Executable file
419
5i24/configs/hostmot2/source/pktuartx16.vhd
Executable file
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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use work.log2.all;
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entity pktuartx16 is
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generic (MaxFrameSize: integer ); -- in bytes (-1) maximum is 2K bytes
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Port (clk : in std_logic;
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ibus : in std_logic_vector(15 downto 0);
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obus : out std_logic_vector(15 downto 0);
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pushdata : in std_logic;
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pushsc: in std_logic;
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readsc: in std_logic;
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loadbitratel : in std_logic;
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readbitratel : in std_logic;
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loadbitrateh : in std_logic;
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readbitrateh : in std_logic;
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loadmodel : in std_logic;
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readmodel : in std_logic;
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loadmodeh : in std_logic;
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readmodeh : in std_logic;
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drven : out std_logic;
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txdata : out std_logic
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);
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end pktuartx16;
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architecture Behavioral of pktuartx16 is
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-- buffer related signals
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signal InAdd: std_logic_vector(log2(MaxFrameSize) -2 downto 0);
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signal OutAdd: std_logic_vector(log2(MaxFrameSize) -2 downto 0);
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signal OutData: std_logic_vector(15 downto 0);
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signal ReadData: std_logic;
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signal FrameBufferEmpty: std_logic;
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-- frame FIFO related signals
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signal PopSC: std_logic;
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signal SFrameCount: std_logic_vector(4 downto 0);
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signal SCPopAdd: std_logic_vector(3 downto 0);
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signal SCFIFOError: std_logic;
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signal SCFIFOEmpty : std_logic;
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signal SCPopData: std_logic_vector(log2(maxFrameSize)-1 downto 0);
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-- uart interface related signals
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constant DDSWidth : integer := 20;
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signal BitrateDDSReg : std_logic_vector(DDSWidth-1 downto 0);
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signal BitrateDDSAccum : std_logic_vector(DDSWidth-1 downto 0);
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alias DDSMSB : std_logic is BitrateDDSAccum(DDSWidth-1);
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signal OldDDSMSB: std_logic;
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signal SampleTime: std_logic;
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signal DelayTime: std_logic;
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signal BitCount : std_logic_vector(3 downto 0);
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signal BytePointer : std_logic := '0';
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signal SReg: std_logic_vector(10 downto 0);
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signal SendData: std_logic_vector(7 downto 0);
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signal SendCount: std_logic_vector(log2(MaxFrameSize)-1 downto 0);
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signal Clear: std_logic;
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alias SregData: std_logic_vector(7 downto 0)is SReg(9 downto 2);
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alias StartBit: std_logic is Sreg(1);
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alias StopBit: std_logic is Sreg(10);
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alias IdleBit: std_logic is Sreg(0);
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signal Go: std_logic := '0';
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signal FDGo: std_logic := '0';
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signal SCNZ: std_logic := '0';
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signal ModeReg: std_logic_vector(15 downto 0);
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alias FrameDelay: std_logic_vector(7 downto 0) is ModeReg(15 downto 8);
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signal FrameDelayCount: std_logic_vector(7 downto 0);
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alias DriveEnDelay: std_logic_vector(3 downto 0) is ModeReg(3 downto 0);
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signal DriveDelayCount: std_logic_vector(3 downto 0);
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alias DriveEnAuto: std_logic is ModeReg(5);
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alias DriveEnBit: std_logic is ModeReg(6);
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signal DriveEnable: std_logic;
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signal DriveEnHold: std_logic;
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signal WaitingForDrive: std_logic;
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signal Busy: std_logic;
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component SRL16E
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--
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generic (INIT : bit_vector);
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--
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port (D : in std_logic;
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CE : in std_logic;
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CLK : in std_logic;
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A0 : in std_logic;
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A1 : in std_logic;
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A2 : in std_logic;
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A3 : in std_logic;
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Q : out std_logic);
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end component;
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begin
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buffram : entity work.dpram
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generic map (
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width => 16,
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depth => MaxFrameSize/2
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)
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port map(
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addra => InAdd,
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addrb => OutAdd,
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clk => clk,
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dina => ibus,
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-- douta =>
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doutb => OutData,
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wea => pushdata
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);
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abuf: process (clk,InAdd,OutAdd)
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begin
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if rising_edge(clk) then
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if pushdata = '1' then
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InAdd <= InAdd+1;
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end if;
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if ReadData = '1' then
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OutAdd <= OutAdd +1;
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end if;
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if Clear = '1' then
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InAdd <= (others => '0');
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OutAdd <= (others => '0');
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end if;
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end if; -- clk
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if InAdd = OutAdd then
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FrameBufferEmpty <= '1';
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else
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FrameBufferEmpty <= '0';
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end if;
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end process abuf;
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fifosrl: for i in 0 to log2(MaxFrameSize)-1 generate
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asr16e: SRL16E generic map (x"0000") port map(
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D => ibus(i),
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CE => pushsc,
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CLK => clk,
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A0 => SCPopAdd(0),
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A1 => SCPopAdd(1),
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A2 => SCPopAdd(2),
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A3 => SCPopAdd(3),
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Q => SCPopData(i)
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);
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end generate;
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ascfifo: process (clk,SCPopData,SFrameCount) -- send counter fifo
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begin
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if rising_edge(clk) then
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if pushsc = '1' and PopSC = '0' then
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if SFrameCount /= 16 then -- a push
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-- always increment the data counter if not full
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SFrameCount <= SFrameCount +1;
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SCPopAdd <= SCPopAdd +1; -- popadd must follow data down shiftreg
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else
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SCFIFOError <= '1';
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end if;
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end if;
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if (PopSC = '1') and (pushsc = '0') and (SCFIFOEmpty = '0') then -- a pop
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-- always decrement the data counter if not empty
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SFrameCount <= SFrameCount -1;
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SCPopAdd <= SCPopAdd -1;
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end if;
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-- if both push and pop are asserted we dont change either counter
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if Clear = '1' then -- a Clear fifo
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SCPopadd <= (others => '1');
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SFrameCount <= (others => '0');
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SCFIFOError <= '0';
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end if;
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end if; -- clk rise
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if SFrameCount = 0 then
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SCFIFOEmpty <= '1';
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else
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SCFIFOEmpty <= '0';
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end if;
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end process ascfifo;
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asimplepktuarttx: process (clk,loadmodel,loadmodeh,OldDDSMSB,BitRateDDSAccum,DriveDelayCount,
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DriveEnable,ModeReg,Go,BytePointer,OutData,readbitratel, readbitrateh,
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readmodel,readmodeh,ibus,BitRateDDSReg,FDGo,WaitingForDrive,SReg,Busy,
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SCNZ,SFrameCount,SendCount,SCFIFOError,SCFIFOEmpty,ReadSC,FrameBufferEmpty)
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begin
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if rising_edge(clk) then
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if Go = '1' or FDGo = '1' then
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BitRateDDSAccum <= BitRateDDSAccum - BitRateDDSReg;
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if FDGo = '0' then
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if SampleTime = '1' then
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SReg <= '1' & SReg(10 downto 1); -- right shift = LSb first
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BitCount <= BitCount -1;
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if BitCount = 0 then
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Go <= '0';
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end if;
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end if;
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end if;
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if FDGO = '1' then -- frame delay
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if DelayTime = '1' then
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FrameDelayCount <= FrameDelayCount -1;
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if FrameDelayCount = x"01" then
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FDGo <= '0';
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end if;
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end if;
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end if;
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else
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BitRateDDSAccum <= (others => '0');
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end if;
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if Go = '0' and FDGo = '0' then -- prepare to send
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StartBit <= '0';
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StopBit <= '1';
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IdleBit <= '1';
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BitCount <= "1010";
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if SendCount /= 0 and DriveEnHold = '0' then -- start byte send -- UART SReg not busy and we have data
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SRegData <= SendData;
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Go <= '1';
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BytePointer <= not BytePointer;
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SendCount <= SendCount -1;
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if BytePointer = '1' then
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ReadData <= '1'; -- advance read data pointer
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end if;
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SCNZ <= '1';
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else -- SendCount = 0
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if SCFIFOEmpty = '0' then -- more frames to send
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SendCount <= SCPopData;
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PopSC <= '1';
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end if;
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if SCNZ = '1' then -- just at end of frame
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if BytePointer /= '0' then -- discard partial data
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BytePointer <= '0';
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ReadData <= '1';
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end if;
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FDGo <= '1';
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FrameDelayCount <= FrameDelay;
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SCNZ <= '0';
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end if;
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end if;
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end if;
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if Clear = '1' then
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SendCount <= (others => '0');
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BytePointer <= '0';
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Go <= '0';
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FDGo <='0';
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SCNZ <='0';
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end if;
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if ReadData = '1' then
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ReadData <= '0';
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end if;
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if PopSC = '1' then
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PopSC <= '0';
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end if;
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if DriveEnable = '0' then
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DriveDelayCount <= DriveEnDelay;
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else
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if WaitingForDrive = '1' then
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DriveDelayCount <= DriveDelayCount -1;
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end if;
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end if;
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OldDDSMSB <= DDSMSB;
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if loadbitratel = '1' then
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BitRateDDSReg(15 downto 0) <= ibus;
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end if;
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if loadbitrateh = '1' then
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BitRateDDSReg(DDSWidth-1 downto 16) <= ibus(DDSWidth-17 downto 0);
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end if;
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if loadmodel = '1' then
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ModeReg <= ibus(15 downto 0);
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end if;
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end if; -- clk
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if loadmodeh = '1' and ibus(0) = '1' then
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Clear <= '1';
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else
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Clear <= '0';
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end if;
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SampleTime <= (not OldDDSMSB) and DDSMSB;
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DelayTime <= OldDDSMSB and (not DDSMSB);
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if DriveDelayCount /= 0 then
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WaitingForDrive <= '1';
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else
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WaitingForDrive <= '0';
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end if;
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DriveEnHold <= (not DriveEnable) or WaitingForDrive;
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if DriveEnAuto = '1' then
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DriveEnable <= (Go or FDGo or SCNZ or (not SCFIFOEmpty)); -- when there is data to xmit
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else
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DriveEnable <= DriveEnBit;
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end if;
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case BytePointer is
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when '0' => SendData <= OutData(7 downto 0);
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when '1' => SendData <= OutData(15 downto 8);
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when others => null;
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end case;
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Busy <= Go or FDGo or (not SCFIFOEmpty) or SCNZ;
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obus <= (others => 'Z');
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if readsc = '1' then
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obus(log2(MaxFrameSize)-1 downto 0) <=SendCount;
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obus(15 downto log2(MaxFrameSize)) <= (others => '0');
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end if;
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if readbitratel = '1' then
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obus <= BitRateDDSReg(15 downto 0);
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end if;
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if readbitrateh = '1' then
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obus(DDSWidth-17 downto 0) <= BitRateDDSReg(DDSWidth-1 downto 16);
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obus(15 downto DDSWidth-16) <= (others => '0');
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end if;
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if readmodel = '1' then
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obus(3 downto 0) <= ModeReg(3 downto 0);
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obus(4) <= SCFIFOError;
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obus(6 downto 5) <= ModeReg(6 downto 5);
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obus(7) <= Busy;
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obus(15 downto 8) <= ModeReg(15 downto 8);
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end if;
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if readmodeh = '1' then
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obus(4 downto 0) <= SFrameCount;
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obus(5) <= (not FrameBufferEmpty) and (not Busy);
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obus(15 downto 6) <= (others => '0');
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end if;
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txdata<= SReg(0);
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drven <= DriveEnable;
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end process asimplepktuarttx;
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end Behavioral;
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