?
This commit is contained in:
Thaddeus-Maximus
471
5i24/configs/hostmot2/source/pktuartr8.vhd
Executable file
471
5i24/configs/hostmot2/source/pktuartr8.vhd
Executable file
@@ -0,0 +1,471 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.math_real.all;
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use ieee.numeric_std.all;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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use work.log2.all;
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entity pktuartr8 is
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generic (
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MaxFrameSize: integer; -- in bytes (-1) maximum is 2K bytes
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Clock: integer
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);
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Port (clk : in std_logic;
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ibus : in std_logic_vector(7 downto 0);
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obus : out std_logic_vector(7 downto 0);
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popdata : in std_logic;
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poprc: in std_logic;
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loadbitratel : in std_logic;
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readbitratel : in std_logic;
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loadbitratem : in std_logic;
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readbitratem : in std_logic;
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loadbitrateh : in std_logic;
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readbitrateh : in std_logic;
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loadmodel : in std_logic;
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readmodel : in std_logic;
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loadmodem : in std_logic;
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readmodem : in std_logic;
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loadmodeh : in std_logic;
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readmodeh : in std_logic;
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loadfilter : in std_logic;
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readfilter : in std_logic;
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rxmask : in std_logic;
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rxdata : in std_logic
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);
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end pktuartr8;
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-- digital input filter added 12/15
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architecture Behavioral of pktuartr8 is
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-- buffer related signals
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signal InAdd: std_logic_vector(log2(MaxFrameSize) -1 downto 0);
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signal OutAdd: std_logic_vector(log2(MaxFrameSize) -1 downto 0);
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signal OutData: std_logic_vector(7 downto 0);
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signal PushData: std_logic;
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signal FrameBufferEmpty: std_logic;
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-- frame FIFO related signals
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signal PushRC: std_logic;
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signal RFrameCount: std_logic_vector(4 downto 0) := "00000";
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signal RCPopAdd: std_logic_vector(3 downto 0) := "1111";
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signal RCFIFOEmpty : std_logic;
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signal RCFIFOError: std_logic;
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signal RCPopData: std_logic_vector(log2(maxFrameSize)-1 downto 0);
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signal ErrPopData: std_logic_vector(1 downto 0);
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-- uart interface related signals
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constant DDSWidth : integer := 20;
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constant defaultfilter : real := round((real(Clock)/5000000.0)); --default filter TC is 200 ns
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signal BitrateDDSReg : std_logic_vector(DDSWidth-1 downto 0);
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signal BitrateDDSAccum : std_logic_vector(DDSWidth-1 downto 0);
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alias DDSMSB : std_logic is BitrateDDSAccum(DDSWidth-1);
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signal OldDDSMSB: std_logic;
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signal SampleTime: std_logic;
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signal DelayTime: std_logic;
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signal BitCount : std_logic_vector(3 downto 0);
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signal SReg: std_logic_vector(9 downto 0);
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signal RDataLatch : std_logic_vector(7 downto 0);
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alias SRegData: std_logic_vector(7 downto 0)is SReg(9 downto 2);
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alias StartBit: std_logic is Sreg(0);
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alias StopBit: std_logic is Sreg(9);
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signal RXPipe : std_logic_vector(1 downto 0);
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signal RecvCount: std_logic_vector(log2(MaxFrameSize)-1 downto 0);
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signal Go: std_logic;
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signal FDGo: std_logic;
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signal Clear: std_logic;
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signal ModeReg: std_logic_vector(15 downto 0);
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alias FrameDelay: std_logic_vector(7 downto 0) is ModeReg(15 downto 8);
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signal FrameDelayCount: std_logic_vector(7 downto 0);
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alias FalseStart: std_logic is ModeReg(0);-- started recieve but middle of start bit is '1'
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alias OverRun: std_logic is ModeReg(1); -- '0' where stop bit should be
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alias RXMaskEn: std_logic is ModeReg(2); -- enable TXEN of transmit side to disable receive
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alias RXEnable: std_logic is ModeReg(3); -- RX enable
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signal RXErrs: std_logic_vector(1 downto 0);
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signal ClrRXErrs: std_logic;
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signal ClrRXErrsD: std_logic;
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signal Busy: std_logic;
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signal FilterReg: std_logic_vector(7 downto 0) := std_logic_vector(to_unsigned(integer(defaultfilter),8));
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signal FilterCount: std_logic_vector(7 downto 0);
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signal RXDataD: std_logic;
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signal RXDataFilt: std_logic;
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component SRL16E
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--
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generic (INIT : bit_vector);
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--
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port (D : in std_logic;
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CE : in std_logic;
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CLK : in std_logic;
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A0 : in std_logic;
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A1 : in std_logic;
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A2 : in std_logic;
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A3 : in std_logic;
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Q : out std_logic);
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end component;
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begin
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buffram : entity work.dpram
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generic map (
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width => 8,
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depth => MaxFrameSize
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)
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port map(
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addra => InAdd,
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addrb => OutAdd,
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clk => clk,
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dina => RDataLatch,
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-- douta =>
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doutb => OutData,
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wea => PushData
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);
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abuf: process (clk,InAdd,OutAdd)
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begin
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if rising_edge(clk) then
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if PushData = '1' then
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InAdd <= InAdd+1;
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end if;
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if popdata = '1' then
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OutAdd <= OutAdd +1;
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end if;
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if Clear = '1' then
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InAdd <= (others => '0');
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OutAdd <= (others => '0');
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end if;
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end if; -- clk
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if InAdd = OutAdd then
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FrameBufferEmpty <= '1';
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else
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FrameBufferEmpty <= '0';
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end if;
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end process abuf;
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fiforc: for i in 0 to log2(MaxFrameSize)-1 generate
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asr16e: SRL16E generic map (x"0000") port map(
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D => RecvCount(i),
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CE => PushRC,
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CLK => clk,
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A0 => RCPopAdd(0),
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A1 => RCPopAdd(1),
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A2 => RCPopAdd(2),
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A3 => RCPopAdd(3),
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Q => RCPopData(i)
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);
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end generate;
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fifoerrs: for i in 0 to 1 generate
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asr16e: SRL16E generic map (x"0000") port map(
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D => RXErrs(i),
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CE => PushRC,
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CLK => clk,
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A0 => RCPopAdd(0),
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A1 => RCPopAdd(1),
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A2 => RCPopAdd(2),
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A3 => RCPopAdd(3),
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Q => ErrPopData(i)
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);
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end generate;
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arcfifo: process (clk,RCPopData,RFrameCount) -- recv counter fifo
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begin
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if rising_edge(clk) then
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if PushRC = '1' and poprc = '0' then
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if RFrameCount /= 16 then -- a push
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-- always increment the data counter if not full
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RFrameCount <= RFrameCount +1;
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RCPopAdd <= RCPopAdd +1; -- popadd must follow data down shiftreg
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else
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RCFIFOError <= '1';
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end if;
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end if;
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if (poprc = '1') and (PushRC = '0') then
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if RCFIFOEmpty = '0' then -- a pop
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RFrameCount <= RFrameCount -1;
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RCPopAdd <= RCPopAdd -1;
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else
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RCFIFOError <= '1'; -- pop with no data
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end if;
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end if;
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-- if both push and pop are asserted we dont change either counter
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if Clear = '1' then -- a Clear fifo
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RCPopadd <= (others => '1');
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RFrameCount <= (others => '0');
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RCFIFOError <= '0';
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end if;
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end if; -- clk rise
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if RFrameCount = 0 then
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RCFIFOEmpty <= '1';
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else
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RCFIFOEmpty <= '0';
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end if;
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end process arcfifo;
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asimpleuartrx: process (clk, loadmodel,loadmodeh,OldDDSMSB,BitRateDDSAccum,pushrc,
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OldDDSMSB,FrameDelayCount,poprc,RCPopData,popdata,busy,
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OutData,ErrPopData,readbitratel,readbitrateh,readbitratem,
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BitRateDDSReg,readmodel,readmodem,readmodeh,ModeReg,FrameBufferEmpty,
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RCFIFOError,rxmask,Go,FDGo,ibus,RCFIFOEmpty,RFrameCount,
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readfilter,filterreg)
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begin
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report "Default FilterReg = " & integer'image(integer(defaultfilter));
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if rising_edge(clk) then
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RXDataD <= rxdata;
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RXPipe <= RXPipe(0) & RXDataFilt; -- Two stage rx data pipeline to compensate for
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-- two clock delay from start bit detection to acquire loop startup
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if (RXDataD = '1') and (FilterCount < FilterReg) then -- simple digital filter on rxdata
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FilterCount <= FilterCount + 1;
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end if;
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if (RXDataD = '0') and (FilterCount /= 0) then
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FilterCount <= FilterCount -1;
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end if;
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if FilterCount >= FilterReg then
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RXDataFilt<= '1';
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end if;
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if FilterCount = 0 then
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RXDataFilt<= '0';
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end if;
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-- two clock delay from start bit detection to acquire loop startup
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if Go = '1' or FDGo = '1' then
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BitRateDDSAccum <= BitRateDDSAccum + BitRateDDSReg;
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if Go = '1' then
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if SampleTime = '1' then
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if BitCount = 0 then -- received a char
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Go <= '0';
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if FDGo = '0' then -- first character of a frame
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RecvCount <= conv_std_logic_vector(1,log2(MaxFrameSize));
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else
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RecvCount <= RecvCount + 1;
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end if;
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FDGo <= '1';
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FrameDelayCount <= FrameDelay;
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if RXPipe(1) = '0' then
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OverRun <= '1';
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RXErrs(1) <= '1';
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end if;
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RDataLatch <= SRegData;
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PushData <= '1'; -- write and advance write data pointer every char
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end if; -- bit count = 0
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if BitCount = "1001" then -- false start bit check
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if RXPipe(1) = '1' then
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Go <= '0'; -- abort receive
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FalseStart <= '1';
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RXErrs(0) <= '1';
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end if;
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end if;
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SReg <= RXPipe(1) & SReg(9 downto 1); -- right shift = LSb first
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BitCount <= BitCount -1;
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end if; -- sampletime = 1
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end if;
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if FDGo = '1' then -- framing timeout
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if DelayTime = '1' then
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FrameDelayCount <= FrameDelayCount -1;
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if FrameDelayCount = x"01" then
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FDGo <= '0';
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PushRC <= '1';
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ClrRXErrs <= '1';
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end if;
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end if;
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end if;
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end if; -- Go or FDGo
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if PushData = '1' then
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PushData <= '0';
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end if;
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if PushRC = '1' then
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PushRC <= '0';
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end if;
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if ClrRXErrs = '1' then
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ClrRXErrs <= '0';
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end if;
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ClrRXErrsD <= ClrRXErrs;
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if ClrRXErrsD = '1' then
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RXErrs <= "00";
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end if;
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if Go = '0' then
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BitCount <= "1001";
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if RXDataFilt = '0' and (rxmask and RXMaskEn) = '0' and RXEnable = '1' then
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Go <= '1'; -- start bit detection
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BitRateDDSAccum <= (others => '0');
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end if;
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end if;
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if Clear = '1' then
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Go <= '0';
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FDGo <= '0';
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FrameDelayCount <= x"01";
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end if;
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OldDDSMSB <= DDSMSB; -- for Phase accumulator MSB edge detection
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if loadbitratel = '1' then
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BitRateDDSReg(7 downto 0) <= ibus;
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end if;
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if loadbitratem = '1' then
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BitRateDDSReg(15 downto 8) <= ibus;
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end if;
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if loadbitrateh = '1' then
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BitRateDDSReg(DDSWidth-1 downto 16) <= ibus(DDSWidth-17 downto 0);
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end if;
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if loadmodel= '1' then
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ModeReg(7 downto 0) <= ibus;
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end if;
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if loadmodem= '1' then
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ModeReg(15 downto 8) <= ibus;
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end if;
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if loadfilter= '1' then
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FilterReg <= ibus;
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end if;
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end if; -- clk
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if loadmodeh = '1' and ibus(0) = '1' then
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Clear <= '1';
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else
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Clear <= '0';
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end if;
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SampleTime <= (not OldDDSMSB) and DDSMSB; -- sample on rising edge of DDS MSB
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DelayTime <= OldDDSMSB and (not DDSMSB);
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Busy <= Go or FDGo or PushRC or (not RCFIFOEmpty);
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obus <= (others => 'Z');
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if poprc = '1' then
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obus(log2(maxFrameSize)-1 downto 0) <= RCPopData; -- note 64 deep max
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obus(7 downto 6) <= ErrPopData;
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end if;
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if popdata = '1' then
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obus <= OutData;
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end if;
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if readbitratel = '1' then
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obus <= BitRateDDSReg(7 downto 0);
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end if;
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if readbitratem = '1' then
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obus <= BitRateDDSReg(15 downto 8);
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end if;
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if readbitrateh = '1' then
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obus(DDSWidth-17 downto 0) <= BitRateDDSReg(DDSWidth-1 downto 16);
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obus(7 downto DDSWidth-16) <= (others => '0');
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end if;
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if readmodel = '1' then
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obus(3 downto 0) <= ModeReg(3 downto 0);
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obus(4) <= RCFIFOError;
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obus(6) <= rxmask;
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obus(7) <= Busy;
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end if;
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if readmodem = '1' then
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obus <= ModeReg(15 downto 8); -- frame delay
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end if;
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if readmodeh = '1' then
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obus(4 downto 0) <= RFrameCount;
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obus(5) <= (not FrameBufferEmpty) and (not Busy); -- buffer error if not expected
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obus(7 downto 6) <= (others => '0');
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end if;
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if readfilter = '1' then
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obus <= FilterReg; -- rx data input filter
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end if;
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end process asimpleuartrx;
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end Behavioral;
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Block a user