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This commit is contained in:
Thaddeus-Maximus
196
5i24/configs/hostmot2/source/periodm.vhd
Executable file
196
5i24/configs/hostmot2/source/periodm.vhd
Executable file
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library ieee;
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use IEEE.std_logic_1164.ALL;
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use IEEE.std_logic_ARITH.ALL;
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use IEEE.std_logic_UNSIGNED.ALL;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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entity periodm is
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port (
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clk : in std_logic;
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ibus : in std_logic_vector (31 downto 0);
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obus : out std_logic_vector (31 downto 0);
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loadmode : in std_logic;
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readmode : in std_logic;
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loadlimit : in std_logic;
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readlimit : in std_logic;
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readperiod : in std_logic;
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readwidth : in std_logic;
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input : in std_logic
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);
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end periodm;
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architecture Behavioral of periodm is
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signal ptimer: std_logic_vector(31 downto 0);
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signal wtimer: std_logic_vector(31 downto 0);
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signal periodlatch: std_logic_vector(31 downto 0);
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signal periodoutlatch: std_logic_vector(31 downto 0);
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signal periodlimit: std_logic_vector(31 downto 0);
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signal prewidthlatch: std_logic_vector(31 downto 0);
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signal widthlatch: std_logic_vector(31 downto 0);
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signal widthoutlatch: std_logic_vector(31 downto 0);
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signal filtercount: std_logic_vector(15 downto 0);
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signal avecount: std_logic_vector(11 downto 0);
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signal modereg: std_logic_vector(31 downto 0);
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alias polarity : std_logic is modereg(0);
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alias filterreg: std_logic_vector(15 downto 0) is modereg(31 downto 16);
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alias avecountreg: std_logic_vector(11 downto 0) is modereg(15 downto 4);
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signal inputd: std_logic;
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signal filtoutput: std_logic;
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signal filtoutputd: std_logic;
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signal filtoutputdd: std_logic;
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signal valid: std_logic;
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signal periodvalid: std_logic;
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begin
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aperiodm: process (clk,readmode,modereg,inputd,readperiod,readwidth,
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periodoutlatch,widthoutlatch,readlimit,periodlimit)
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begin
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if rising_edge(clk) then
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inputd <= polarity xor input;
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if ptimer < periodlimit then -- check if the input frequency is high enough
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ptimer <= ptimer + 1; -- and dead-end the timer
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periodvalid <= '1';
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end if;
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if ptimer = periodlimit then -- if stuck at limit = no signal, period is invalid
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periodvalid <= '0';
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valid <= '0'; -- invalidate status immediately
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end if;
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if (inputd = '1') and (filtercount < filterreg) then -- digital filter on input
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filtercount <= filtercount + 1; -- note: this does not change period/width
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end if; -- but will limit minimum pulse width
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if (inputd = '0') and (filtercount /= 0) then
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filtercount <= filtercount -1;
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end if;
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if filtercount >= filterreg then
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filtoutput <= '1';
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end if;
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if filtercount = 0 then
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filtoutput <= '0';
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end if;
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filtoutputd <= filtoutput;
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if filtoutput = '1' then
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wtimer <= wtimer +1;
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end if;
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if filtoutput = '1' and filtoutputd = '0' then -- on rising edge of input for period
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valid <= periodvalid;
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if avecount = 0 then
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periodlatch <= ptimer;
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avecount <= avecountreg;
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widthlatch <= prewidthlatch; -- likewise with width average
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ptimer <= x"00000000";
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wtimer <= x"00000000";
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else
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avecount <= avecount -1;
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end if;
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end if;
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if filtoutput = '0' and filtoutputd = '1' then -- on falling edge of input
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if avecount = 0 then
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prewidthlatch <= wtimer;
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end if;
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end if;
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if loadmode = '1' then
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modereg(31 downto 3) <= ibus(31 downto 3);
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modereg(0) <= ibus(0);
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end if;
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if loadlimit = '1' then
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periodlimit <= ibus;
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end if;
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if readmode = '1' then -- latch our read data so period and width values
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periodoutlatch <= periodlatch; -- are synchronous. This requires that the mode
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widthoutlatch <= widthlatch; -- register be read first
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end if;
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end if; -- clk
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obus <= (others => 'Z');
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if readmode = '1' then
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obus(31 downto 3) <= modereg(31 downto 3);
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obus(2) <= inputd;
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obus(1) <= valid;
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obus(0) <= polarity;
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end if;
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if readperiod = '1' then
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obus <= periodoutlatch;
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-- obus <= timer;
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end if;
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if readwidth = '1' then
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obus <= widthoutlatch;
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end if;
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if readlimit = '1' then
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obus <= periodlimit;
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end if;
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end process;
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end Behavioral;
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