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This commit is contained in:
Thaddeus-Maximus
313
5i24/configs/hostmot2/source/oneshot.vhd
Executable file
313
5i24/configs/hostmot2/source/oneshot.vhd
Executable file
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library ieee;
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use IEEE.std_logic_1164.ALL;
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use IEEE.std_logic_ARITH.ALL;
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use IEEE.std_logic_UNSIGNED.ALL;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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entity oneshot is
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port ( clk : in std_logic;
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ibus : in std_logic_vector (31 downto 0);
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obus : out std_logic_vector (31 downto 0);
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loadpw1 : in std_logic;
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loadpw2 : in std_logic;
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loadfilter1 : in std_logic;
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loadfilter2 : in std_logic;
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loadrate : in std_logic;
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loadcontrol : in std_logic;
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readcontrol : in std_logic;
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timers : in std_logic_vector(4 downto 0);
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pulse1out : out std_logic;
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pulse2out : out std_logic;
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hwtrigger1 : in std_logic;
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hwtrigger2 : in std_logic);
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end oneshot;
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architecture Behavioral of oneshot is
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signal pw1: std_logic_vector(31 downto 0);
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signal pw2: std_logic_vector(31 downto 0);
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signal pw1count: std_logic_vector(32 downto 0);
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signal pw2count: std_logic_vector(32 downto 0);
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alias pw1countmsb: std_logic is pw1count(32);
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alias pw2countmsb: std_logic is pw2count(32);
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signal pw1prevmsb: std_logic;
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signal pw2prevmsb: std_logic;
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signal rateaccum: std_logic_vector(31 downto 0);
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signal rateaccumreg: std_logic_vector(31 downto 0);
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alias ratemsb: std_logic is rateaccum(31);
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signal timerdiv: std_logic_vector(15 downto 0);
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signal timerdivreg: std_logic_vector(15 downto 0);
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signal trigfilterreg1: std_logic_vector(23 downto 0);
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signal trigfilterreg2: std_logic_vector(23 downto 0);
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signal trigfiltercount1: std_logic_vector(23 downto 0);
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signal trigfiltercount2: std_logic_vector(23 downto 0);
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signal trigger1: std_logic;
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signal trigger2: std_logic;
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signal triggerd1: std_logic;
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signal triggerd2: std_logic;
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signal exttrigger1: std_logic;
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signal exttrigger2: std_logic;
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signal dplltrigger: std_logic;
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signal controlreg: std_logic_vector(31 downto 0);
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signal hwtrigger1d: std_logic;
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signal hwtrigger2d: std_logic;
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signal run1: std_logic;
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signal run2: std_logic;
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alias startselect1: std_logic_vector(2 downto 0) is controlreg(2 downto 0);
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alias startrise1: std_logic is controlreg(3);
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alias startfall1: std_logic is controlreg(4);
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alias retrigger1: std_logic is controlreg(5);
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alias enable1: std_logic is controlreg(6);
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alias reset1: std_logic is controlreg(7);
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alias swtrigger1: std_logic is controlreg(10);
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alias timerselect: std_logic_vector(3 downto 0) is controlreg(15 downto 12);
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alias startselect2: std_logic_vector(2 downto 0) is controlreg(18 downto 16);
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alias startrise2: std_logic is controlreg(19);
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alias startfall2: std_logic is controlreg(20);
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alias retrigger2: std_logic is controlreg(21);
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alias enable2: std_logic is controlreg(22);
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alias reset2: std_logic is controlreg(23);
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alias swtrigger2: std_logic is controlreg(26);
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begin
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aoneshot: process (clk)
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begin
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if rising_edge(clk) then
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triggerd1 <= trigger1;
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triggerd2 <= trigger2;
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hwtrigger1d <= hwtrigger1;
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hwtrigger2d <= hwtrigger2;
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if (hwtrigger1d = '1') and (trigfiltercount1 < trigfilterreg1) then
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trigfiltercount1 <= trigfiltercount1 + 1;
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end if;
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if (hwtrigger1d = '0') and (trigfiltercount1 /= 0) then
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trigfiltercount1 <= trigfiltercount1 -1;
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end if;
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if trigfiltercount1 >= trigfilterreg1 then
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exttrigger1 <= '1';
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-- trigfiltercount1 <= trigfilterreg1; -- handle the case where the filter time is reduced
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end if;
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if trigfiltercount1 = 0 then
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exttrigger1 <= '0';
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end if;
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if (hwtrigger2d = '1') and (trigfiltercount2 < trigfilterreg2) then
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trigfiltercount2 <= trigfiltercount2 + 1;
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end if;
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if (hwtrigger2d = '0') and (trigfiltercount2 /= 0) then
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trigfiltercount2 <= trigfiltercount2 -1;
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end if;
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if trigfiltercount2 >= trigfilterreg2 then
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exttrigger2 <= '1';
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-- trigfiltercount2 <= trigfilterreg2; -- handle the case where the filter time is reduced
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end if;
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if trigfiltercount2 = 0 then
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exttrigger2 <= '0';
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end if;
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rateaccum <= rateaccum + rateaccumreg;
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case startselect1 is
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when "000" => run1 <= '0'; -- cancel any pulse in progress
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when "001" => trigger1 <= swtrigger1;
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when "010" => trigger1 <= exttrigger1;
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when "011" => trigger1 <= dplltrigger;
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when "100" => trigger1 <= ratemsb;
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when "101" => trigger1 <= run1;
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when "110" => trigger1 <= run2;
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when others => run1 <= '0';
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end case;
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case startselect2 is
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when "000" => run2 <= '0'; -- cancel any pulse in progress
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when "001" => trigger2 <= swtrigger2;
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when "010" => trigger2 <= exttrigger2;
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when "011" => trigger2 <= dplltrigger;
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when "100" => trigger2 <= ratemsb;
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when "101" => trigger2 <= run1;
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when "110" => trigger2 <= run2;
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when others => run2 <= '0';
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end case;
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if reset1 = '1' then
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run1 <= '0';
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end if;
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if run1 = '1' then
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if pw1countmsb = '0' then
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pw1count <= pw1count -1;
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end if;
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end if;
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if pw1countmsb = '1' then -- end of pulse
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run1 <= '0';
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end if;
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if (run1 = '0') then
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pw1count(31 downto 0) <= pw1;
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pw1countmsb <='0';
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end if;
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if reset2 = '1' then
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run2 <= '0';
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end if;
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if run2 = '1' then
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if pw2countmsb = '0' then
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pw2count <= pw2count -1;
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end if;
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end if;
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if pw2countmsb = '1' then-- end of pulse
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run2 <= '0';
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end if;
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if (run2 = '0') then
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pw2count(31 downto 0) <= pw2;
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pw2countmsb <='0';
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end if;
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if (startrise1 = '1' and trigger1 = '1' and triggerd1='0' and enable1='1')
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or (startfall1 = '1' and trigger1 = '0' and triggerd1='1' and enable1='1') then
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if retrigger1 = '1' then
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run1 <= '1';
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pw1count(31 downto 0) <= pw1; -- reload timer if retriggerable
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pw1countmsb <='0';
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else
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if run1 = '0' then
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run1 <= '1';
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end if;
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end if;
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end if;
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if (startrise2 = '1' and trigger2 = '1' and triggerd2='0' and enable2='1')
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or (startfall2 = '1' and trigger2 = '0' and triggerd2='1' and enable2='1') then
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if retrigger2 = '1' then
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run2 <= '1';
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pw2count(31 downto 0) <= pw2; -- reload timer if retriggerable
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pw2countmsb <='0';
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else
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if run2 = '0' then
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run2 <= '1';
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end if;
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end if;
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end if;
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if loadcontrol = '1' then
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controlreg <= ibus(31 downto 0);
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end if;
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if loadpw1 = '1' then
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pw1 <= ibus;
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end if;
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if loadpw2 = '1' then
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pw2 <= ibus;
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end if;
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if loadfilter1 = '1' then
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trigfilterreg1 <= ibus(23 downto 0);
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end if;
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if loadfilter2 = '1' then
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trigfilterreg2 <= ibus(23 downto 0);
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end if;
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if loadrate = '1' then
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rateaccumreg <= ibus;
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end if;
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end if; -- clk
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case timerselect(2 downto 0) is
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when "000" => dplltrigger <= timers(0);
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when "001" => dplltrigger <= timers(1);
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when "010" => dplltrigger <= timers(2);
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when "011" => dplltrigger <= timers(3);
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when "100" => dplltrigger <= timers(4);
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when others => dplltrigger <= timers(0);
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end case;
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obus <= (others => 'Z');
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if readcontrol = '1' then
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obus(7 downto 0) <= controlreg(7 downto 0);
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obus(8) <= run1;
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obus(9) <= exttrigger1;
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obus(10) <= swtrigger1;
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obus(15 downto 12) <= timerselect;
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obus(23 downto 16) <= controlreg(23 downto 16);
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obus(24) <= run2;
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obus(25) <= exttrigger2;
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obus(26) <= swtrigger2;
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obus(31 downto 27) <= (others => '0'); -- zero unused readback bits
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obus(11) <= '0';
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end if;
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pulse1out <= run1;
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pulse2out <= run2;
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end process;
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end Behavioral;
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