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This commit is contained in:
Thaddeus-Maximus
213
5i24/configs/hostmot2/source/inmux.vhd
Executable file
213
5i24/configs/hostmot2/source/inmux.vhd
Executable file
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use ieee.math_real.all;
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use ieee.numeric_std.all;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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use work.log2.all;
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entity inmux is -- simple input multiplexor 32 bits max
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generic (
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buswidth : integer := 32;
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muxwidth : integer
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);
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Port (
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clk: in std_logic;
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ibus: in std_logic_vector (buswidth -1 downto 0);
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obus: out std_logic_vector (buswidth -1 downto 0);
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loadcontrol: in std_logic;
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readcontrol: in std_logic;
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loadfilter: in std_logic;
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readfilter: in std_logic;
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readfiltereddata: in std_logic;
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readrawdata: in std_logic;
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muxadd: out std_logic_vector(4 downto 0);
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muxdata: in std_logic
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);
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end inmux;
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architecture behavioral of inmux is
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signal controlreg: std_logic_vector(31 downto 0) := std_logic_vector(to_unsigned(integer(muxwidth-1),32));
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alias maxcount: std_logic_vector(4 downto 0) is controlreg(4 downto 0);
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alias globalinvert: std_logic is controlreg(5);
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alias ratediv: std_logic_vector(9 downto 0) is controlreg(15 downto 6);
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alias timelong: std_logic_vector(9 downto 0) is controlreg(31 downto 22);
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alias timeshort: std_logic_vector(5 downto 0) is controlreg(21 downto 16);
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signal ratecount: std_logic_vector(9 downto 0);
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signal rawdata: std_logic_vector(muxwidth -1 downto 0);
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signal filtereddata: std_logic_vector(muxwidth -1 downto 0);
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signal filterreg: std_logic_vector(muxwidth -1 downto 0);
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type filtercounttype is array(muxwidth -1 downto 0) of std_logic_vector(9 downto 0);
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signal filtercount: filtercounttype;
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signal syncdata: std_logic;
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signal muxdatad: std_logic;
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signal gfcount: std_logic_vector(2 downto 0);
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signal gfdata: std_logic;
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signal muxcount: std_logic_vector(4 downto 0);
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signal prescale: std_logic_vector(1 downto 0);
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signal index: integer;
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begin
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ainmux: process (clk,
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controlreg,
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muxdata,
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ibus)
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begin
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if rising_edge(clk) then
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prescale <= prescale +1;
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muxdatad <= muxdata xor globalinvert;
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if muxdatad = '1' then -- 7 count glitch filter on muxdata
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if gfcount < 7 then
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gfcount <= gfcount +1;
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end if;
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else
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if gfcount /= 0 then
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gfcount <= gfcount -1;
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end if;
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end if;
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if gfcount = 0 then
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gfdata <= '0';
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end if;
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if gfcount = 7 then
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gfdata <= '1';
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end if;
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if prescale = 0 then
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if ratecount /= 0 then
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ratecount <= ratecount -1;
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else -- for every scanned pin
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ratecount <= ratediv;
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index <= to_integer(unsigned(muxcount)); -- note 1 muxcount pipeline delay
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syncdata <= gfdata;
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rawdata(index) <= syncdata; -- raw (unfiltered) data
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if rawdata(integer(index)) = '1' then -- count up
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if filterreg(index) = '1' then -- if filter bit is 1 use timelong
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if filtercount(index) < timelong then
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filtercount(index) <= filtercount(index) +1;
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end if;
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if filtercount(index) = timelong then
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filtereddata(index) <= '1';
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end if;
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else
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if filtercount(index) < "0000"×hort then -- if filter bit is 0 use timeshort
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filtercount(index) <= filtercount(index) +1;
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end if;
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if filtercount(index) >= "0000"×hort then
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filtereddata(index) <= '1';
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end if;
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end if;
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else -- count down
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if filtercount(index) > 0 then
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filtercount(index) <= filtercount(index) -1;
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end if;
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if filtercount(index) = 0 then
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filtereddata(index) <= '0';
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end if;
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end if;
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if muxcount /= 0 then
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muxcount <= muxcount-1;
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else
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muxcount <= maxcount;
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end if;
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end if; -- ratecount=0
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end if; -- prescale = 0
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if loadcontrol = '1' then
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controlreg(31 downto 5) <= ibus(31 downto 5); -- mux size (4 downto 0) is read only
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end if;
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if loadfilter = '1' then
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filterreg <= ibus(muxwidth-1 downto 0);
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end if;
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end if; -- clk
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obus <= (others => 'Z');
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if readcontrol = '1' then
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obus <= controlreg;
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end if;
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if readfilter = '1' then
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obus(muxwidth-1 downto 0) <= filterreg;
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obus(Buswidth-1 downto muxwidth) <= ( others => '0' );
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end if;
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if readfiltereddata = '1' then
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obus(muxwidth-1 downto 0) <= filtereddata;
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obus(Buswidth-1 downto muxwidth) <= ( others => '0' );
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end if;
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if readrawdata = '1' then
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obus(muxwidth-1 downto 0) <= rawdata;
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obus(Buswidth-1 downto muxwidth) <= ( others => '0' );
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end if;
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muxadd <= muxcount;
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end process;
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end behavioral;
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