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This commit is contained in:
Thaddeus-Maximus
295
5i24/configs/hostmot2/source/fanucabs.vhd
Executable file
295
5i24/configs/hostmot2/source/fanucabs.vhd
Executable file
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.MATH_REAL.ALL;
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--
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-- Copyright (C) 2009, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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entity FanucAbs is
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generic (
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Clock : integer
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);
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Port (clk : in std_logic;
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ibus : in std_logic_vector(31 downto 0);
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obus : out std_logic_vector(31 downto 0);
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loadcontrol0 : in std_logic;
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loadcontrol1 : in std_logic;
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loadcontrol2 : in std_logic;
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lstart : in std_logic;
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pstart : in std_logic;
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timers : in std_logic_vector(4 downto 0);
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readdata0 : in std_logic;
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readdata1 : in std_logic;
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readdata2 : in std_logic;
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readcontrol0 : in std_logic;
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readcontrol1 : in std_logic;
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busyout : out std_logic;
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davout: out std_logic;
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requestout : out std_logic;
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rxdata : in std_logic;
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testclk : out std_logic
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);
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end FanucABS;
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architecture Behavioral of FanucABS is
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constant DDSSize : integer := 20;
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constant DefaultBRDDS : real :=
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round((2**real(DDSSize))*(1024000.0/real(Clock)));
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signal BitrateDDSReg : std_logic_vector(DDSSize-1 downto 0) :=
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std_logic_vector(to_unsigned(integer(DefaultBRDDS),DDSSize));
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signal BitrateDDSAccum : std_logic_vector(DDSSize-1 downto 0);
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alias DDSMSB : std_logic is BitrateDDSAccum(DDSSize-1);
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signal OldDDSMSB: std_logic;
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signal BitCountReg : std_logic_vector(6 downto 0) :=
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std_logic_vector(to_unsigned(76,7));
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signal BitCount : std_logic_vector(6 downto 0);
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constant DefaultReqWidthReg : real := round(real(Clock)*8.0e-6);
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signal RequestWidthReg : std_logic_vector(9 downto 0) :=
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std_logic_vector(to_unsigned(integer(DefaultReqWidthReg),10));
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signal RequestWidth : std_logic_vector(9 downto 0);
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signal FAbsSreg: std_logic_vector(75 downto 0);
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signal FAbsLatch: std_logic_vector(75 downto 0);
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signal TimerSelect: std_logic_vector(2 downto 0);
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signal Timer: std_logic;
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signal OldTimer: std_logic;
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signal TStart: std_logic;
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signal RXGo: std_logic;
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signal Start: std_logic;
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signal Busy: std_logic;
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signal Request: std_logic;
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signal RXDone: std_logic;
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signal OldRXDone: std_logic;
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signal InvertMask: std_logic;
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signal PStartmask: std_logic;
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signal TStartmask: std_logic;
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signal SampleTime: std_logic;
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signal FilterTime: std_logic_vector(3 downto 0);
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signal FilterTimeReg: std_logic_vector(3 downto 0) := "1111";
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signal FilteredRXData: std_logic;
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signal RXDataD: std_logic;
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signal RXPipe : std_logic_vector(1 downto 0);
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signal EnableSetupLoad: std_logic := '0';
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signal CableErr: std_logic := '0';
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signal DAV : std_logic := '0';
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begin
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afabsinterface: process (clk, lstart, tstart, TStartmask , pstart, PStartmask,
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BitrateDDSAccum, OldDDSMSB, readdata0, FAbsLatch,
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readdata1, readdata2, readcontrol0, BitCountReg, RXGo,
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Busy, RequestWidthReg, readcontrol1, BitrateDDSReg, Request,
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Timer,OldTimer,TimerSelect,Timers,CableErr,DAv,FilterTimeReg)
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begin
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if clk'event and clk = '1' then
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RXDataD <= rxdata; -- first stage sync
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if RXdataD = '0' then
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if FilterTime /=0 then
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FilterTime <= FilterTime -1;
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end if;
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else
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if FilterTime /= FilterTimeReg then
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FilterTIme <= FilterTime +1;
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end if;
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end if;
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if FilterTime = 0 then
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FilteredRXData <= '0';
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end if;
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if FilterTime = FilterTimeReg then
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FilteredRXData <= '1';
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end if;
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RXPipe <= RXPipe(0) & FilteredRXData; -- Two stage rx data pipeline to compensate for
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-- start bit --> dds startup time
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if Start = '1' then
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BitCount <= BitCountReg;
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RequestWidth <= RequestWidthReg;
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BitRateDDSAccum <= (others => '0');
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FAbsSReg <= (Others => '0');
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Busy <= '1';
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RXGo <= '0'; -- reset Go if it was running/waiting
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RXDone <= '0';
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CableErr <= FilteredRXData; -- if we have a start bit here we have a cable/polarity error
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end if;
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if RequestWidth /=0 then -- request pulse one shot
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RequestWidth <= RequestWidth -1;
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Request <= '1';
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else
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Request <= '0';
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end if;
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if (Busy = '1') and (RXDone = '0') and (FilteredRXData = '1') then
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RXGo <= '1'; -- start bit detection
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end if;
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if RXGo = '1' then -- Receive go
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BitRateDDSAccum <= BitRateDDSAccum + BitRateDDSReg;
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if SampleTime = '1' then
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FAbsSReg <= (not RXPipe(1)) & FAbsSReg(75 downto 1) ; -- shiftright
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if BitCount /= 0 then
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BitCount <= BitCount -1;
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else
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RXDone <= '1'; -- minor buglet: we are actually done 1/2 bit
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end if; -- time later, but probably not worth fixing
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end if;
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end if;
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if (RXDone = '1') and (OldRXDone = '0') then -- on rxdone becoming true we
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RXGo <= '0'; -- stop receiving
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FAbsLatch <= FAbsSReg; -- transfer data
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Busy <= '0';
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DAV <= not CableErr; -- dont set DAV if theres a cable error
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end if;
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OldDDSMSB <= DDSMSB;
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OldRXDone <= RXDone;
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if loadcontrol0 = '1' then
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EnableSetupLoad <= ibus(24);
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PStartMask <= ibus(8);
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TStartMask <= ibus(9);
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TimerSelect <= ibus(14 downto 12);
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end if;
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if loadcontrol1 = '1' and EnableSetupLoad = '1'then
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BitRateDDSReg <= ibus(19 downto 0);
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FilterTimeReg <= ibus(31 downto 28);
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end if;
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if loadcontrol2 = '1' and EnableSetupLoad = '1' then
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RequestWidthReg <= ibus(23 downto 14);
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BitCountReg <= ibus(30 downto 24);
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end if;
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if readdata0 = '1' then
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DAV <= '0';
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end if;
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OldTimer <= Timer;
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end if; -- clk
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SampleTime <= DDSMSB and (not OldDDSMSB);
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if Timer = '1' and OldTimer = '0' then -- rising edge of selected timer
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TStart <= '1';
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else
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TStart <= '0';
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end if;
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case TimerSelect is
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when "000" => Timer <= timers(0);
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when "001" => Timer <= timers(1);
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when "010" => Timer <= timers(2);
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when "011" => Timer <= timers(3);
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when "100" => Timer <= timers(4);
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when others => Timer <= Timers(0);
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end case;
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if lstart = '1' or (TStart = '1' and TStartMask = '1') or (pstart = '1' and PStartMask = '1')then
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Start <= '1';
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else
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Start <= '0';
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end if;
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obus <= (others => 'Z');
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if readdata0 = '1' then
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obus <= FAbsLatch(31 downto 0);
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end if;
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if readdata1 = '1' then
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obus <= FAbsLatch(63 downto 32);
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end if;
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if readdata2 = '1' then
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obus(11 downto 0) <= FAbsLatch(75 downto 64);
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obus(13 downto 12) <= (others =>'0');
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obus(23 downto 14) <= RequestWidthReg;
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obus(30 downto 24) <= BitCountReg;
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obus(31) <= CableErr;
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end if;
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if readcontrol0 = '1' then
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obus(7 downto 0) <= (others =>'0');
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obus(8) <= PStartMask;
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obus(9) <= TStartMask;
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obus(10) <= RXGo;
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obus(11) <= Busy;
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obus(14 downto 12) <= TimerSelect;
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obus(15) <= DAV;
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obus(31 downto 16) <= (others =>'0');
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end if;
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if readcontrol1 = '1' then
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obus(19 downto 0) <= BitRateDDSReg;
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obus(31 downto 28) <= FilterTimeReg;
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obus(27 downto 20) <= (others => '0');
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end if;
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testclk <= DDSMSB;
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requestout <= not Request;
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busyout <= Busy or (not DAV);
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davout <= DAV;
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end process afabsinterface;
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end Behavioral;
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