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Thaddeus-Maximus
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5i24/configs/hostmot2/source/dpwmpdmgenh.vhd
Executable file
260
5i24/configs/hostmot2/source/dpwmpdmgenh.vhd
Executable file
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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entity dpwmpdmgenh is
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generic (
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buswidth : integer;
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refwidth : integer
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);
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port (
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clk: in std_logic;
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hclk: in std_logic;
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refcount: in std_logic_vector (refwidth-1 downto 0);
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ibus: in std_logic_vector (buswidth -1 downto 0);
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loadpwmval: in std_logic;
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pcrloadcmd: in std_logic;
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pdmrate : in std_logic;
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pwmouta: out std_logic;
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pwmoutb: out std_logic
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);
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end dpwmpdmgenh;
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architecture behavioral of dpwmpdmgenh is
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signal prepwmval: std_logic_vector (refwidth-2 downto 0);
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signal pwmval: std_logic_vector (refwidth-2 downto 0);
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signal fixedrefcount: std_logic_vector (refwidth-2 downto 0);
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signal pdmaccum: std_logic_vector (refwidth-1 downto 0);
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alias pdmbit: std_logic is pdmaccum(refwidth-1);
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signal preditherval: std_logic_vector(3 downto 0);
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signal ditherval: std_logic_vector(3 downto 0);
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signal dpwmval: std_logic_vector (refwidth-2 downto 0);
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signal ditheraccum: std_logic_vector(4 downto 0);
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alias ditherup: std_logic is ditheraccum(4);
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signal maskedrefcount: std_logic_vector (refwidth-2 downto 0);
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signal pwm: std_logic;
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signal dir: std_logic;
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signal toggle: std_logic;
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signal mask: std_logic_vector (refwidth-2 downto 0);
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signal predir: std_logic;
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signal premodereg: std_logic_vector(6 downto 0);
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signal modereg: std_logic_vector(6 downto 0);
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alias pwmwidth: std_logic_vector(1 downto 0) is modereg(1 downto 0);
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alias pwmmode: std_logic is modereg(2);
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alias pwmoutmode: std_logic_vector(1 downto 0) is modereg(4 downto 3);
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alias doublebuf: std_logic is modereg(5);
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alias ditherena: std_logic is modereg(6);
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signal loadpwmreq: std_logic;
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signal oldloadpwmreq: std_logic;
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signal olderloadpwmreq: std_logic;
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signal loadpcrreq: std_logic;
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signal oldloadpcrreq: std_logic;
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signal olderloadpcrreq: std_logic;
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signal oldtoggle: std_logic;
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signal cyclestart: std_logic;
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begin
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apwmgen: process (clk,hclk,refcount,ibus,loadpwmval,pwmval,pwm,
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fixedrefcount,mask,pwmmode,toggle,oldtoggle,
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pwmwidth,olderloadpwmreq,olderloadpcrreq,
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pwmoutmode,dir,pdmaccum
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)
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begin
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if rising_edge(hclk) then
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if pdmrate = '1' then
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pdmaccum <= ('0'&pdmaccum(refwidth-2 downto 0)) + ('0'&pwmval);
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end if;
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if oldloadpwmreq = '1' and olderloadpwmreq = '1' then
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pwmval <= prepwmval;
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ditherval <= preditherval;
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dir <= predir;
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oldloadpwmreq <= '0';
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end if;
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if oldloadpcrreq = '1' and olderloadpcrreq ='1' then
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modereg <= premodereg;
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end if;
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if cyclestart = '1' then
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ditheraccum <= '0'& ditheraccum(3 downto 0) + ('0' & ditherval);
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end if;
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olderloadpwmreq <= oldloadpwmreq;
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olderloadpcrreq <= oldloadpcrreq;
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if (loadpwmreq and (cyclestart or (not doublebuf))) = '1' then
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oldloadpwmreq <= '1';
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end if;
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-- oldloadpwmreq <= loadpwmreq and (cyclestartflag or (not doublebuf));
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oldloadpcrreq <= loadpcrreq;
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-- was combinatorial but now pipelined to meet 100 MHz timing
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if (ditherup = '1') and (ditherena = '1') then
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dpwmval <= pwmval + 1;
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else
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dpwmval <= pwmval;
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end if;
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if (UNSIGNED(maskedrefcount) < UNSIGNED(dpwmval)) then
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pwm <= '1';
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else
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pwm <= '0';
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end if;
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case pwmmode is
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when '0' => fixedrefcount <= refcount(refwidth-2 downto 0);
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when '1' =>
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if toggle = '1' then -- symmetrical mode
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fixedrefcount <= (not refcount(refwidth-2 downto 0));
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else
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fixedrefcount <= refcount(refwidth-2 downto 0);
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end if;
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when others => null;
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end case;
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oldtoggle <= toggle;
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end if; -- hclk
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maskedrefcount <= fixedrefcount and mask;
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if pwmmode = '1' then
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cyclestart <= ((not toggle) and oldtoggle); -- falling edge of toggle sym mode
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else
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cyclestart <= toggle xor oldtoggle; -- both edges of toggle ramp mode
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end if;
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case pwmwidth is
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when "00" =>
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mask(refwidth-2 downto refwidth-4) <= "000";
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mask(refwidth-5 downto 0) <= ( others => '1');
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toggle <= refcount(refwidth-4);
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when "01" =>
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mask(refwidth-2 downto refwidth-3) <= "00";
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mask(refwidth-4 downto 0) <= ( others => '1');
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toggle <= refcount(refwidth-3);
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when "10" =>
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mask(refwidth-2) <= '0';
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mask(refwidth-3 downto 0) <= ( others => '1');
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toggle <= refcount(refwidth-2);
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when "11" =>
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mask <= (others => '1');
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toggle <= refcount(refwidth-1);
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when others => null;
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end case;
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if rising_edge(clk) then -- 33/48/50 mhz local bus clock
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if loadpwmval = '1' then
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prepwmval <= ibus((refwidth-2)+16 downto 16); -- Fixme! only works for buswidth 32
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preditherval <= ibus(15 downto 12);
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predir <= ibus(BusWidth -1);
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loadpwmreq <= '1';
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end if;
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if pcrloadcmd = '1' then
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premodereg <= ibus(6 downto 0);
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loadpcrreq <= '1';
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end if;
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end if; -- clk
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if olderloadpwmreq = '1' then -- asynchronous request clear, could use flancter but dont need async clear
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loadpwmreq <= '0';
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end if;
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if olderloadpcrreq = '1' then -- asynchronous request clear ""
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loadpcrreq <= '0';
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end if;
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case pwmoutmode is
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when "00" =>
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pwmouta <= pwm; -- normal sign magnitude
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pwmoutb <= dir;
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when "01" =>
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pwmouta <= dir; -- reversed pwm/dir = locked antiphase
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pwmoutb <= pwm;
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when "10" =>
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if dir = '1' then -- up/down mode
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pwmouta <= pwm;
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pwmoutb <= '0';
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else
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pwmouta <= '0';
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pwmoutb <= pwm;
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end if;
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when "11" =>
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pwmouta <= pdmbit;
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pwmoutb <= dir;
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when others => null;
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end case;
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-- pwmoutc <= ena;
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end process;
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end behavioral;
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