?
This commit is contained in:
Thaddeus-Maximus
426
5i24/configs/hostmot2/source/bufferedspi.vhd
Executable file
426
5i24/configs/hostmot2/source/bufferedspi.vhd
Executable file
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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entity bufferedspi is
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generic (
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cswidth : integer := 4;
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gatedcs : boolean := true
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);
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port (
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clk : in std_logic;
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ibus : in std_logic_vector(31 downto 0);
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obus : out std_logic_vector(31 downto 0);
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addr : in std_logic_vector(3 downto 0);
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hostpush : in std_logic;
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hostpop : in std_logic;
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loadasend : in std_logic;
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loaddesc : in std_logic;
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clear : in std_logic;
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readcount : in std_logic;
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spiclk : out std_logic;
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spiin : in std_logic;
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spiout: out std_logic;
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spiframe: out std_logic;
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spicsout: out std_logic_vector(cswidth-1 downto 0)
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);
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end bufferedspi;
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architecture behavioral of bufferedspi is
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constant DivWidth: integer := 8;
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-- spi interface related signals
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signal RateDiv : std_logic_vector(DivWidth -1 downto 0);
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signal ModeReg : std_logic_vector(31 downto 0);
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signal LoadData : std_logic;
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signal StartCycle : std_logic;
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alias BitcountReg : std_logic_vector(5 downto 0) is ModeReg(5 downto 0);
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alias CPOL : std_logic is ModeReg(6);
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alias CPHA : std_logic is ModeReg(7);
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alias RateDivReg : std_logic_vector(DivWidth -1 downto 0) is ModeReg(15 downto 8);
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alias CSReg : std_logic_vector(cswidth -1 downto 0) is ModeReg(cswidth-1 +16 downto 16);
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alias CSTimerReg : std_logic_vector(4 downto 0) is ModeReg(28 downto 24);
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alias SampleLate : std_logic is ModeReg(29);
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alias DontClearFrame : std_logic is ModeReg(30);
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alias DontEcho : std_logic is ModeReg(31);
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signal BitCount : std_logic_vector(5 downto 0);
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signal ClockFF: std_logic;
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signal SPISreg: std_logic_vector(31 downto 0);
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signal LFrame: std_logic;
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signal EFrame: std_logic;
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signal Dav: std_logic;
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signal SPIInLatch: std_logic;
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signal SPIData: std_logic;
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signal FirstLeadingEdge: std_logic;
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signal CSTimer: std_logic_vector(4 downto 0);
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alias CSTimerDone: std_logic is CSTimer(4);
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-- input FIFO related signals
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signal ipopadd: std_logic_vector(3 downto 0) := x"f";
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signal ipopdata: std_logic_vector(31 downto 0);
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signal idatacounter: std_logic_vector(4 downto 0);
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signal ipush: std_logic;
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signal ififohasdata: std_logic;
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-- output FIFO related signals
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signal opushdata: std_logic_vector(35 downto 0);
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signal opopadd: std_logic_vector(3 downto 0) := x"f";
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signal opopdata: std_logic_vector(35 downto 0);
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signal odatacounter: std_logic_vector(4 downto 0);
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signal opop: std_logic;
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signal ofifohasdata: std_logic;
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-- autosend table related signals
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signal autosenddata: std_logic_vector(35 downto 0);
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signal autosendadd: std_logic_vector(3 downto 0);
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signal autosendlength: std_logic_vector(3 downto 0);
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-- channel descriptor related signals
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signal desc: std_logic_vector(31 downto 0);
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alias CSTimerFromDesc : std_logic_vector(4 downto 0) is desc(28 downto 24);
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signal descptr: std_logic_vector(3 downto 0);
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component SRL16E
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--
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generic (INIT : bit_vector);
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--
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port (D : in std_logic;
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CE : in std_logic;
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CLK : in std_logic;
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A0 : in std_logic;
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A1 : in std_logic;
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A2 : in std_logic;
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A3 : in std_logic;
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Q : out std_logic);
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end component;
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begin
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ofifo: for i in 0 to 35 generate
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asr16e: SRL16E generic map (x"0000") port map(
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D => opushdata(i),
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CE => hostpush,
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CLK => clk,
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A0 => opopadd(0),
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A1 => opopadd(1),
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A2 => opopadd(2),
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A3 => opopadd(3),
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Q => opopdata(i)
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);
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end generate;
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ififo: for i in 0 to 31 generate
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asr16e: SRL16E generic map (x"0000") port map(
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D => SPISReg(i),
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CE => ipush,
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CLK => clk,
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A0 => ipopadd(0),
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A1 => ipopadd(1),
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A2 => ipopadd(2),
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A3 => ipopadd(3),
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Q => ipopdata(i)
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);
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end generate;
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autosendtable: for i in 0 to 35 generate
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asr16e: SRL16E generic map (x"0000") port map(
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D => opushdata(i),
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CE => loadasend,
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CLK => clk,
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A0 => autosendadd(0),
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A1 => autosendadd(1),
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A2 => autosendadd(2),
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A3 => autosendadd(3),
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Q => autosenddata(i)
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);
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end generate;
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chandesc: for i in 0 to 31 generate
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asr16e: SRL16E generic map (x"0000") port map(
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D => ibus(i),
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CE => loaddesc,
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CLK => clk,
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A0 => descptr(0), -- the address that was pushed
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A1 => descptr(1),
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A2 => descptr(2),
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A3 => descptr(3),
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Q => desc(i)
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);
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end generate;
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outfifo: process (clk,opopdata,odatacounter)
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begin
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if rising_edge(clk) then
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if hostpush = '1' and opop = '0' then
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if odatacounter /= 16 then -- a push
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-- always increment the data counter if not full
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odatacounter <= odatacounter +1;
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opopadd <= opopadd +1; -- popadd must follow data down shiftreg
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end if;
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end if;
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if (opop = '1') and (hostpush = '0') and (ofifohasdata = '1') then -- a pop
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-- always decrement the data counter if not empty
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odatacounter <= odatacounter -1;
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opopadd <= opopadd -1;
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end if;
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-- if both push and pop are asserted we dont change either counter
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if clear = '1' then -- a clear fifo
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opopadd <= (others => '1');
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odatacounter <= (others => '0');
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end if;
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end if; -- clk rise
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if odatacounter = 0 then
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ofifohasdata <= '0';
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else
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ofifohasdata <= '1';
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end if;
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end process outfifo;
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infifo: process (clk,ipopdata,odatacounter)
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begin
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if rising_edge(clk) then
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if ipush = '1' and hostpop = '0' then
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if idatacounter /= 16 then -- a push
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-- always increment the data counter if not full
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idatacounter <= idatacounter +1;
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ipopadd <= ipopadd +1; -- popadd must follow data down shiftreg
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end if;
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end if;
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if (hostpop = '1') and (ipush = '0') and (ififohasdata = '1') then -- a pop
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-- always decrement the data counter if not empty
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idatacounter <= idatacounter -1;
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ipopadd <= ipopadd -1;
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end if;
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-- if both push and pop are asserted we dont change either counter
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if clear = '1' then -- a clear fifo
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ipopadd <= (others => '1');
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idatacounter <= (others => '0');
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end if;
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end if; -- clk rise
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if idatacounter = 0 then
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ififohasdata <= '0';
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else
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ififohasdata <= '1';
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end if;
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end process infifo;
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aspiinterface: process (clk, ModeReg, ClockFF, LFrame,
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SPISreg, BitcountReg, opopdata,
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Dav,RateDivReg,addr, ibus,
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hostpop, ipopdata, readcount,
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idatacounter, odatacounter)
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begin
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if rising_edge(clk) then
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if StartCycle = '0' and ofifohasdata = '1' and opop = '0'
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and CSTimerDone= '1' and LFrame = '0' and Dav = '0' and loaddata = '0' then
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-- if SPI shift register is free and we have data and CS setup/hold time is passed
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ModeReg <= desc;
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CSTimer <= CSTimerFromDesc; -- load early for pre-LFrame delay
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StartCycle <= '1';
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end if;
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if StartCycle = '1' then
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if CSTimerDone = '1' then
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StartCycle <= '0';
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LoadData <= '1';
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end if;
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end if;
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if Dav = '1' then
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if DontEcho = '0' then
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ipush <= '1'; -- push SPI recieve data on ififo
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end if;
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Dav <= '0';
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end if;
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if ipush = '1' then
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ipush <= '0';
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end if;
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if loaddata = '1' then
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SPISreg <= opopdata(31 downto 0);
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BitCount <= BitCountReg;
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LFrame <= '1';
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EFrame <= '1';
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ClockFF <= '0';
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FirstLeadingEdge <= '1';
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RateDiv <= RateDivReg;
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loaddata <= '0';
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opop <= '1';
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end if;
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if opop = '1' then
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opop <= '0';
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end if;
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if CSTimerDone = '0' then
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CSTimer <= CSTimer -1;
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end if;
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if LFrame = '1' then -- single shift register SPI
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if RateDiv = 0 then -- maybe update to dual later to allow
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RateDiv <= RateDivReg; -- receive data skew adjustment
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SPIInLatch <= spiin; -- spi in data latched on every edge
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if ClockFF = '0' then -- clock was low
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if BitCount(5) = '1' then -- underflow so done
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LFrame <= '0'; -- LFrame cleared 1/2 SPI clock after GO
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if DontClearFrame = '0' then
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EFrame <= '0'; -- EFrame only cleared if DontClearFrame is false
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end if;
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Dav <= '1';
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CSTimer <= CSTimerReg; -- load timer from copy for post LFrame delay
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else
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ClockFF <= '1';
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end if;
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if CPHA = '1' and FirstLeadingEdge = '0' then -- shift out on leading edge for CPHA = 1 case
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SPISreg <= SPISreg(30 downto 0) & SPIData; -- shift in data is from previous faling edge
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end if;
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FirstLeadingEdge <= '0';
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else -- clock was high
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ClockFF <= '0';
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BitCount <= BitCount -1;
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if CPHA = '0' then -- shift out on trailing edge for CPHA = 0 case
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SPISreg <= SPISreg(30 downto 0) & SPIData; -- shift in data is from previous rising edge
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end if;
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end if;
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else
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RateDiv <= RateDiv -1;
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end if;
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end if;
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if clear = '1' then
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LFrame <= '0';
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EFrame <= '0';
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ClockFF <= '0';
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Dav <= '0';
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LoadData <= '0';
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StartCycle <= '0';
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CSTimerDone <= '0';
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ipush <= '0';
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end if;
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end if; -- clk
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if SampleLate = '1' then
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SPIData <= spiin;
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else
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SPIData <= SPIInLatch;
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end if;
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opushdata <= addr & ibus; -- push address to select descriptor at far end of FIFO
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descptr <= opopdata(35 downto 32); -- here!
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obus <= (others => 'Z');
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if hostpop = '1' then
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obus <= ipopdata;
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end if;
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if readcount = '1' then
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obus(4 downto 0) <= idatacounter;
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obus(7 downto 5) <= (others => '0');
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obus(12 downto 8) <= odatacounter;
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obus(31 downto 13) <= (others => '0');
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end if;
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spiclk <= ClockFF xor CPOL;
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spiframe <= not EFrame;
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if gatedcs then -- gated/decoded CS/frame = DBSPI
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for i in CSwidth-1 downto 0 loop
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if i = conv_integer(CSReg) then
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spicsout(i) <= not EFrame;
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else
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spicsout(i) <= '1';
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end if;
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end loop;
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report("Decoded BSPI found");
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else
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spicsout <= CSReg; -- decoded select with separate frame = BSPI
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report("Normal BSPI found");
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end if;
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spiout <= SPISReg(conv_integer(BitCountReg(4 downto 0)));
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end process aspiinterface;
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end Behavioral;
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Block a user