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This commit is contained in:
Thaddeus-Maximus
422
5i24/configs/hostmot2/source/biss_loop.vhd
Executable file
422
5i24/configs/hostmot2/source/biss_loop.vhd
Executable file
@@ -0,0 +1,422 @@
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--
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-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
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-- http://www.mesanet.com
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--
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-- This program is is licensed under a disjunctive dual license giving you
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-- the choice of one of the two following sets of free software/open source
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-- licensing terms:
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--
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-- * GNU General Public License (GPL), version 2.0 or later
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-- * 3-clause BSD License
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--
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--
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-- The GNU GPL License:
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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--
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--
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-- The 3-clause BSD License:
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--
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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--
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-- * Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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--
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-- * Redistributions in binary form must reproduce the above
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-- copyright notice, this list of conditions and the following
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-- disclaimer in the documentation and/or other materials
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-- provided with the distribution.
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--
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-- * Neither the name of Mesa Electronics nor the names of its
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-- contributors may be used to endorse or promote products
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-- derived from this software without specific prior written
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-- permission.
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--
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--
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-- Disclaimer:
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--
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-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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--
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use work.log2.all;
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use work.oneofndecode.all;
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entity biss is
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port (
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clk : in std_logic;
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hclk : in std_logic;
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ibus : in std_logic_vector(31 downto 0);
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obus : out std_logic_vector(31 downto 0);
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poplifo : in std_logic;
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lstart : in std_logic;
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pstart : in std_logic;
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timers : in std_logic_vector(4 downto 0);
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loadcontrol0 : in std_logic;
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loadcontrol1 : in std_logic;
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readcontrol0 : in std_logic;
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readcontrol1 : in std_logic;
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lifohasdata : out std_logic;
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busyout: out std_logic;
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davout: out std_logic;
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testdata: out std_logic;
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sampletime: out std_logic;
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bissclk : out std_logic;
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bissdata : in std_logic
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);
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end biss;
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architecture Behavioral of biss is
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-- BISS interface related signals
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constant DDSWidth : integer := 16; -- 16 max
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constant BitLength : integer := 10; -- limited by SLR16 x 32 bits wide so 512 bits
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constant TestDataConst : std_logic_vector(31 downto 0) := x"AABCD123";
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signal BitLengthReg : std_logic_vector(BitLength-1 downto 0);
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signal BitCount : std_logic_vector(BitLength-1 downto 0);
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signal BitrateDDSReg : std_logic_vector(DDSWidth-1 downto 0);
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signal BitPointer : std_logic_vector(4 downto 0);
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alias BitPointerMSB : std_logic is BitPointer(4);
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signal OldBitPointerMSB : std_logic;
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signal FilterTime : std_logic_vector(32-Bitlength-DDSWidth-1 downto 0);
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signal FilterTimeReg : std_logic_vector(32-Bitlength-DDSWidth-1 downto 0);
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signal FilteredBISSData : std_logic;
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signal XmitDDSAccum : std_logic_vector(DDSWidth-1 downto 0);
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alias XmitDDSMSB : std_logic is XmitDDSAccum(DDSWidth-1);
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signal OldXmitDDSMSB: std_logic;
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signal RecvDDSAccum : std_logic_vector(DDSWidth-1 downto 0);
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alias RecvDDSMSB : std_logic is RecvDDSAccum(DDSWidth-1);
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signal OldRecvDDSMSB : std_logic;
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signal RXSampleTime: std_logic;
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signal XmitClockRE : std_logic;
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signal BISSDataD : std_logic;
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signal BISSDataPipe: std_logic_vector(2 downto 0);
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signal XGo: std_logic := '0';
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signal RGo: std_logic := '0';
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signal DGo: std_logic := '0';
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signal DAV: std_logic := '0';
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signal SyncDAV: std_logic := '0';
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signal TimerSelect: std_logic_vector(2 downto 0);
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signal Timer: std_logic;
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signal OldTimer: std_logic;
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signal TStart: std_logic := '0';
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signal TStartMask: std_logic := '0';
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signal PStartMask: std_logic := '0';
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signal StartReq: std_logic := '0';
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signal StartReq1: std_logic := '0';
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signal StartReq2: std_logic := '0';
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signal PopReq: std_logic := '0';
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signal PopReq1: std_logic := '0';
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signal PopReq2: std_logic := '0';
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-- test signals
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signal SampleToggle: std_logic;
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signal TestDataSR: std_logic_vector(31 downto 0);
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-- LIFO related signals
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signal PushData: std_logic_vector(31 downto 0);
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signal PopAdd: std_logic_vector(3 downto 0) := x"f";
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signal PopData: std_logic_vector(31 downto 0);
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signal DataCounter: std_logic_vector(4 downto 0);
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signal PushBit: std_logic_vector(31 downto 0);
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signal Push: std_logic;
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signal Pop: std_logic;
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signal ClearLIFO: std_logic;
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signal llifoempty: std_logic;
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signal llifohasdata: std_logic;
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component SRL16E
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--
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generic (INIT : bit_vector);
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--
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port (D : in std_logic;
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CE : in std_logic;
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CLK : in std_logic;
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A0 : in std_logic;
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A1 : in std_logic;
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A2 : in std_logic;
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A3 : in std_logic;
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Q : out std_logic);
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end component;
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begin
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lifosrl: for i in 0 to 31 generate
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asr16e: SRL16E generic map (x"0000") port map(
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D => BissDataPipe(2),
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CE => PushBit(i),
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CLK => hclk,
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A0 => PopAdd(0),
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A1 => PopAdd(1),
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A2 => PopAdd(2),
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A3 => PopAdd(3),
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Q => PopData(i)
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);
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end generate;
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alifo: process (hclk,Popdata,DataCounter,llifoempty)
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begin
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if rising_edge(hclk) then
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if (Push = '1') and (Pop = '0') then
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if DataCounter /= 16 then -- a Push
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-- always increment the data counter if not full
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DataCounter <= DataCounter +1;
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end if;
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end if;
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if (Pop = '1') and (Push = '0') then -- a Pop
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if DataCounter > 0 then
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DataCounter <= DataCounter - 1;
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PopAdd <= PopAdd + 1;
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end if;
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end if;
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if ClearLIFO = '1' then -- a clear lifo
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PopAdd <= (others => '0');
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DataCounter <= (others => '0');
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end if;
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end if; -- clk rise
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if DataCounter = 0 then
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llifoempty <= '1';
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else
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llifoempty <= '0';
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end if;
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end process alifo;
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asimplebiss: process (clk, StartReq2, StartReq1, PopReq2, PopReq1, OldRecvDDSMSB, BISSDataPipe,
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RecvDDSAccum, OldXmitDDSMSB, XmitDDSAccum, DGo, BitPointer, RXSampleTime,
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DataCounter, SyncDAV, poplifo, PopData, llifoempty,hclk, readcontrol0,Readcontrol1,
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Timer,Timers,TimerSelect,BitLengthReg,FilterTimeReg,BitRateDDSReg,PstartMask,
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TStartMask,RGo,XGo)
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begin
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if rising_edge(hclk) then
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-- fi
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BISSDataD <= bissdata;
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if BissDataD = '0' then
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if FilterTime /=0 then
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FilterTime <= FilterTime -1;
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end if;
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else
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if FilterTime /= FilterTimeReg then
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FilterTIme <= FilterTime +1;
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end if;
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end if;
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if FilterTime = 0 then
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FilteredBISSData <= '0';
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end if;
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if FilterTime = FilterTimeReg then
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FilteredBISSData <= '1';
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end if;
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BISSDataPipe <= BISSDataPipe(1 downto 0) & FilteredBISSData; -- Two stage rx data pipeline to compensate for
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-- two clock delay from start bit detection to acquire loop startup
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-- OldBitPointerMSB <= BitPointerMSB;
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if XGo = '1' then
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if XmitClockRE = '1' then
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TestDataSR <= TestDataSR(30 downto 0) & TestDataSR(31);
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end if;
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XmitDDSAccum <= XmitDDSAccum + BitRateDDSReg; -- start clock
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if RGo = '1' then -- RGo means we detected start bit
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RecvDDSAccum <= RecvDDSAccum + BitRateDDSReg;
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if RXSampleTime = '1' then
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if BitCount = 0 then
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RGo <= '0'; -- done with receive
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DAV <= '1';
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else
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if DGo = '1' and RGo = '1' then
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BitCount <= BitCount -1;
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BitPointer <= BitPointer -1;
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SampleToggle <= not SampleToggle;
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end if;
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end if;
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DGo <= '1'; -- data starts 1 bit after start bit
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end if;
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end if;
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else
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XmitDDSAccum <= (others => '0');
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RecvDDSAccum <= (others => '0');
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SampleToggle <= '0';
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TestDataSR <= TestDataConst;
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end if;
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if (RGo = '0') and (DGo = '0') and (BISSDataPipe(0) = '1') and (BISSDataPipe(1)= '0') then -- start bit detection
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RGo <= '1';
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end if;
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if (RGo = '0') and (BitCount = 0) and (XmitClockRE = '1') then --stop xmit clock synchronously
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DGo <= '0';
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XGo <= '0';
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end if;
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OldXmitDDSMSB <= XmitDDSMSB; -- for Phase accumulator MSB edge detection
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OldRecvDDSMSB <= RecvDDSMSB; -- for Phase accumulator MSB edge detection
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-- clock domain crossing control signals
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StartReq2 <= StartReq1;
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if StartReq = '1' then
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StartReq1 <= '1';
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end if;
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PopReq2 <= PopReq1;
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if PopReq = '1' then
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PopReq1 <= '1';
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DAV <= '0'; -- DAV cleared on any reads
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end if;
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if PopReq2 = '1' then
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PopReq1 <= '0';
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end if;
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if (StartReq2 and StartReq1) = '1' then
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BitCount <= BitLengthReg;
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BitPointer <= BitLengthReg(4 downto 0); --5 bit remainder
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XGo <= '1';
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RGo <= '0';
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DGo <= '0';
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StartReq1 <= '0';
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end if;
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end if; -- hclk
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PushBit <= OneOfNDecode(32,DGo,RXSampleTime,BitPointer);
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if (BitPointer = "00001") and (DGo = '1') and (RXSampleTime = '1') then
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Push <= '1';
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else
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Push <= '0';
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end if;
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if (StartReq2 and StartReq1) = '1' then
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ClearLIFO <= '1'; -- always clear data LIFO when starting cycle
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else
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CLearLIFO <= '0';
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end if;
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if (PopReq2 and PopReq1) = '1' then
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Pop <= '1';
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else
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Pop <= '0';
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end if;
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if rising_edge(clk) then
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if loadControl0= '1' then
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BitRateDDSReg <= ibus(31 downto 32-DDSWidth);
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FilterTimeReg <= ibus(32-DDSWidth-1 downto bitlength);
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BitLengthReg <= ibus(BitLength-1 downto 0);
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end if;
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if loadControl1= '1' then
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TimerSelect <= ibus(14 downto 12);
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PstartMask <= ibus(8);
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TstartMask <= ibus(9);
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end if;
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if (lstart = '1') or ((pstart = '1') and (PstartMask = '1')) or ((TStart = '1') and (TStartMask = '1')) then
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StartReq <= '1';
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end if;
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if (Poplifo = '1') then
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PopReq <= '1';
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end if;
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SyncDAV <= DAV;
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OldTimer <= Timer;
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end if; -- clk rising edge
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if Timer = '1' and OldTimer = '0' then -- rising edge of selected timer
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TStart <= '1';
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else
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TStart <= '0';
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end if;
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case TimerSelect(2 downto 0) is
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when "000" => Timer <= timers(0);
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when "001" => Timer <= timers(1);
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when "010" => Timer <= timers(2);
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when "011" => Timer <= timers(3);
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when "100" => Timer <= timers(4);
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when others => Timer <= Timers(0);
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end case;
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if StartReq2 = '1' then
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StartReq <= '0'; -- async clear request
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end if;
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if PopReq2 = '1' then
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PopReq <= '0'; -- async clear request
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end if;
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RXSampleTime <= (not OldRecvDDSMSB) and RecvDDSMSB; -- sample on rising edge of DDS MSB, that is 1/2 cycle from edge
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XmitClockRE <= OldXmitDDSMSB and (not XmitDDSMSB); -- stop xmit clock in idle state
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obus <= (others => 'Z');
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if readcontrol0 = '1' then
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obus(9 downto 0) <= BitLengthReg;
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obus(15 downto 10) <= FilterTimeReg;
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obus(31 downto 32-DDSWidth) <= BitRateDDSReg;
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end if;
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if readcontrol1 = '1' then
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obus(4 downto 0) <= DataCounter;
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obus(7 downto 5) <= (others => '0');
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obus(8) <= PstartMask;
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obus(9) <= TstartMask;
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obus(10) <= RGo;
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obus(11) <= '0';
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obus(14 downto 12) <= TimerSelect;
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obus(15) <= SyncDAV;
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obus(31 downto 16) <= (others => '0');
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end if;
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if poplifo = '1' then
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obus <= PopData;
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end if;
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lifohasdata <= not llifoempty;
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bissclk <= not XmitDDSMSB;
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busyout <= XGo or not SyncDAV;
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davout <= SyncDAV;
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sampletime <= SampleToggle;
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testdata <= TestDataSR(31);
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end process asimplebiss;
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end Behavioral;
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