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This commit is contained in:
Thaddeus-Maximus
129
5i24/configs/hostmot2/source/4i65.ucf
Executable file
129
5i24/configs/hostmot2/source/4i65.ucf
Executable file
@@ -0,0 +1,129 @@
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NET "SYNCLK" LOC = "p185" | IOSTANDARD = LVTTL ;
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# NET "WAITOUT" LOC = "p113" | IOSTANDARD = LVTTL
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NET "LCLK" LOC = "P182" | IOSTANDARD = LVTTL ;
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OFFSET = OUT 24 ns AFTER "LCLK" ;
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OFFSET = IN 19.5 ns BEFORE "LCLK" ;
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NET "ADS" LOC = "p98" | IOSTANDARD = LVTTL ;
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NET "BLAST" LOC = "p99" | IOSTANDARD = LVTTL ;
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NET "INT" LOC = "p112" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
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NET "IOBITS<0>" LOC = "P83" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<10>" LOC = "P67" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<11>" LOC = "P63" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<12>" LOC = "P62" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<13>" LOC = "P61" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<14>" LOC = "P60" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<15>" LOC = "P59" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<16>" LOC = "P58" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<17>" LOC = "P57" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<18>" LOC = "P49" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<19>" LOC = "P48" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<1>" LOC = "P82" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<20>" LOC = "P47" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<21>" LOC = "P46" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<22>" LOC = "P45" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<23>" LOC = "P44" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<24>" LOC = "P8" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<25>" LOC = "P7" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<26>" LOC = "P6" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<27>" LOC = "P5" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<28>" LOC = "P4" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<29>" LOC = "P3" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<2>" LOC = "P81" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<30>" LOC = "P206" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<31>" LOC = "P205" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<32>" LOC = "P204" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<33>" LOC = "P203" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<34>" LOC = "P202" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<35>" LOC = "P201" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<36>" LOC = "P200" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<37>" LOC = "P199" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<38>" LOC = "P195" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<39>" LOC = "P194" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<3>" LOC = "P75" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<40>" LOC = "P193" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<41>" LOC = "P192" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<42>" LOC = "P191" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<43>" LOC = "P189" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<44>" LOC = "P188" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<45>" LOC = "P187" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<46>" LOC = "P181" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<47>" LOC = "P180" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<48>" LOC = "P43" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<49>" LOC = "P42" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<4>" LOC = "P74" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<50>" LOC = "P41" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<51>" LOC = "P37" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<52>" LOC = "P36" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<53>" LOC = "P35" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<54>" LOC = "P34" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<55>" LOC = "P33" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<56>" LOC = "P31" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<57>" LOC = "P30" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<58>" LOC = "P29" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<59>" LOC = "P27" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<5>" LOC = "P73" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<60>" LOC = "P24" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<61>" LOC = "P23" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<62>" LOC = "P22" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<63>" LOC = "P21" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<64>" LOC = "P20" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<65>" LOC = "P18" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<66>" LOC = "P17" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<67>" LOC = "P16" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<68>" LOC = "P15" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<69>" LOC = "P14" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<6>" LOC = "P71" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<70>" LOC = "P10" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<71>" LOC = "P9" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<7>" LOC = "P70" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<8>" LOC = "P69" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<9>" LOC = "P68" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "LAD<0>" LOC = "P153" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<10>" LOC = "P172" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<11>" LOC = "P168" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<12>" LOC = "P167" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<13>" LOC = "P166" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<14>" LOC = "P165" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<15>" LOC = "P164" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<16>" LOC = "P163" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<17>" LOC = "P162" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<18>" LOC = "P152" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<19>" LOC = "P151" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<1>" LOC = "P146" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<20>" LOC = "P150" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<21>" LOC = "P149" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<22>" LOC = "P148" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<23>" LOC = "P147" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<24>" LOC = "P141" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<25>" LOC = "P140" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<26>" LOC = "P139" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<27>" LOC = "P138" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<28>" LOC = "P136" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<29>" LOC = "P134" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<2>" LOC = "P142" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<30>" LOC = "P133" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<31>" LOC = "P132" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
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NET "LAD<3>" LOC = "P135" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<4>" LOC = "P126" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<5>" LOC = "P119" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<6>" LOC = "P115" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<7>" LOC = "P108" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<8>" LOC = "P174" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LAD<9>" LOC = "P173" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
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NET "LEDS<0>" LOC = "P84" | SLEW = SLOW | DRIVE = 24 | IOSTANDARD = LVTTL ;
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NET "LEDS<1>" LOC = "P86" | SLEW = SLOW | DRIVE = 24 | IOSTANDARD = LVTTL ;
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NET "LEDS<2>" LOC = "P87" | SLEW = SLOW | DRIVE = 24 | IOSTANDARD = LVTTL ;
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NET "LEDS<3>" LOC = "P88" | SLEW = SLOW | DRIVE = 24 | IOSTANDARD = LVTTL ;
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NET "LEDS<4>" LOC = "P89" | SLEW = SLOW | DRIVE = 24 | IOSTANDARD = LVTTL ;
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NET "LEDS<5>" LOC = "P90" | SLEW = SLOW | DRIVE = 24 | IOSTANDARD = LVTTL ;
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NET "LEDS<6>" LOC = "P94" | SLEW = SLOW | DRIVE = 24 | IOSTANDARD = LVTTL ;
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NET "LEDS<7>" LOC = "P95" | SLEW = SLOW | DRIVE = 24 | IOSTANDARD = LVTTL ;
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NET "LW_R" LOC = "P101" | IOSTANDARD = LVTTL ;
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NET "READY" LOC = "P102" | IOSTANDARD = LVTTL | SLEW = FAST ;
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INST "*CLKDLL_inst3" LOC = "DLL3"; # 50 MHz synclk clock multx2
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INST "*BUFG_inst3" LOC = "GCLKBUF3"; # 100 Mhz buffer = PWM clock
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INST "*BUFG_inst1" LOC = "GCLKBUF1"; # 50 MHz buffer = processor clock
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#NET "LCLK" TNM_NET = "LCLK";
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#TIMESPEC "TS_LCLK" = PERIOD "LCLK" 33 ns HIGH 50 %;
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#NET "SYNCLK" TNM_NET = "SYNCLK";
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#TIMESPEC "TS_SYNCLK" = PERIOD "SYNCLK" 20 ns HIGH 50 %;
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132
5i24/configs/hostmot2/source/4i65ss.ucf
Executable file
132
5i24/configs/hostmot2/source/4i65ss.ucf
Executable file
@@ -0,0 +1,132 @@
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NET "SYNCLK" LOC = "p185" | IOSTANDARD = LVTTL ;
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# NET "WAITOUT" LOC = "p113" | IOSTANDARD = LVTTL
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NET "LCLK" LOC = "P182" | IOSTANDARD = LVTTL ;
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OFFSET = OUT 24 ns AFTER "LCLK" ;
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OFFSET = IN 19.5 ns BEFORE "LCLK" ;
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NET "ADS" LOC = "p98" | IOSTANDARD = LVTTL ;
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NET "BLAST" LOC = "p99" | IOSTANDARD = LVTTL ;
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NET "INT" LOC = "p112" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
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NET "IOBITS<0>" LOC = "P83" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<10>" LOC = "P67" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<11>" LOC = "P63" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<12>" LOC = "P62" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<13>" LOC = "P61" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<14>" LOC = "P60" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<15>" LOC = "P59" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<16>" LOC = "P58" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<17>" LOC = "P57" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<18>" LOC = "P49" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<19>" LOC = "P48" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<1>" LOC = "P82" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<20>" LOC = "P47" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<21>" LOC = "P46" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<22>" LOC = "P45" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<23>" LOC = "P44" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<24>" LOC = "P8" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<25>" LOC = "P7" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<26>" LOC = "P6" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<27>" LOC = "P5" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<28>" LOC = "P4" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<29>" LOC = "P3" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<2>" LOC = "P81" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<30>" LOC = "P206" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<31>" LOC = "P205" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<32>" LOC = "P204" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<33>" LOC = "P203" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<34>" LOC = "P202" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<35>" LOC = "P201" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<36>" LOC = "P200" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<37>" LOC = "P199" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<38>" LOC = "P195" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<39>" LOC = "P194" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<3>" LOC = "P75" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<40>" LOC = "P193" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<41>" LOC = "P192" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<42>" LOC = "P191" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<43>" LOC = "P189" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<44>" LOC = "P188" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<45>" LOC = "P187" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<46>" LOC = "P181" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<47>" LOC = "P180" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<48>" LOC = "P43" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<49>" LOC = "P42" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<4>" LOC = "P74" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<50>" LOC = "P41" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<51>" LOC = "P37" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<52>" LOC = "P36" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<53>" LOC = "P35" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<54>" LOC = "P34" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<55>" LOC = "P33" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<56>" LOC = "P31" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<57>" LOC = "P30" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<58>" LOC = "P29" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<59>" LOC = "P27" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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NET "IOBITS<5>" LOC = "P73" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
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||||
NET "IOBITS<60>" LOC = "P24" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
|
||||
NET "IOBITS<61>" LOC = "P23" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
|
||||
NET "IOBITS<62>" LOC = "P22" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
|
||||
NET "IOBITS<63>" LOC = "P21" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
|
||||
NET "IOBITS<64>" LOC = "P20" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
|
||||
NET "IOBITS<65>" LOC = "P18" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
|
||||
NET "IOBITS<66>" LOC = "P17" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
|
||||
NET "IOBITS<67>" LOC = "P16" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
|
||||
NET "IOBITS<68>" LOC = "P15" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
|
||||
NET "IOBITS<69>" LOC = "P14" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
|
||||
NET "IOBITS<6>" LOC = "P71" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
|
||||
NET "IOBITS<70>" LOC = "P10" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
|
||||
NET "IOBITS<71>" LOC = "P9" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
|
||||
NET "IOBITS<7>" LOC = "P70" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
|
||||
NET "IOBITS<8>" LOC = "P69" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
|
||||
NET "IOBITS<9>" LOC = "P68" | SLEW = SLOW | IOSTANDARD = LVTTL | DRIVE = 24 ;
|
||||
NET "LAD<0>" LOC = "P153" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<10>" LOC = "P172" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<11>" LOC = "P168" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<12>" LOC = "P167" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<13>" LOC = "P166" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<14>" LOC = "P165" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<15>" LOC = "P164" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<16>" LOC = "P163" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<17>" LOC = "P162" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<18>" LOC = "P152" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<19>" LOC = "P151" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<1>" LOC = "P146" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<20>" LOC = "P150" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<21>" LOC = "P149" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<22>" LOC = "P148" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<23>" LOC = "P147" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<24>" LOC = "P141" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<25>" LOC = "P140" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<26>" LOC = "P139" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<27>" LOC = "P138" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<28>" LOC = "P136" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<29>" LOC = "P134" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<2>" LOC = "P142" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<30>" LOC = "P133" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<31>" LOC = "P132" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<3>" LOC = "P135" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<4>" LOC = "P126" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<5>" LOC = "P119" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<6>" LOC = "P115" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<7>" LOC = "P108" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<8>" LOC = "P174" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LAD<9>" LOC = "P173" | SLEW = FAST | IOSTANDARD = LVTTL | DRIVE = 8 ;
|
||||
NET "LEDS<0>" LOC = "P84" | SLEW = SLOW | DRIVE = 24 | IOSTANDARD = LVTTL ;
|
||||
NET "LEDS<1>" LOC = "P86" | SLEW = SLOW | DRIVE = 24 | IOSTANDARD = LVTTL ;
|
||||
NET "LEDS<2>" LOC = "P87" | SLEW = SLOW | DRIVE = 24 | IOSTANDARD = LVTTL ;
|
||||
NET "LEDS<3>" LOC = "P88" | SLEW = SLOW | DRIVE = 24 | IOSTANDARD = LVTTL ;
|
||||
NET "LEDS<4>" LOC = "P89" | SLEW = SLOW | DRIVE = 24 | IOSTANDARD = LVTTL ;
|
||||
NET "LEDS<5>" LOC = "P90" | SLEW = SLOW | DRIVE = 24 | IOSTANDARD = LVTTL ;
|
||||
NET "LEDS<6>" LOC = "P94" | SLEW = SLOW | DRIVE = 24 | IOSTANDARD = LVTTL ;
|
||||
NET "LEDS<7>" LOC = "P95" | SLEW = SLOW | DRIVE = 24 | IOSTANDARD = LVTTL ;
|
||||
NET "LW_R" LOC = "P101" | IOSTANDARD = LVTTL ;
|
||||
NET "READY" LOC = "P102" | IOSTANDARD = LVTTL | SLEW = FAST ;
|
||||
INST "*CLKDLL_inst3" LOC = "DLL3"; # 50 MHz synclk clock multx2
|
||||
INST "*BUFG_inst3" LOC = "GCLKBUF3"; # 100 Mhz buffer = PWM clock
|
||||
INST "*BUFG_inst1" LOC = "GCLKBUF1"; # 50 MHz buffer = processor clock
|
||||
#PACE: Start of PACE Area Constraints
|
||||
#PACE: Start of PACE Prohibit Constraints
|
||||
#PACE: End of Constraints generated by PACE
|
||||
NET "LCLK" TNM_NET = "LCLK";
|
||||
TIMESPEC "TS_LCLK" = PERIOD "LCLK" 33 ns HIGH 50 %;
|
||||
NET "SYNCLK" TNM_NET = "SYNCLK";
|
||||
TIMESPEC "TS_SYNCLK" = PERIOD "SYNCLK" 20 ns HIGH 50 %;
|
||||
171
5i24/configs/hostmot2/source/4i68.ucf
Executable file
171
5i24/configs/hostmot2/source/4i68.ucf
Executable file
@@ -0,0 +1,171 @@
|
||||
OFFSET = IN 10 ns BEFORE "LCLK" ;
|
||||
INST "LAD<0>" TNM = "lad";
|
||||
INST "LAD<1>" TNM = "lad";
|
||||
INST "LAD<2>" TNM = "lad";
|
||||
INST "LAD<3>" TNM = "lad";
|
||||
INST "LAD<4>" TNM = "lad";
|
||||
INST "LAD<5>" TNM = "lad";
|
||||
INST "LAD<6>" TNM = "lad";
|
||||
INST "LAD<7>" TNM = "lad";
|
||||
INST "LAD<8>" TNM = "lad";
|
||||
INST "LAD<9>" TNM = "lad";
|
||||
INST "LAD<10>" TNM = "lad";
|
||||
INST "LAD<11>" TNM = "lad";
|
||||
INST "LAD<12>" TNM = "lad";
|
||||
INST "LAD<13>" TNM = "lad";
|
||||
INST "LAD<14>" TNM = "lad";
|
||||
INST "LAD<15>" TNM = "lad";
|
||||
INST "LAD<16>" TNM = "lad";
|
||||
INST "LAD<17>" TNM = "lad";
|
||||
INST "LAD<18>" TNM = "lad";
|
||||
INST "LAD<19>" TNM = "lad";
|
||||
INST "LAD<20>" TNM = "lad";
|
||||
INST "LAD<21>" TNM = "lad";
|
||||
INST "LAD<22>" TNM = "lad";
|
||||
INST "LAD<23>" TNM = "lad";
|
||||
INST "LAD<24>" TNM = "lad";
|
||||
INST "LAD<25>" TNM = "lad";
|
||||
INST "LAD<26>" TNM = "lad";
|
||||
INST "LAD<27>" TNM = "lad";
|
||||
INST "LAD<28>" TNM = "lad";
|
||||
INST "LAD<29>" TNM = "lad";
|
||||
INST "LAD<30>" TNM = "lad";
|
||||
INST "LAD<31>" TNM = "lad";
|
||||
TIMEGRP "lad" OFFSET = IN 10 ns BEFORE "LCLK" ;
|
||||
#NET "DACK" LOC = "P36" | IOSTANDARD = LVCMOS33 | PULLUP
|
||||
#NET "DEN" LOC = "P57" | PULLUP | IOSTANDARD = LVCMOS33
|
||||
NET "DREQ" LOC = "P37" | IOSTANDARD = LVCMOS33 | PULLUP;
|
||||
NET "BLAST" OFFSET = IN 8.5 ns BEFORE "LCLK" HIGH ;
|
||||
NET "LW_R" OFFSET = IN 8 ns BEFORE "LCLK" HIGH ;
|
||||
# NET "HOLDA" OFFSET = OUT 13 ns AFTER "LCLK" HIGH
|
||||
NET "READY" OFFSET = OUT 11.5 ns AFTER "LCLK" HIGH ;
|
||||
#PACE: Start of Constraints generated by PACE
|
||||
#PACE: Start of PACE I/O Pin Assignments
|
||||
NET "ADS" LOC = "P46" | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "BLAST" LOC = "P44" | IOSTANDARD = LVCMOS33 | PULLUP ;
|
||||
# NET "CCS" IOSTANDARD = LVCMOS33
|
||||
NET "DISABLECONF" LOC = "P200" | IOSTANDARD = LVCMOS33 | PULLDOWN | SLEW = SLOW ;
|
||||
NET "HOLD" LOC = "P50" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "HOLDA" LOC = "P48" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST ;
|
||||
NET "INT" LOC = "P39" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12 ;
|
||||
NET "IOBITS<0>" LOC = "P35" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<10>" LOC = "P21" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<11>" LOC = "P20" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<12>" LOC = "P19" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<13>" LOC = "P18" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<14>" LOC = "P16" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<15>" LOC = "P15" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<16>" LOC = "P13" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<17>" LOC = "P12" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<18>" LOC = "P11" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<19>" LOC = "P10" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<1>" LOC = "P34" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<20>" LOC = "P9" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<21>" LOC = "P7" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<22>" LOC = "P5" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<23>" LOC = "P4" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<24>" LOC = "P154" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<25>" LOC = "P152" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<26>" LOC = "P150" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<27>" LOC = "P149" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<28>" LOC = "P148" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<29>" LOC = "P147" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<2>" LOC = "P33" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<30>" LOC = "P146" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<31>" LOC = "P144" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<32>" LOC = "P143" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<33>" LOC = "P141" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<34>" LOC = "P140" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<35>" LOC = "P139" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<36>" LOC = "P138" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<37>" LOC = "P137" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<38>" LOC = "P135" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<39>" LOC = "P133" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<3>" LOC = "P31" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<40>" LOC = "P132" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<41>" LOC = "P131" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<42>" LOC = "p130" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<43>" LOC = "P128" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<44>" LOC = "P126" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<45>" LOC = "P125" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<46>" LOC = "P124" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<47>" LOC = "P123" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<48>" LOC = "P199" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<49>" LOC = "P198" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<4>" LOC = "P29" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<50>" LOC = "P196" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<51>" LOC = "P194" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<52>" LOC = "P191" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<53>" LOC = "P190" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<54>" LOC = "P187" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<55>" LOC = "P185" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<56>" LOC = "P184" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<57>" LOC = "P183" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<58>" LOC = "P181" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<59>" LOC = "P180" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<5>" LOC = "P28" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<60>" LOC = "P178" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<61>" LOC = "P176" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<62>" LOC = "P172" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<63>" LOC = "P171" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<64>" LOC = "P169" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<65>" LOC = "P168" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<66>" LOC = "P166" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<67>" LOC = "P165" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<68>" LOC = "P189" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<69>" LOC = "P182" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<6>" LOC = "P27" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<70>" LOC = "P175" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<71>" LOC = "P167" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<7>" LOC = "P26" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<8>" LOC = "P24" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<9>" LOC = "P22" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "LAD<0>" LOC = "P92" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<10>" LOC = "P64" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<11>" LOC = "P65" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<12>" LOC = "P71" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<13>" LOC = "P76" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<14>" LOC = "P78" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<15>" LOC = "P79" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<16>" LOC = "P80" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<17>" LOC = "P85" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<18>" LOC = "P93" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<19>" LOC = "P94" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<1>" LOC = "P90" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<20>" LOC = "P95" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<21>" LOC = "P96" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<22>" LOC = "P97" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<23>" LOC = "P100" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<24>" LOC = "P101" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<25>" LOC = "P102" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<26>" LOC = "P108" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<27>" LOC = "P109" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<28>" LOC = "P111" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<29>" LOC = "P113" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<2>" LOC = "P87" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<30>" LOC = "P114" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<31>" LOC = "P115" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<3>" LOC = "P86" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<4>" LOC = "P74" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<5>" LOC = "P72" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<6>" LOC = "P68" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<7>" LOC = "P67" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<8>" LOC = "P62" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<9>" LOC = "P63" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LCLK" LOC = "P77" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "LEDS<0>" LOC = "P83" | SLEW = SLOW | IOSTANDARD = LVCMOS33 | DRIVE = 24 ;
|
||||
NET "LEDS<1>" LOC = "P81" | SLEW = SLOW | IOSTANDARD = LVCMOS33 | DRIVE = 24 ;
|
||||
NET "LEDS<2>" LOC = "P205" | SLEW = SLOW | IOSTANDARD = LVCMOS33 | DRIVE = 24 ;
|
||||
NET "LEDS<3>" LOC = "P197" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 24 ;
|
||||
NET "LW_R" LOC = "P122" | IOSTANDARD = LVCMOS33 | PULLUP ;
|
||||
NET "READY" LOC = "P58" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ;
|
||||
NET "BTERM" LOC = "P61" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ;
|
||||
#PACE: Start of PACE Area Constraints
|
||||
#PACE: Start of PACE Prohibit Constraints
|
||||
#PACE: End of Constraints generated by PACE
|
||||
NET "LCLK" TNM_NET = "LCLK";
|
||||
TIMESPEC "TS_LCLK" = PERIOD "LCLK" 20 ns HIGH 50 %;
|
||||
NET "clkfx1" TNM_NET = "async_med"; # For async sserial processor
|
||||
NET "LCLK" TNM_NET = "async_low";
|
||||
TIMESPEC "TSLowToMed" = FROM "async_low" to "async_med" TIG;
|
||||
TIMESPEC "TSMedtoLow" = FROM "async_med" to "async_low" TIG;
|
||||
278
5i24/configs/hostmot2/source/4i69.ucf
Executable file
278
5i24/configs/hostmot2/source/4i69.ucf
Executable file
@@ -0,0 +1,278 @@
|
||||
OFFSET = OUT 20 ns AFTER "LCLK" ;
|
||||
OFFSET = IN 20 ns BEFORE "LCLK" ;
|
||||
TIMESPEC "TS_LCLK" = PERIOD "LCLK" 19.5 ns HIGH 50 %;
|
||||
NET "BLAST" OFFSET = IN 8.5 ns BEFORE "LCLK" HIGH ;
|
||||
NET "LW_R" OFFSET = IN 8 ns BEFORE "LCLK" HIGH ;
|
||||
NET "READY" OFFSET = OUT 11.5 ns AFTER "LCLK" HIGH ;
|
||||
TIMEGRP "lad" OFFSET = OUT 13.5 ns AFTER "LCLK" HIGH ;
|
||||
TIMEGRP "lad" OFFSET = IN 9 ns BEFORE "LCLK" HIGH ;
|
||||
INST "LAD<0>" TNM = "lad";
|
||||
INST "LAD<1>" TNM = "lad";
|
||||
INST "LAD<2>" TNM = "lad";
|
||||
INST "LAD<3>" TNM = "lad";
|
||||
INST "LAD<4>" TNM = "lad";
|
||||
INST "LAD<5>" TNM = "lad";
|
||||
INST "LAD<6>" TNM = "lad";
|
||||
INST "LAD<7>" TNM = "lad";
|
||||
INST "LAD<8>" TNM = "lad";
|
||||
INST "LAD<9>" TNM = "lad";
|
||||
INST "LAD<10>" TNM = "lad";
|
||||
INST "LAD<11>" TNM = "lad";
|
||||
INST "LAD<12>" TNM = "lad";
|
||||
INST "LAD<13>" TNM = "lad";
|
||||
INST "LAD<14>" TNM = "lad";
|
||||
INST "LAD<15>" TNM = "lad";
|
||||
INST "LAD<16>" TNM = "lad";
|
||||
INST "LAD<17>" TNM = "lad";
|
||||
INST "LAD<18>" TNM = "lad";
|
||||
INST "LAD<19>" TNM = "lad";
|
||||
INST "LAD<20>" TNM = "lad";
|
||||
INST "LAD<21>" TNM = "lad";
|
||||
INST "LAD<22>" TNM = "lad";
|
||||
INST "LAD<23>" TNM = "lad";
|
||||
INST "LAD<24>" TNM = "lad";
|
||||
INST "LAD<25>" TNM = "lad";
|
||||
INST "LAD<26>" TNM = "lad";
|
||||
INST "LAD<27>" TNM = "lad";
|
||||
INST "LAD<28>" TNM = "lad";
|
||||
INST "LAD<29>" TNM = "lad";
|
||||
INST "LAD<30>" TNM = "lad";
|
||||
INST "LAD<31>" TNM = "lad";
|
||||
NET "/ADS" LOC = "T4" | IOSTANDARD = LVTTL ; # Bank2 63N
|
||||
NET "/BLAST" LOC = "R1" | IOSTANDARD = LVTTL ; # Bank3 32N_M3DQ15
|
||||
NET "/BTERM" LOC = "P6" | IOSTANDARD = LVTTL ; # Bank2 47P
|
||||
NET "/CCS" LOC = "M4" | IOSTANDARD = LVTTL ; # Bank3 1P
|
||||
NET "/DREQ" LOC = "M1" | IOSTANDARD = LVTTL ; # Bank3 35N_M3DQ11
|
||||
NET "/INT" LOC = "N4" | IOSTANDARD = LVTTL ; # Bank3 2N
|
||||
NET "/READY" LOC = "T6" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank2 47N
|
||||
NET "LCLK" LOC = "M9" | IOSTANDARD = LVTTL ; # Bank2 29P_C3
|
||||
NET "DISABLECONF" LOC = "G5" | IOSTANDARD = LVTTL | SLEW = SLOW ; # Bank3 51N_M3A4
|
||||
NET "IOBITS<0>" LOC = "H5" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank3 43N_C22_M3CAS
|
||||
NET "IOBITS<10>" LOC = "F1" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank3 41N_C26_M3DQ5
|
||||
NET "IOBITS<11>" LOC = "F2" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank3 41P_C27_M3DQ4
|
||||
NET "IOBITS<12>" LOC = "F3" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank3 53N_M3A12
|
||||
NET "IOBITS<13>" LOC = "F4" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank3 53P_M3CKE
|
||||
NET "IOBITS<14>" LOC = "E1" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank3 46N_M3CLKN
|
||||
NET "IOBITS<15>" LOC = "E2" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank3 46P_M3CLK
|
||||
NET "IOBITS<16>" LOC = "E3" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank3 54N_M3A11
|
||||
NET "IOBITS<17>" LOC = "E4" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank3 54P_M3RESET
|
||||
NET "IOBITS<18>" LOC = "D1" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank3 49N_M3A2
|
||||
NET "IOBITS<19>" LOC = "D3" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank3 49P_M3A7
|
||||
NET "IOBITS<1>" LOC = "J6" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank3 43P_C23_M3RAS
|
||||
NET "IOBITS<20>" LOC = "B1" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank3 50N_M3BA2
|
||||
NET "IOBITS<21>" LOC = "C1" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank3 50P_M3WE
|
||||
NET "IOBITS<22>" LOC = "C2" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank3 48N_M3BA1
|
||||
NET "IOBITS<23>" LOC = "C3" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank3 48P_M3BA0
|
||||
NET "IOBITS<24>" LOC = "J16" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank1 43N_C4_M1DQ5
|
||||
NET "IOBITS<25>" LOC = "J14" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank1 43P_C5_M1DQ4
|
||||
NET "IOBITS<26>" LOC = "B16" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank1 29N_A22_M1A14
|
||||
NET "IOBITS<27>" LOC = "B15" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank1 29P_A23_M1A13
|
||||
NET "IOBITS<28>" LOC = "C16" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank1 33N_A14_M1A4
|
||||
NET "IOBITS<29>" LOC = "C15" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank1 33P_A15_M1A10
|
||||
NET "IOBITS<2>" LOC = "J1" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank3 38N_M3DQ3
|
||||
NET "IOBITS<30>" LOC = "D16" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank1 31N_A18_M1A12
|
||||
NET "IOBITS<31>" LOC = "D14" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank1 31P_A19_M1CKE
|
||||
NET "IOBITS<32>" LOC = "E16" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank1 34N_A12_M1BA2
|
||||
NET "IOBITS<33>" LOC = "E15" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank1 34P_A13_M1WE
|
||||
NET "IOBITS<34>" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank1 1N_A24_VREF
|
||||
NET "IOBITS<35>" LOC = "E13" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank1 1P_A25
|
||||
NET "IOBITS<36>" LOC = "F16" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank1 35N_A10_M1A2
|
||||
NET "IOBITS<37>" LOC = "F15" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank1 35P_A11_M1A7
|
||||
NET "IOBITS<38>" LOC = "F14" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank1 32N_A16_M1A9
|
||||
NET "IOBITS<39>" LOC = "F13" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank1 32P_A17_M1A8
|
||||
NET "IOBITS<3>" LOC = "J3" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank3 38P_M3DQ2
|
||||
NET "IOBITS<40>" LOC = "G16" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank1 36N_A8_M1BA1
|
||||
NET "IOBITS<41>" LOC = "G14" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank1 36P_A9_M1BA0
|
||||
NET "IOBITS<42>" LOC = "H16" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank1 37N_A6_M1A1
|
||||
NET "IOBITS<43>" LOC = "H15" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank1 37P_A7_M1A0
|
||||
NET "IOBITS<44>" LOC = "H14" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank1 39N_M1ODT
|
||||
NET "IOBITS<45>" LOC = "H13" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank1 39P_M1A3
|
||||
NET "IOBITS<46>" LOC = "K14" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank1 41N_C8_M1CAS
|
||||
NET "IOBITS<47>" LOC = "J13" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank1 41P_C9_M1RAS
|
||||
NET "IOBITS<48>" LOC = "E8" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank0 36N_C14
|
||||
NET "IOBITS<49>" LOC = "E7" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank0 36P_C15
|
||||
NET "IOBITS<4>" LOC = "H1" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank3 39N_M3LDQSN
|
||||
NET "IOBITS<50>" LOC = "A5" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank0 2N
|
||||
NET "IOBITS<51>" LOC = "B5" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank0 2P
|
||||
NET "IOBITS<52>" LOC = "C5" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank0 3N
|
||||
NET "IOBITS<53>" LOC = "D5" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank0 3P
|
||||
NET "IOBITS<54>" LOC = "A6" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank0 4N
|
||||
NET "IOBITS<55>" LOC = "B6" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank0 4P
|
||||
NET "IOBITS<56>" LOC = "A7" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank0 6N
|
||||
NET "IOBITS<57>" LOC = "C7" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank0 6P
|
||||
NET "IOBITS<58>" LOC = "A8" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank0 33N
|
||||
NET "IOBITS<59>" LOC = "B8" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank0 33P
|
||||
NET "IOBITS<5>" LOC = "H2" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank3 39P_M3LDQS
|
||||
NET "IOBITS<60>" LOC = "A9" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank0 34N_C18
|
||||
NET "IOBITS<61>" LOC = "C9" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank0 34P_C19
|
||||
NET "IOBITS<62>" LOC = "A10" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank0 35N_C16
|
||||
NET "IOBITS<63>" LOC = "B10" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank0 35P_C17
|
||||
NET "IOBITS<64>" LOC = "A11" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank0 39N
|
||||
NET "IOBITS<65>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank0 39P
|
||||
NET "IOBITS<66>" LOC = "A12" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank0 62N_VREF
|
||||
NET "IOBITS<67>" LOC = "B12" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank0 62P
|
||||
NET "IOBITS<68>" LOC = "A13" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank0 63N_SCP6
|
||||
NET "IOBITS<69>" LOC = "C13" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank0 63P_SCP7
|
||||
NET "IOBITS<6>" LOC = "H3" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank3 44N_C20_M3A6
|
||||
NET "IOBITS<70>" LOC = "A14" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank0 65N_SCP2
|
||||
NET "IOBITS<71>" LOC = "B14" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank0 65P_SCP3
|
||||
NET "IOBITS<7>" LOC = "H4" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank3 44P_C21_M3A5
|
||||
NET "IOBITS<8>" LOC = "G1" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank3 40N_M3DQ7
|
||||
NET "IOBITS<9>" LOC = "G3" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP ; # Bank3 40P_M3DQ6
|
||||
NET "LAD<0>" LOC = "P10" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank2 3P_D0_MISO1
|
||||
NET "LAD<10>" LOC = "T8" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank2 30N_C0_USRCC
|
||||
NET "LAD<11>" LOC = "P8" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank2 30P_C1_D13
|
||||
NET "LAD<12>" LOC = "N8" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank2 29N_C2
|
||||
NET "LAD<13>" LOC = "P9" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank2 14N_D12
|
||||
NET "LAD<14>" LOC = "N9" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank2 14P_D11
|
||||
NET "LAD<15>" LOC = "T9" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank2 23N
|
||||
NET "LAD<16>" LOC = "R9" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank2 23P
|
||||
NET "LAD<17>" LOC = "P11" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank2 13N_D10
|
||||
NET "LAD<18>" LOC = "T12" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank1 52N_M1DQ15
|
||||
NET "LAD<19>" LOC = "R12" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank1 52P_M1DQ14
|
||||
NET "LAD<1>" LOC = "N12" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank2 12P_D1_MISO2
|
||||
NET "LAD<20>" LOC = "T13" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank1 51N_M1DQ13
|
||||
NET "LAD<21>" LOC = "T14" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank1 51P_M1DQ12
|
||||
NET "LAD<22>" LOC = "T15" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank1 50N_M1UDQSN
|
||||
NET "LAD<23>" LOC = "R14" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank1 50P_M1UDQS
|
||||
NET "LAD<24>" LOC = "R16" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank1 49N_M1DQ11
|
||||
NET "LAD<25>" LOC = "R15" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank1 49P_M1DQ10
|
||||
NET "LAD<26>" LOC = "P16" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank1 48N_M1DQ9
|
||||
NET "LAD<27>" LOC = "P15" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank1 48P_HDC_M1DQ8
|
||||
NET "LAD<28>" LOC = "N16" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank1 45N_A0_M1LDQS
|
||||
NET "LAD<29>" LOC = "N14" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank1 45P_A1_M1LDQS
|
||||
NET "LAD<2>" LOC = "P12" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank2 12N_D2_MISO3
|
||||
NET "LAD<30>" LOC = "M14" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank1 74N_DOUT_BUS
|
||||
NET "LAD<31>" LOC = "M13" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank1 74P_AWAKE
|
||||
NET "LAD<3>" LOC = "N5" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank2 49P_D3
|
||||
NET "LAD<4>" LOC = "P5" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank2 49N_D4
|
||||
NET "LAD<5>" LOC = "L8" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank2 62P_D5
|
||||
NET "LAD<6>" LOC = "L7" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank2 62N_D6
|
||||
NET "LAD<7>" LOC = "R5" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank2 48P_D7
|
||||
NET "LAD<8>" LOC = "T7" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank2 32N_C28
|
||||
NET "LAD<9>" LOC = "R7" | IOSTANDARD = LVTTL | SLEW = FAST ; # Bank2 32P_C29
|
||||
NET "LEDS<0>" LOC = "J4" | IOSTANDARD = LVTTL | SLEW = SLOW ; # Bank3 42N_C24_M3LDM
|
||||
NET "LEDS<1>" LOC = "K3" | IOSTANDARD = LVTTL | SLEW = SLOW ; # Bank3 42P_C25_M3UDM
|
||||
NET "LEDS<2>" LOC = "K1" | IOSTANDARD = LVTTL | SLEW = SLOW ; # Bank3 37N_M3DQ1
|
||||
NET "LEDS<3>" LOC = "K2" | IOSTANDARD = LVTTL | SLEW = SLOW ; # Bank3 37P_M3DQ0
|
||||
NET "LEDS<4>" LOC = "L4" | IOSTANDARD = LVTTL | SLEW = SLOW ; # Bank3 45P_M3A3
|
||||
NET "LEDS<5>" LOC = "L1" | IOSTANDARD = LVTTL | SLEW = SLOW ; # Bank3 36N_M3DQ9
|
||||
NET "LEDS<6>" LOC = "L3" | IOSTANDARD = LVTTL | SLEW = SLOW ; # Bank3 36P_M3DQ8
|
||||
NET "LEDS<7>" LOC = "M3" | IOSTANDARD = LVTTL | SLEW = SLOW ; # Bank3 1N_VREF
|
||||
NET "HOLD" LOC = "N6" | IOSTANDARD = LVTTL ; # Bank2 64N_D9
|
||||
NET "HOLDA" LOC = "P4" | IOSTANDARD = LVTTL ; # Bank2 63P
|
||||
NET "LW_R" LOC = "L14" | IOSTANDARD = LVTTL ; # Bank1 47P_FWE_M1DQ0
|
||||
NET "LIOBITS<0>" LOC = "F5" | IOSTANDARD = LVTTL | SLEW = SLOW ; # Bank3 55N_M3A14 Analog PS drive
|
||||
NET "LIOBITS<1>" LOC = "B3" | IOSTANDARD = LVTTL | SLEW = SLOW ; # Bank3 83P A-D SPI /CS
|
||||
NET "LIOBITS<2>" LOC = "A3" | IOSTANDARD = LVTTL | SLEW = SLOW ; # Bank3 83N_VREF A-D SPI CLK
|
||||
NET "LIOBITS<3>" LOC = "A2" | IOSTANDARD = LVTTL | SLEW = SLOW ; # Bank3 52N_M3A9 A-D SPI out
|
||||
NET "LIOBITS<4>" LOC = "B2" | IOSTANDARD = LVTTL | SLEW = SLOW | PULLUP; # Bank3 52P_M3A8 A-D SPI in
|
||||
|
||||
#NET "/DACK" LOC = "M2" | IOSTANDARD = LVTTL ; # Bank3 35P_M3DQ10
|
||||
#NET "/DEN" LOC = "K15" | IOSTANDARD = LVTTL ; # Bank1 44P_A3_M1DQ6
|
||||
#NET "/LBE<0>" LOC = "M16" | IOSTANDARD = LVTTL ; # Bank1 46N_FOE_M1DQ3
|
||||
#NET "/LBE<1>" LOC = "M15" | IOSTANDARD = LVTTL ; # Bank1 46P_FCS_M1DQ2
|
||||
#NET "/LBE<2>" LOC = "L16" | IOSTANDARD = LVTTL ; # Bank1 47N_LDC_M1DQ1
|
||||
#NET "/LBE<3>" LOC = "L13" | IOSTANDARD = LVTTL ; # Bank1 53N_VREF
|
||||
#NET "/RESET" LOC = "N3" | IOSTANDARD = LVTTL ; # Bank3 34P_M3UDQS
|
||||
#NET "/WAIT" LOC = "P1" | IOSTANDARD = LVTTL ; # Bank3 33N_M3DQ13
|
||||
#NET "ALE" LOC = "K16" | IOSTANDARD = LVTTL ; # Bank1 44N_A2_M1DQ7
|
||||
#NET "CCLK" LOC = "R11" | IOSTANDARD = LVTTL ; # Bank2 1P_CCLK
|
||||
#NET "DMPAF" LOC = "N1" | IOSTANDARD = LVTTL ; # Bank3 34N_M3UDQSN
|
||||
#NET "DONE" LOC = "P13" | IOSTANDARD = LVTTL ; # Bank2 ONE
|
||||
#NET "/LSERR" LOC = "R2" | IOSTANDARD = LVTTL ; # Bank3 32P_M3DQ14
|
||||
#NET "/PROGRAM" LOC = "T2" | IOSTANDARD = LVTTL ; # Bank2 ROGRAM_B
|
||||
#NET "BREQO" LOC = "P2" | IOSTANDARD = LVTTL ; # Bank3 33P_M3DQ12
|
||||
#NET "NC" LOC = "A1" | IOSTANDARD = LVTTL ; # Bank5 ND
|
||||
#NET "NC" LOC = "A16" | IOSTANDARD = LVTTL ; # Bank5 ND
|
||||
#NET "NC" LOC = "A4" | IOSTANDARD = LVTTL ; # Bank0 1N_VREF
|
||||
#NET "NC" LOC = "B11" | IOSTANDARD = LVTTL ; # Bank5 ND
|
||||
#NET "NC" LOC = "B7" | IOSTANDARD = LVTTL ; # Bank5 ND
|
||||
#NET "NC" LOC = "C10" | IOSTANDARD = LVTTL ; # Bank0 37N_C12
|
||||
#NET "NC" LOC = "C6" | IOSTANDARD = LVTTL ; # Bank0 7N
|
||||
#NET "NC" LOC = "C8" | IOSTANDARD = LVTTL ; # Bank0 38N_VREF
|
||||
#NET "NC" LOC = "D11" | IOSTANDARD = LVTTL ; # Bank0 66P_SCP1
|
||||
#NET "NC" LOC = "D12" | IOSTANDARD = LVTTL ; # Bank0 66N_SCP0
|
||||
#NET "NC" LOC = "D13" | IOSTANDARD = LVTTL ; # Bank5 ND
|
||||
#NET "NC" LOC = "D4" | IOSTANDARD = LVTTL ; # Bank5 ND
|
||||
#NET "NC" LOC = "D6" | IOSTANDARD = LVTTL ; # Bank0 7P
|
||||
#NET "NC" LOC = "D8" | IOSTANDARD = LVTTL ; # Bank0 38P
|
||||
#NET "NC" LOC = "D9" | IOSTANDARD = LVTTL ; # Bank0 40N
|
||||
#NET "NC" LOC = "E10" | IOSTANDARD = LVTTL ; # Bank0 37P_C13
|
||||
#NET "NC" LOC = "E11" | IOSTANDARD = LVTTL ; # Bank0 64N_SCP4
|
||||
#NET "NC" LOC = "E5" | IOSTANDARD = LVTTL ; # Bank5 CCAUX
|
||||
#NET "NC" LOC = "E6" | IOSTANDARD = LVTTL ; # Bank0 5N
|
||||
#NET "NC" LOC = "E9" | IOSTANDARD = LVTTL ; # Bank5 ND
|
||||
#NET "NC" LOC = "F10" | IOSTANDARD = LVTTL ; # Bank0 64P_SCP5
|
||||
#NET "NC" LOC = "F11" | IOSTANDARD = LVTTL ; # Bank5 CCAUX
|
||||
#NET "NC" LOC = "F12" | IOSTANDARD = LVTTL ; # Bank1 30P_A21_M1RST
|
||||
#NET "NC" LOC = "F6" | IOSTANDARD = LVTTL ; # Bank3 55P_M3A13
|
||||
#NET "NC" LOC = "F7" | IOSTANDARD = LVTTL ; # Bank0 5P
|
||||
#NET "NC" LOC = "F8" | IOSTANDARD = LVTTL ; # Bank5 CCAUX
|
||||
#NET "NC" LOC = "F9" | IOSTANDARD = LVTTL ; # Bank0 40P
|
||||
#NET "NC" LOC = "G10" | IOSTANDARD = LVTTL ; # Bank5 CCAUX
|
||||
#NET "NC" LOC = "G11" | IOSTANDARD = LVTTL ; # Bank1 30N_A20_M1A11
|
||||
#NET "NC" LOC = "G12" | IOSTANDARD = LVTTL ; # Bank1 38P_A5_M1CLK
|
||||
#NET "NC" LOC = "G15" | IOSTANDARD = LVTTL ; # Bank5 ND
|
||||
#NET "NC" LOC = "G2" | IOSTANDARD = LVTTL ; # Bank5 ND
|
||||
#NET "NC" LOC = "G6" | IOSTANDARD = LVTTL ; # Bank3 51P_M3A10
|
||||
#NET "NC" LOC = "G7" | IOSTANDARD = LVTTL ; # Bank5 CCINT
|
||||
#NET "NC" LOC = "G8" | IOSTANDARD = LVTTL ; # Bank5 ND
|
||||
#NET "NC" LOC = "G9" | IOSTANDARD = LVTTL ; # Bank5 CCINT
|
||||
#NET "NC" LOC = "H10" | IOSTANDARD = LVTTL ; # Bank5 CCINT
|
||||
#NET "NC" LOC = "H11" | IOSTANDARD = LVTTL ; # Bank1 38N_A4_M1CLKN
|
||||
#NET "NC" LOC = "H12" | IOSTANDARD = LVTTL ; # Bank5 ND
|
||||
#NET "NC" LOC = "H6" | IOSTANDARD = LVTTL ; # Bank5 CCAUX
|
||||
#NET "NC" LOC = "H7" | IOSTANDARD = LVTTL ; # Bank5 ND
|
||||
#NET "NC" LOC = "H8" | IOSTANDARD = LVTTL ; # Bank5 CCINT
|
||||
#NET "NC" LOC = "H9" | IOSTANDARD = LVTTL ; # Bank5 ND
|
||||
#NET "NC" LOC = "J10" | IOSTANDARD = LVTTL ; # Bank5 CCAUX
|
||||
#NET "NC" LOC = "J11" | IOSTANDARD = LVTTL ; # Bank1 40P_C11_M1A5
|
||||
#NET "NC" LOC = "J12" | IOSTANDARD = LVTTL ; # Bank1 40N_C10_M1A6
|
||||
#NET "NC" LOC = "J5" | IOSTANDARD = LVTTL ; # Bank5 ND
|
||||
#NET "NC" LOC = "J7" | IOSTANDARD = LVTTL ; # Bank5 CCINT
|
||||
#NET "NC" LOC = "J8" | IOSTANDARD = LVTTL ; # Bank5 ND
|
||||
#NET "NC" LOC = "J9" | IOSTANDARD = LVTTL ; # Bank5 CCINT
|
||||
#NET "NC" LOC = "K10" | IOSTANDARD = LVTTL ; # Bank5 CCINT
|
||||
#NET "NC" LOC = "K11" | IOSTANDARD = LVTTL ; # Bank1 42N_C6_M1LDM
|
||||
#NET "NC" LOC = "K12" | IOSTANDARD = LVTTL ; # Bank1 42P_C7_M1UDM
|
||||
#NET "NC" LOC = "K5" | IOSTANDARD = LVTTL ; # Bank3 47P_M3A0
|
||||
#NET "NC" LOC = "K6" | IOSTANDARD = LVTTL ; # Bank3 47N_M3A1
|
||||
#NET "NC" LOC = "K7" | IOSTANDARD = LVTTL ; # Bank5 ND
|
||||
#NET "NC" LOC = "K8" | IOSTANDARD = LVTTL ; # Bank5 CCINT
|
||||
#NET "NC" LOC = "K9" | IOSTANDARD = LVTTL ; # Bank5 ND
|
||||
#NET "NC" LOC = "L10" | IOSTANDARD = LVTTL ; # Bank2 16P
|
||||
#NET "NC" LOC = "L12" | IOSTANDARD = LVTTL ; # Bank1 53P
|
||||
#NET "NC" LOC = "L15" | IOSTANDARD = LVTTL ; # Bank5 ND
|
||||
#NET "NC" LOC = "L2" | IOSTANDARD = LVTTL ; # Bank5 ND
|
||||
#NET "NC" LOC = "L5" | IOSTANDARD = LVTTL ; # Bank3 45N_M3ODT
|
||||
#NET "NC" LOC = "L6" | IOSTANDARD = LVTTL ; # Bank5 CCAUX
|
||||
#NET "NC" LOC = "L9" | IOSTANDARD = LVTTL ; # Bank5 CCAUX
|
||||
#NET "NC" LOC = "M10" | IOSTANDARD = LVTTL ; # Bank2 16N_VREF
|
||||
#NET "NC" LOC = "M11" | IOSTANDARD = LVTTL ; # Bank2 2N_CMPMOSI
|
||||
#NET "NC" LOC = "M12" | IOSTANDARD = LVTTL ; # Bank2 2P_CMPCLK
|
||||
#NET "NC" LOC = "M5" | IOSTANDARD = LVTTL ; # Bank3 2P
|
||||
#NET "NC" LOC = "M6" | IOSTANDARD = LVTTL ; # Bank2 64P_D8
|
||||
#NET "NC" LOC = "M7" | IOSTANDARD = LVTTL ; # Bank2 31N_C30_D15
|
||||
#NET "NC" LOC = "M8" | IOSTANDARD = LVTTL ; # Bank5 ND
|
||||
#NET "NC" LOC = "N13" | IOSTANDARD = LVTTL ; # Bank5 ND
|
||||
#NET "NC" LOC = "P14" | IOSTANDARD = LVTTL ; # Bank4 USPEND
|
||||
#NET "NC" LOC = "P3" | IOSTANDARD = LVTTL ; # Bank5 ND
|
||||
#NET "NC" LOC = "P7" | IOSTANDARD = LVTTL ; # Bank2 31P_C31_D14
|
||||
#NET "NC" LOC = "R10" | IOSTANDARD = LVTTL ; # Bank5 ND
|
||||
#NET "NC" LOC = "R6" | IOSTANDARD = LVTTL ; # Bank5 ND
|
||||
#NET "NC" LOC = "T1" | IOSTANDARD = LVTTL ; # Bank5 ND
|
||||
#NET "NC" LOC = "T16" | IOSTANDARD = LVTTL ; # Bank5 ND
|
||||
#NET "NC" LOC = "T3" | IOSTANDARD = LVTTL ; # Bank2 65N_CSO_B
|
||||
#NET "NC" LOC = "T5" | IOSTANDARD = LVTTL ; # Bank2 48N_RDWR_VREF
|
||||
#NET "HSWPEN" LOC = "C4" | IOSTANDARD = LVTTL ; # Bank0 1P_HSWAPEN
|
||||
#NET "NINIT" LOC = "R3" | IOSTANDARD = LVTTL ; # Bank2 65P_INIT_B
|
||||
#NET "BANK<0>" LOC = "B13" | IOSTANDARD = LVTTL ; # Bank0 CCO
|
||||
#NET "BANK<0>" LOC = "B4" | IOSTANDARD = LVTTL ; # Bank0 CCO
|
||||
#NET "BANK<0>" LOC = "B9" | IOSTANDARD = LVTTL ; # Bank0 CCO
|
||||
#NET "BANK<0>" LOC = "D10" | IOSTANDARD = LVTTL ; # Bank0 CCO
|
||||
#NET "BANK<0>" LOC = "D7" | IOSTANDARD = LVTTL ; # Bank0 CCO
|
||||
NET "clkfx1" TNM_NET = "async_med"; # For async sserial processor
|
||||
NET "LCLK" TNM_NET = "async_low";
|
||||
TIMESPEC "TSLowToMed" = FROM "async_low" to "async_med" TIG;
|
||||
TIMESPEC "TSMedtoLow" = FROM "async_med" to "async_low" TIG;
|
||||
121
5i24/configs/hostmot2/source/4i74.ucf
Executable file
121
5i24/configs/hostmot2/source/4i74.ucf
Executable file
@@ -0,0 +1,121 @@
|
||||
NET "NREQ" LOC = "P137" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<31>" LOC = "P138" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<30>" LOC = "P139" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<29>" LOC = "P140" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<28>" LOC = "P141" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<27>" LOC = "P142" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<26>" LOC = "P143" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "PCLK" LOC = "P24" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<25>" LOC = "P1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<24>" LOC = "P2" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NCBE<3>" LOC = "P5" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<23>" LOC = "P6" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<22>" LOC = "P7" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<21>" LOC = "P8" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<20>" LOC = "P9" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<19>" LOC = "P10" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<18>" LOC = "P11" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<17>" LOC = "P12" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<16>" LOC = "P14" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NCBE<2>" LOC = "P15" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NIRDY" LOC = "P16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NFRAME" LOC = "P17" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NDEVSEL" LOC = "P21" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NTRDY" LOC = "P22" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NLOCK" LOC = "P23" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NSTOP" LOC = "P26" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NPERR" LOC = "P27" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "PAR" LOC = "P29" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NSERR" LOC = "P30" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NCBE<1>" LOC = "P32" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<15>" LOC = "P33" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<14>" LOC = "P34" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<13>" LOC = "P35" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<12>" LOC = "P40" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<11>" LOC = "P41" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<10>" LOC = "P43" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<9>" LOC = "P44" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<8>" LOC = "P45" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NCBE<0>" LOC = "P46" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<7>" LOC = "P47" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<6>" LOC = "P48" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<5>" LOC = "P50" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<4>" LOC = "P51" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<3>" LOC = "P55" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<2>" LOC = "P56" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<1>" LOC = "P57" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<0>" LOC = "P58" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "IDSEL" LOC = "P59" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NRST" LOC = "P61" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NINTA" LOC = "P62" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 | PULLUP;
|
||||
NET "XCLK" LOC = "P133" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
|
||||
NET "IOBITS<0>" LOC = "P132" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<1>" LOC = "P131" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<2>" LOC = "P127" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<3>" LOC = "P126" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<4>" LOC = "P124" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<5>" LOC = "P123" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<6>" LOC = "P121" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<7>" LOC = "P120" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<8>" LOC = "P119" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<9>" LOC = "P118" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<10>" LOC = "P117" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<11>" LOC = "P116" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<12>" LOC = "P115" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<13>" LOC = "P114" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<14>" LOC = "P112" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<15>" LOC = "P111" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<16>" LOC = "P105" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<17>" LOC = "P104" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<18>" LOC = "P102" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<19>" LOC = "P101" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<20>" LOC = "P100" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<21>" LOC = "P99" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<22>" LOC = "P98" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<23>" LOC = "P97" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<24>" LOC = "P95" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<25>" LOC = "P94" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<26>" LOC = "P93" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<27>" LOC = "P92" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<28>" LOC = "P88" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<29>" LOC = "P87" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<30>" LOC = "P85" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<31>" LOC = "P84" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<32>" LOC = "P83" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<33>" LOC = "P82" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<34>" LOC = "P81" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<35>" LOC = "P80" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<36>" LOC = "P79" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<37>" LOC = "P78" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<38>" LOC = "P67" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<39>" LOC = "P66" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<40>" LOC = "P75" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
NET "IOBITS<41>" LOC = "P74" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=8;
|
||||
|
||||
NET "SPICS" LOC = "P38" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "SPIDO" LOC = "P64" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "SPIDI" LOC = "P65" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "SPICLK" LOC = "P70" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
|
||||
#NET "TMS" LOC = "P107" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "TDI" LOC = "P110" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "TDO" LOC = "P106" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "TCK" LOC = "P109" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "NPROGRAM" LOC = "P37" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "NGNT" LOC = "P134" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "M0" LOC = "P69" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "M1" LOC = "P60" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "HSWAPEN" LOC = "P144" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NINIT" LOC = "P39" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "NDONE" LOC = "P71" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
|
||||
|
||||
NET "PCLK" TNM_NET = "PCLK";
|
||||
TIMESPEC "TS_PCLK" = PERIOD "PCLK" 30 ns HIGH 50 %;
|
||||
NET "XCLK" TNM_NET = "XCLK";
|
||||
TIMESPEC "TS_XCLK" = PERIOD "XCLK" 20 ns HIGH 50 %;
|
||||
NET "clkfx1" TNM_NET = "async_med"; # for async sserial processor clock
|
||||
NET "PCLK" TNM_NET = "async_low";
|
||||
TIMESPEC "TSLowToMed" = FROM "async_low" to "async_med" TIG;
|
||||
TIMESPEC "TSMedtoLow" = FROM "async_med" to "async_low" TIG;
|
||||
146
5i24/configs/hostmot2/source/5i20.ucf
Executable file
146
5i24/configs/hostmot2/source/5i20.ucf
Executable file
@@ -0,0 +1,146 @@
|
||||
TIMESPEC "TS_LCLK" = PERIOD "LCLK" 29.5 ns HIGH 50 %;
|
||||
TIMESPEC "TS_P2P" = FROM "PADS" TO "PADS" 50 ns;
|
||||
NET "LCLK" TNM_NET = "LCLK";
|
||||
OFFSET = OUT 24 ns AFTER "LCLK" ;
|
||||
OFFSET = IN 19.5 ns BEFORE "LCLK" ;
|
||||
#NET "SYNCLK" TNM_NET = "SYNCLK"
|
||||
#TIMESPEC "TS_SYNCLK" = PERIOD "SYNCLK" 19.5 ns HIGH 50 %
|
||||
# NET "SYNCLK" LOC = "p185" | IOSTANDARD = LVTTL
|
||||
# NET "WAITOUT" LOC = "p113" | IOSTANDARD = LVTTL
|
||||
NET "SYNCLK" TNM_NET = "SYNCLK";
|
||||
TIMESPEC "TS_SYNCLK" = PERIOD "SYNCLK" 20 ns HIGH 50 %;
|
||||
#PACE: Start of Constraints generated by PACE
|
||||
|
||||
#PACE: Start of PACE I/O Pin Assignments
|
||||
NET "ADS" LOC = "p98" | IOSTANDARD = LVTTL ;
|
||||
NET "BLAST" LOC = "p99" | IOSTANDARD = LVTTL ;
|
||||
NET "INT" LOC = "p112" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<0>" LOC = "p96" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<10>" LOC = "p63" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<11>" LOC = "p61" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<12>" LOC = "p59" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<13>" LOC = "p57" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<14>" LOC = "p48" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<15>" LOC = "p46" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<16>" LOC = "p44" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<17>" LOC = "p42" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<18>" LOC = "p37" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<19>" LOC = "p35" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<1>" LOC = "p94" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<20>" LOC = "p33" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<21>" LOC = "p30" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<22>" LOC = "p27" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<23>" LOC = "p23" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<24>" LOC = "p95" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<25>" LOC = "p90" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<26>" LOC = "p88" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<27>" LOC = "p86" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<28>" LOC = "p83" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<29>" LOC = "p81" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<2>" LOC = "p89" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<30>" LOC = "p74" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<31>" LOC = "p71" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<32>" LOC = "p69" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<33>" LOC = "p67" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<34>" LOC = "p62" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<35>" LOC = "p60" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<36>" LOC = "p58" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<37>" LOC = "p49" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<38>" LOC = "p47" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<39>" LOC = "p45" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<3>" LOC = "p87" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<40>" LOC = "p43" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<41>" LOC = "p41" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<42>" LOC = "p36" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<43>" LOC = "p34" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<44>" LOC = "p31" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<45>" LOC = "p29" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<46>" LOC = "p24" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<47>" LOC = "p22" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<48>" LOC = "p181" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<49>" LOC = "p187" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<4>" LOC = "p84" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<50>" LOC = "p188" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<51>" LOC = "p189" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<52>" LOC = "p191" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<53>" LOC = "p192" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<54>" LOC = "p193" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<55>" LOC = "p194" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<56>" LOC = "p195" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<57>" LOC = "p199" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<58>" LOC = "p200" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<59>" LOC = "p201" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<5>" LOC = "p82" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<60>" LOC = "p202" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<61>" LOC = "p203" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<62>" LOC = "p204" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<63>" LOC = "p205" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<64>" LOC = "p206" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<65>" LOC = "p3" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<66>" LOC = "p4" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<67>" LOC = "p5" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<68>" LOC = "p6" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<69>" LOC = "p7" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<6>" LOC = "p75" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<70>" LOC = "p8" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<71>" LOC = "p9" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<7>" LOC = "p73" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<8>" LOC = "p70" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<9>" LOC = "p68" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "LAD<0>" LOC = "p153" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<10>" LOC = "p172" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<11>" LOC = "p168" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<12>" LOC = "p167" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<13>" LOC = "p166" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<14>" LOC = "p165" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<15>" LOC = "p164" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<16>" LOC = "p163" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<17>" LOC = "p162" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<18>" LOC = "p152" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<19>" LOC = "p151" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<1>" LOC = "p146" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<20>" LOC = "p150" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<21>" LOC = "p149" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<22>" LOC = "p148" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<23>" LOC = "p147" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<24>" LOC = "p141" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<25>" LOC = "p140" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<26>" LOC = "p139" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<27>" LOC = "p138" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<28>" LOC = "p136" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<29>" LOC = "p134" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<2>" LOC = "p142" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<30>" LOC = "p133" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<31>" LOC = "p132" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<3>" LOC = "p135" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<4>" LOC = "p126" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<5>" LOC = "p119" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<6>" LOC = "p115" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<7>" LOC = "p108" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<8>" LOC = "p174" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<9>" LOC = "p173" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LBE<0>" IOSTANDARD = LVTTL ;
|
||||
NET "LBE<1>" IOSTANDARD = LVTTL ;
|
||||
NET "LBE<2>" IOSTANDARD = LVTTL ;
|
||||
NET "LBE<3>" IOSTANDARD = LVTTL ;
|
||||
NET "LCLK" LOC = "p182" | IOSTANDARD = LVTTL ;
|
||||
NET "LEDS<0>" LOC = "p10" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LEDS<1>" LOC = "p14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LEDS<2>" LOC = "p15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LEDS<3>" LOC = "p16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LEDS<4>" LOC = "p17" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LEDS<5>" LOC = "p18" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LEDS<6>" LOC = "p20" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LEDS<7>" LOC = "p21" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LW_R" LOC = "P101" | IOSTANDARD = LVTTL ;
|
||||
NET "READY" LOC = "p102" | IOSTANDARD = LVTTL | SLEW = FAST | DRIVE = 8 ;
|
||||
NET "SYNCLK" LOC = "p185" | IOSTANDARD = LVTTL ;
|
||||
INST "*CLKDLL_inst3" LOC = "DLL3"; # 50 MHz synclk clock multx2
|
||||
INST "*BUFG_inst3" LOC = "GCLKBUF3"; # 100 Mhz buffer = PWM clock
|
||||
INST "*BUFG_inst1" LOC = "GCLKBUF1"; # 50 MHz buffer = processor clock
|
||||
# Note the next four lines need to be commented out for configurations that do no use sserial
|
||||
# or you must set the 'Allow unused timing constraints option" (-aut in ngdbuild 10.1.03 only)
|
||||
# NET "CLK0" TNM_NET = "async_med"; # For async sserial processor
|
||||
# NET "LCLK" TNM_NET = "async_low";
|
||||
# TIMESPEC "TSLowToMed" = FROM "async_low" to "async_med" TIG;
|
||||
#TIMESPEC "TSMedtoLow" = FROM "async_med" to "async_low" TIG;
|
||||
146
5i24/configs/hostmot2/source/5i20ss.ucf
Executable file
146
5i24/configs/hostmot2/source/5i20ss.ucf
Executable file
@@ -0,0 +1,146 @@
|
||||
TIMESPEC "TS_LCLK" = PERIOD "LCLK" 29.5 ns HIGH 50 %;
|
||||
TIMESPEC "TS_P2P" = FROM "PADS" TO "PADS" 50 ns;
|
||||
NET "LCLK" TNM_NET = "LCLK";
|
||||
OFFSET = OUT 24 ns AFTER "LCLK" ;
|
||||
OFFSET = IN 19.5 ns BEFORE "LCLK" ;
|
||||
#NET "SYNCLK" TNM_NET = "SYNCLK"
|
||||
#TIMESPEC "TS_SYNCLK" = PERIOD "SYNCLK" 19.5 ns HIGH 50 %
|
||||
# NET "SYNCLK" LOC = "p185" | IOSTANDARD = LVTTL
|
||||
# NET "WAITOUT" LOC = "p113" | IOSTANDARD = LVTTL
|
||||
NET "SYNCLK" TNM_NET = "SYNCLK";
|
||||
TIMESPEC "TS_SYNCLK" = PERIOD "SYNCLK" 20 ns HIGH 50 %;
|
||||
#PACE: Start of Constraints generated by PACE
|
||||
|
||||
#PACE: Start of PACE I/O Pin Assignments
|
||||
NET "ADS" LOC = "p98" | IOSTANDARD = LVTTL ;
|
||||
NET "BLAST" LOC = "p99" | IOSTANDARD = LVTTL ;
|
||||
NET "INT" LOC = "p112" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<0>" LOC = "p96" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<10>" LOC = "p63" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<11>" LOC = "p61" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<12>" LOC = "p59" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<13>" LOC = "p57" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<14>" LOC = "p48" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<15>" LOC = "p46" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<16>" LOC = "p44" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<17>" LOC = "p42" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<18>" LOC = "p37" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<19>" LOC = "p35" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<1>" LOC = "p94" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<20>" LOC = "p33" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<21>" LOC = "p30" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<22>" LOC = "p27" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<23>" LOC = "p23" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<24>" LOC = "p95" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<25>" LOC = "p90" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<26>" LOC = "p88" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<27>" LOC = "p86" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<28>" LOC = "p83" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<29>" LOC = "p81" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<2>" LOC = "p89" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<30>" LOC = "p74" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<31>" LOC = "p71" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<32>" LOC = "p69" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<33>" LOC = "p67" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<34>" LOC = "p62" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<35>" LOC = "p60" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<36>" LOC = "p58" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<37>" LOC = "p49" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<38>" LOC = "p47" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<39>" LOC = "p45" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<3>" LOC = "p87" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<40>" LOC = "p43" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<41>" LOC = "p41" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<42>" LOC = "p36" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<43>" LOC = "p34" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<44>" LOC = "p31" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<45>" LOC = "p29" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<46>" LOC = "p24" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<47>" LOC = "p22" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<48>" LOC = "p181" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<49>" LOC = "p187" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<4>" LOC = "p84" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<50>" LOC = "p188" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<51>" LOC = "p189" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<52>" LOC = "p191" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<53>" LOC = "p192" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<54>" LOC = "p193" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<55>" LOC = "p194" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<56>" LOC = "p195" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<57>" LOC = "p199" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<58>" LOC = "p200" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<59>" LOC = "p201" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<5>" LOC = "p82" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<60>" LOC = "p202" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<61>" LOC = "p203" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<62>" LOC = "p204" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<63>" LOC = "p205" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<64>" LOC = "p206" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<65>" LOC = "p3" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<66>" LOC = "p4" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<67>" LOC = "p5" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<68>" LOC = "p6" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<69>" LOC = "p7" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<6>" LOC = "p75" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<70>" LOC = "p8" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<71>" LOC = "p9" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<7>" LOC = "p73" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<8>" LOC = "p70" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<9>" LOC = "p68" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "LAD<0>" LOC = "p153" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<10>" LOC = "p172" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<11>" LOC = "p168" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<12>" LOC = "p167" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<13>" LOC = "p166" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<14>" LOC = "p165" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<15>" LOC = "p164" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<16>" LOC = "p163" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<17>" LOC = "p162" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<18>" LOC = "p152" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<19>" LOC = "p151" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<1>" LOC = "p146" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<20>" LOC = "p150" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<21>" LOC = "p149" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<22>" LOC = "p148" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<23>" LOC = "p147" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<24>" LOC = "p141" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<25>" LOC = "p140" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<26>" LOC = "p139" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<27>" LOC = "p138" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<28>" LOC = "p136" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<29>" LOC = "p134" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<2>" LOC = "p142" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<30>" LOC = "p133" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<31>" LOC = "p132" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<3>" LOC = "p135" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<4>" LOC = "p126" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<5>" LOC = "p119" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<6>" LOC = "p115" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<7>" LOC = "p108" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<8>" LOC = "p174" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<9>" LOC = "p173" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LBE<0>" IOSTANDARD = LVTTL ;
|
||||
NET "LBE<1>" IOSTANDARD = LVTTL ;
|
||||
NET "LBE<2>" IOSTANDARD = LVTTL ;
|
||||
NET "LBE<3>" IOSTANDARD = LVTTL ;
|
||||
NET "LCLK" LOC = "p182" | IOSTANDARD = LVTTL ;
|
||||
NET "LEDS<0>" LOC = "p10" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LEDS<1>" LOC = "p14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LEDS<2>" LOC = "p15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LEDS<3>" LOC = "p16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LEDS<4>" LOC = "p17" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LEDS<5>" LOC = "p18" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LEDS<6>" LOC = "p20" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LEDS<7>" LOC = "p21" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LW_R" LOC = "P101" | IOSTANDARD = LVTTL ;
|
||||
NET "READY" LOC = "p102" | IOSTANDARD = LVTTL | SLEW = FAST | DRIVE = 8 ;
|
||||
NET "SYNCLK" LOC = "p185" | IOSTANDARD = LVTTL ;
|
||||
INST "*CLKDLL_inst3" LOC = "DLL3"; # 50 MHz synclk clock multx2
|
||||
INST "*BUFG_inst3" LOC = "GCLKBUF3"; # 100 Mhz buffer = PWM clock
|
||||
INST "*BUFG_inst1" LOC = "GCLKBUF1"; # 50 MHz buffer = processor clock
|
||||
# Note the next four lines need to be commented out for configurations that do no use sserial
|
||||
# or you must set the 'Allow unused timing constraints option" (-aut in ngdbuild 10.1.03 only)
|
||||
NET "CLK0" TNM_NET = "async_med"; # For async sserial processor
|
||||
NET "LCLK" TNM_NET = "async_low";
|
||||
TIMESPEC "TSLowToMed" = FROM "async_low" to "async_med" TIG;
|
||||
TIMESPEC "TSMedtoLow" = FROM "async_med" to "async_low" TIG;
|
||||
168
5i24/configs/hostmot2/source/5i21.ucf
Executable file
168
5i24/configs/hostmot2/source/5i21.ucf
Executable file
@@ -0,0 +1,168 @@
|
||||
#PACE: Start of Constraints generated by PACE
|
||||
|
||||
#PACE: Start of PACE I/O Pin Assignments
|
||||
OFFSET = IN 10 ns BEFORE "LCLK" ;
|
||||
INST "LAD<0>" TNM = "lad";
|
||||
INST "LAD<1>" TNM = "lad";
|
||||
INST "LAD<2>" TNM = "lad";
|
||||
INST "LAD<3>" TNM = "lad";
|
||||
INST "LAD<4>" TNM = "lad";
|
||||
INST "LAD<5>" TNM = "lad";
|
||||
INST "LAD<6>" TNM = "lad";
|
||||
INST "LAD<7>" TNM = "lad";
|
||||
INST "LAD<8>" TNM = "lad";
|
||||
INST "LAD<9>" TNM = "lad";
|
||||
INST "LAD<10>" TNM = "lad";
|
||||
INST "LAD<11>" TNM = "lad";
|
||||
INST "LAD<12>" TNM = "lad";
|
||||
INST "LAD<13>" TNM = "lad";
|
||||
INST "LAD<14>" TNM = "lad";
|
||||
INST "LAD<15>" TNM = "lad";
|
||||
INST "LAD<16>" TNM = "lad";
|
||||
INST "LAD<17>" TNM = "lad";
|
||||
INST "LAD<18>" TNM = "lad";
|
||||
INST "LAD<19>" TNM = "lad";
|
||||
INST "LAD<20>" TNM = "lad";
|
||||
INST "LAD<21>" TNM = "lad";
|
||||
INST "LAD<22>" TNM = "lad";
|
||||
INST "LAD<23>" TNM = "lad";
|
||||
INST "LAD<24>" TNM = "lad";
|
||||
INST "LAD<25>" TNM = "lad";
|
||||
INST "LAD<26>" TNM = "lad";
|
||||
INST "LAD<27>" TNM = "lad";
|
||||
INST "LAD<28>" TNM = "lad";
|
||||
INST "LAD<29>" TNM = "lad";
|
||||
INST "LAD<30>" TNM = "lad";
|
||||
INST "LAD<31>" TNM = "lad";
|
||||
|
||||
# NET "HOLDA" OFFSET = OUT 13 ns AFTER "LCLK" HIGH
|
||||
NET "READY" OFFSET = OUT 11.5 ns AFTER "LCLK" HIGH ;
|
||||
NET "ADS" LOC = "p79" | IOSTANDARD = LVTTL ;
|
||||
NET "CCS" LOC = "p166" | IOSTANDARD = LVTTL ;
|
||||
NET "IOBITS<0>" LOC = "p52" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<10>" LOC = "p26" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<11>" LOC = "p22" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<12>" LOC = "p20" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<13>" LOC = "p18" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<14>" LOC = "p15" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<15>" LOC = "p12" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<16>" LOC = "p10" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<17>" LOC = "p7" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<18>" LOC = "p4" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<19>" LOC = "p2" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<1>" LOC = "p50" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<20>" LOC = "p203" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<21>" LOC = "p199" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<22>" LOC = "p197" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<23>" LOC = "p194" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<24>" LOC = "p190" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<25>" LOC = "p187" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<26>" LOC = "p184" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<27>" LOC = "p182" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<28>" LOC = "p180" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<29>" LOC = "p176" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<2>" LOC = "p46" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<30>" LOC = "p172" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<31>" LOC = "p169" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<3>" LOC = "p44" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<4>" LOC = "p42" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<5>" LOC = "p39" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<6>" LOC = "p36" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<7>" LOC = "p34" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<8>" LOC = "p31" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<9>" LOC = "p28" | IOSTANDARD = LVTTL | SLEW = SLOW | KEEPER ;
|
||||
#NET "DACK" LOC = "p61" | IOSTANDARD = LVTTL ;
|
||||
#NET "DEN" LOC = "p57" | IOSTANDARD = LVTTL | PULLUP ;
|
||||
NET "HOLD" LOC = "p85" | IOSTANDARD = LVTTL | PULLUP ;
|
||||
NET "HOLDA" LOC = "p80" | IOSTANDARD = LVTTL | PULLUP ;
|
||||
#NET "INIT" LOC = "p83" | IOSTANDARD = LVTTL ;
|
||||
NET "INT" LOC = "p63" | IOSTANDARD = LVTTL | PULLUP ;
|
||||
NET "LAD<0>" LOC = "p92" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<10>" LOC = "p96" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<11>" LOC = "p97" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<12>" LOC = "p100" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<13>" LOC = "p101" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<14>" LOC = "p102" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<15>" LOC = "p106" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<16>" LOC = "p107" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<17>" LOC = "p108" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<18>" LOC = "p109" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<19>" LOC = "p111" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<1>" LOC = "p90" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<20>" LOC = "p113" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<21>" LOC = "p114" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<22>" LOC = "p115" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<23>" LOC = "p116" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<24>" LOC = "p117" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<25>" LOC = "p119" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<26>" LOC = "p120" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<27>" LOC = "p122" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<28>" LOC = "p123" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<29>" LOC = "p124" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<2>" LOC = "p87" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<30>" LOC = "p125" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<31>" LOC = "p126" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<3>" LOC = "p86" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<4>" LOC = "p74" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<5>" LOC = "p72" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<6>" LOC = "p68" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<7>" LOC = "p67" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<8>" LOC = "p94" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<9>" LOC = "p95" | IOSTANDARD = LVTTL | SLEW = FAST | KEEPER ;
|
||||
NET "LCLK" LOC = "p77" | IOSTANDARD = LVTTL ;
|
||||
NET "LEDS<0>" LOC = "p140" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "LEDS<1>" LOC = "p141" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "LEDS<2>" LOC = "p143" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "LEDS<3>" LOC = "p144" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "LEDS<4>" LOC = "p146" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "LEDS<5>" LOC = "p147" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "LEDS<6>" LOC = "p148" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "LEDS<7>" LOC = "p149" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "LW_R" LOC = "p133" | IOSTANDARD = LVTTL ;
|
||||
NET "READY" LOC = "p58" | IOSTANDARD = LVTTL ;
|
||||
NET "BLAST" LOC = "P76" | IOSTANDARD = LVTTL | PULLUP ;
|
||||
NET "DREQ" LOC = "P62" | IOSTANDARD = LVTTL | PULLUP ;
|
||||
NET "BTERM" LOC = "P93" | IOSTANDARD = LVTTL | PULLUP ;
|
||||
NET "DISABLECONF" LOC = "P205" | IOSTANDARD = LVTTL | PULLUP ;
|
||||
NET "IOBITS<32>" LOC = "p51" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<42>" LOC = "p200" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<43>" LOC = "p196" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<44>" LOC = "p189" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<45>" LOC = "p183" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<46>" LOC = "p178" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<47>" LOC = "p171" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<33>" LOC = "p45" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<34>" LOC = "p40" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<35>" LOC = "p35" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<36>" LOC = "p29" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<37>" LOC = "p24" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<38>" LOC = "p19" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<39>" LOC = "p13" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<40>" LOC = "p9" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<41>" LOC = "p3" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<48>" LOC = "p48" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<58>" LOC = "p198" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<59>" LOC = "p191" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<60>" LOC = "p185" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<61>" LOC = "p181" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<62>" LOC = "p175" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<63>" LOC = "p168" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<49>" LOC = "p43" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<50>" LOC = "p37" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<51>" LOC = "p33" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<52>" LOC = "p27" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<53>" LOC = "p21" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<54>" LOC = "p16" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<55>" LOC = "p11" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<56>" LOC = "p5" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "IOBITS<57>" LOC = "p204" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "LCLK" TNM_NET = "LCLK";
|
||||
TIMESPEC "TS_LCLK" = PERIOD "LCLK" 20 ns HIGH 50 %;
|
||||
#NET "*prclk*" TNM_NET = "prclk"; -- only for async sserial
|
||||
#TIMESPEC "TSLowToMed" = FROM "LCLK" to "prclk" TIG;
|
||||
#TIMESPEC "TSMedtoLow" = FROM "prclk" to "LCLK" TIG;
|
||||
#PACE: Start of PACE Area Constraints
|
||||
|
||||
#PACE: Start of PACE Prohibit Constraints
|
||||
|
||||
#PACE: End of Constraints generated by PACE
|
||||
243
5i24/configs/hostmot2/source/5i22.ucf
Executable file
243
5i24/configs/hostmot2/source/5i22.ucf
Executable file
@@ -0,0 +1,243 @@
|
||||
# NET "BHE<0>" LOC = "R2"
|
||||
# NET "BHE<1>" LOC = "T1"
|
||||
# NET "BHE<2>" LOC = "U1"
|
||||
# NET "BHE<3>" LOC = "T2"
|
||||
# NET "LRESET" LOC = "D3"
|
||||
# NET "WAITO" LOC = "E3"
|
||||
NET "BLAST" LOC = "E2" | IOSTANDARD = LVTTL ;
|
||||
NET "BTERM" LOC = "G4" | IOSTANDARD = LVTTL ;
|
||||
# NET "LSERR" LOC = "F4"
|
||||
# NET "DMPAF/EOT" LOC = "D1"
|
||||
NET "CCS" LOC = "C2" | IOSTANDARD = LVTTL;
|
||||
NET "DREQ" LOC = "C1" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
# NET "DACK" LOC = "C3"
|
||||
# NET "BREQO" LOC = "E1"
|
||||
# NET "CLK2" LOC = "P9"
|
||||
# NET "CLK3" LOC = "N9"
|
||||
# NET "CLK6" LOC = "F9"
|
||||
# NET "CLK7" LOC = "E9"
|
||||
NET "LCLK" TNM_NET = "LCLK";
|
||||
TIMESPEC "TS_LCLK" = PERIOD "LCLK" 18 ns HIGH 50 %;
|
||||
TIMESPEC "TS_P2P" = FROM "PADS" TO "PADS" 30 ns;
|
||||
#PACE: Start of Constraints generated by PACE
|
||||
#PACE: Start of PACE I/O Pin Assignments
|
||||
NET "ADS" LOC = "F2" | IOSTANDARD = LVTTL ;
|
||||
# NET "DEN" LOC = "V2" | IOSTANDARD = LVTTL
|
||||
NET "DISABLECONF" LOC = "J15" | DRIVE = 24 | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "HOLD" LOC = "G3" | IOSTANDARD = LVTTL ;
|
||||
NET "HOLDA" LOC = "G1" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "INT" LOC = "D2" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW | PULLUP;
|
||||
NET "IOBITS<0>" LOC = "A10" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<10>" LOC = "B14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<11>" LOC = "C14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<12>" LOC = "C15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<13>" LOC = "A15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<14>" LOC = "B15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<15>" LOC = "B13" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<16>" LOC = "A12" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<17>" LOC = "A11" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<18>" LOC = "C18" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<19>" LOC = "B18" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<1>" LOC = "B10" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<20>" LOC = "D18" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<21>" LOC = "D17" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<22>" LOC = "E16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<23>" LOC = "D16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<24>" LOC = "B4" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<25>" LOC = "C4" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<26>" LOC = "C5" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<27>" LOC = "D5" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<28>" LOC = "A4" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<29>" LOC = "A5" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<2>" LOC = "C11" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<30>" LOC = "B5" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<31>" LOC = "B6" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<32>" LOC = "C7" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<33>" LOC = "D7" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<34>" LOC = "C8" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<35>" LOC = "D8" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<36>" LOC = "E8" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<37>" LOC = "F8" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<38>" LOC = "A7" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<39>" LOC = "A8" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<3>" LOC = "D11" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<40>" LOC = "B9" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<41>" LOC = "A9" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<42>" LOC = "E9" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<43>" LOC = "F9" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<44>" LOC = "B3" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<45>" LOC = "D6" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<46>" LOC = "D9" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<47>" LOC = "E7" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<48>" LOC = "N9" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<49>" LOC = "T18" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<4>" LOC = "C12" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<50>" LOC = "T5" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<51>" LOC = "T4" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<52>" LOC = "U6" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<53>" LOC = "R9" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<54>" LOC = "R6" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<55>" LOC = "R5" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<56>" LOC = "V5" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<57>" LOC = "U5" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<58>" LOC = "V8" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<59>" LOC = "V7" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<5>" LOC = "D12" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<60>" LOC = "R8" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<61>" LOC = "T8" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<62>" LOC = "T11" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<63>" LOC = "R11" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<64>" LOC = "V11" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<65>" LOC = "V12" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<66>" LOC = "R13" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<67>" LOC = "U14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<68>" LOC = "V15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<69>" LOC = "U15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<6>" LOC = "D14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<70>" LOC = "R14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<71>" LOC = "V14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<72>" LOC = "P9" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<73>" LOC = "U18" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<74>" LOC = "P16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<75>" LOC = "R16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<76>" LOC = "R17" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<77>" LOC = "R18" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<78>" LOC = "P17" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<79>" LOC = "P18" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<7>" LOC = "D13" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<80>" LOC = "N15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<81>" LOC = "M15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<82>" LOC = "M18" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<83>" LOC = "N17" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<84>" LOC = "K15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<85>" LOC = "L15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<86>" LOC = "L16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<87>" LOC = "L18" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<88>" LOC = "L17" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<89>" LOC = "K17" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<8>" LOC = "D10" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<90>" LOC = "J18" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<91>" LOC = "J17" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<92>" LOC = "H17" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<93>" LOC = "H18" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<94>" LOC = "H16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<95>" LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<9>" LOC = "A14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LAD<0>" LOC = "T12" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<10>" LOC = "H2" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<11>" LOC = "H1" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<12>" LOC = "J2" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<13>" LOC = "J1" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<14>" LOC = "J4" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<15>" LOC = "K2" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<16>" LOC = "K1" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<17>" LOC = "K4" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<18>" LOC = "L1" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<19>" LOC = "L2" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<1>" LOC = "R12" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<20>" LOC = "L4" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<21>" LOC = "L3" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<22>" LOC = "M1" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<23>" LOC = "N2" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<24>" LOC = "M4" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<25>" LOC = "M3" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<26>" LOC = "P4" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<27>" LOC = "N4" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<28>" LOC = "P1" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<29>" LOC = "P2" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<2>" LOC = "N11" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<30>" LOC = "P3" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<31>" LOC = "R3" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<3>" LOC = "P11" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<4>" LOC = "U9" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<5>" LOC = "V9" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<6>" LOC = "R7" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<7>" LOC = "T7" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<8>" LOC = "H3" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LAD<9>" LOC = "H4" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "LCLK" LOC = "E10" | IOSTANDARD = LVTTL ;
|
||||
NET "LEDS<0>" LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LEDS<1>" LOC = "G16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LEDS<2>" LOC = "G18" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LEDS<3>" LOC = "F17" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LEDS<4>" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LEDS<5>" LOC = "E15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LEDS<6>" LOC = "E17" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LEDS<7>" LOC = "E18" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LW_R" LOC = "T3" | IOSTANDARD = LVTTL ;
|
||||
NET "READY" LOC = "V3" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
TIMEGRP "LADOut" OFFSET = OUT 13.5 ns AFTER "LCLK" HIGH ;
|
||||
TIMEGRP "LADOut" OFFSET = IN 9 ns BEFORE "LCLK" HIGH ;
|
||||
INST "LAD<31>" TNM = "LADOut";
|
||||
INST "LAD<30>" TNM = "LADOut";
|
||||
INST "LAD<29>" TNM = "LADOut";
|
||||
INST "LAD<28>" TNM = "LADOut";
|
||||
INST "LAD<27>" TNM = "LADOut";
|
||||
INST "LAD<26>" TNM = "LADOut";
|
||||
INST "LAD<25>" TNM = "LADOut";
|
||||
INST "LAD<24>" TNM = "LADOut";
|
||||
INST "LAD<23>" TNM = "LADOut";
|
||||
INST "LAD<22>" TNM = "LADOut";
|
||||
INST "LAD<21>" TNM = "LADOut";
|
||||
INST "LAD<20>" TNM = "LADOut";
|
||||
INST "LAD<19>" TNM = "LADOut";
|
||||
INST "LAD<18>" TNM = "LADOut";
|
||||
INST "LAD<17>" TNM = "LADOut";
|
||||
INST "LAD<16>" TNM = "LADOut";
|
||||
INST "LAD<15>" TNM = "LADOut";
|
||||
INST "LAD<14>" TNM = "LADOut";
|
||||
INST "LAD<13>" TNM = "LADOut";
|
||||
INST "LAD<12>" TNM = "LADOut";
|
||||
INST "LAD<11>" TNM = "LADOut";
|
||||
INST "LAD<10>" TNM = "LADOut";
|
||||
INST "LAD<9>" TNM = "LADOut";
|
||||
INST "LAD<8>" TNM = "LADOut";
|
||||
INST "LAD<7>" TNM = "LADOut";
|
||||
INST "LAD<6>" TNM = "LADOut";
|
||||
INST "LAD<5>" TNM = "LADOut";
|
||||
INST "LAD<4>" TNM = "LADOut";
|
||||
INST "LAD<3>" TNM = "LADOut";
|
||||
INST "LAD<2>" TNM = "LADOut";
|
||||
INST "LAD<1>" TNM = "LADOut";
|
||||
INST "LAD<0>" TNM = "LADOut";
|
||||
NET "BLAST" OFFSET = IN 8.5 ns BEFORE "LCLK" HIGH ;
|
||||
NET "LW_R" OFFSET = IN 8 ns BEFORE "LCLK" HIGH ;
|
||||
NET "HOLDA" OFFSET = OUT 13 ns AFTER "LCLK" HIGH ;
|
||||
NET "READY" OFFSET = OUT 11.5 ns AFTER "LCLK" HIGH ;
|
||||
INST "DPipe_0" IOB = TRUE;
|
||||
INST "DPipe_1" IOB = TRUE;
|
||||
INST "DPipe_2" IOB = TRUE;
|
||||
INST "DPipe_3" IOB = TRUE;
|
||||
INST "DPipe_4" IOB = TRUE;
|
||||
INST "DPipe_5" IOB = TRUE;
|
||||
INST "DPipe_6" IOB = TRUE;
|
||||
INST "DPipe_7" IOB = TRUE;
|
||||
INST "DPipe_8" IOB = TRUE;
|
||||
INST "DPipe_9" IOB = TRUE;
|
||||
INST "DPipe_10" IOB = TRUE;
|
||||
INST "DPipe_11" IOB = TRUE;
|
||||
INST "DPipe_12" IOB = TRUE;
|
||||
INST "DPipe_13" IOB = TRUE;
|
||||
INST "DPipe_14" IOB = TRUE;
|
||||
INST "DPipe_15" IOB = TRUE;
|
||||
INST "DPipe_16" IOB = TRUE;
|
||||
INST "DPipe_17" IOB = TRUE;
|
||||
INST "DPipe_18" IOB = TRUE;
|
||||
INST "DPipe_19" IOB = TRUE;
|
||||
INST "DPipe_20" IOB = TRUE;
|
||||
INST "DPipe_21" IOB = TRUE;
|
||||
INST "DPipe_22" IOB = TRUE;
|
||||
INST "DPipe_23" IOB = TRUE;
|
||||
INST "DPipe_24" IOB = TRUE;
|
||||
INST "DPipe_25" IOB = TRUE;
|
||||
INST "DPipe_26" IOB = TRUE;
|
||||
INST "DPipe_27" IOB = TRUE;
|
||||
INST "DPipe_28" IOB = TRUE;
|
||||
INST "DPipe_29" IOB = TRUE;
|
||||
INST "DPipe_30" IOB = TRUE;
|
||||
INST "DPipe_31" IOB = TRUE;
|
||||
NET "ReadTSEn_inv" TIG;
|
||||
NET "clkfx1" TNM_NET = "async_med"; # For async sserial processor
|
||||
NET "LCLK" TNM_NET = "async_low";
|
||||
TIMESPEC "TSLowToMed" = FROM "async_low" to "async_med" TIG;
|
||||
TIMESPEC "TSMedtoLow" = FROM "async_med" to "async_low" TIG;
|
||||
169
5i24/configs/hostmot2/source/5i23.ucf
Executable file
169
5i24/configs/hostmot2/source/5i23.ucf
Executable file
@@ -0,0 +1,169 @@
|
||||
OFFSET = IN 20 ns BEFORE "LCLK" ;
|
||||
INST "LAD<0>" TNM = "lad";
|
||||
INST "LAD<1>" TNM = "lad";
|
||||
INST "LAD<2>" TNM = "lad";
|
||||
INST "LAD<3>" TNM = "lad";
|
||||
INST "LAD<4>" TNM = "lad";
|
||||
INST "LAD<5>" TNM = "lad";
|
||||
INST "LAD<6>" TNM = "lad";
|
||||
INST "LAD<7>" TNM = "lad";
|
||||
INST "LAD<8>" TNM = "lad";
|
||||
INST "LAD<9>" TNM = "lad";
|
||||
INST "LAD<10>" TNM = "lad";
|
||||
INST "LAD<11>" TNM = "lad";
|
||||
INST "LAD<12>" TNM = "lad";
|
||||
INST "LAD<13>" TNM = "lad";
|
||||
INST "LAD<14>" TNM = "lad";
|
||||
INST "LAD<15>" TNM = "lad";
|
||||
INST "LAD<16>" TNM = "lad";
|
||||
INST "LAD<17>" TNM = "lad";
|
||||
INST "LAD<18>" TNM = "lad";
|
||||
INST "LAD<19>" TNM = "lad";
|
||||
INST "LAD<20>" TNM = "lad";
|
||||
INST "LAD<21>" TNM = "lad";
|
||||
INST "LAD<22>" TNM = "lad";
|
||||
INST "LAD<23>" TNM = "lad";
|
||||
INST "LAD<24>" TNM = "lad";
|
||||
INST "LAD<25>" TNM = "lad";
|
||||
INST "LAD<26>" TNM = "lad";
|
||||
INST "LAD<27>" TNM = "lad";
|
||||
INST "LAD<28>" TNM = "lad";
|
||||
INST "LAD<29>" TNM = "lad";
|
||||
INST "LAD<30>" TNM = "lad";
|
||||
INST "LAD<31>" TNM = "lad";
|
||||
NET "BLAST" OFFSET = IN 8.5 ns BEFORE "LCLK" HIGH ;
|
||||
NET "LW_R" OFFSET = IN 8 ns BEFORE "LCLK" HIGH ;
|
||||
NET "READY" OFFSET = OUT 11.5 ns AFTER "LCLK" HIGH ;
|
||||
TIMEGRP "lad" OFFSET = OUT 13.5 ns AFTER "LCLK" HIGH ;
|
||||
TIMEGRP "lad" OFFSET = IN 9 ns BEFORE "LCLK" HIGH ;
|
||||
# NET "BREQ0" LOC = "P205"
|
||||
#NET "DACK" LOC = "P36" | IOSTANDARD = LVCMOS33 | PULLUP ;
|
||||
#NET "DEN" LOC = "P57" | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "DREQ" LOC = "P37" | IOSTANDARD = LVCMOS33 | PULLUP ;
|
||||
#PACE: Start of Constraints generated by PACE
|
||||
#PACE: Start of PACE I/O Pin Assignments
|
||||
NET "ADS" LOC = "P46" | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "BLAST" LOC = "p44" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "CCS" LOC = "P197" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "DISABLECONF" LOC = "P200" | IOSTANDARD = LVCMOS33 | PULLDOWN | SLEW = SLOW ;
|
||||
NET "HOLD" LOC = "P50" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "HOLDA" LOC = "P48" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST ;
|
||||
NET "INT" LOC = "P39" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 12 ;
|
||||
NET "IOBITS<0>" LOC = "P199" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<10>" LOC = "P181" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<11>" LOC = "P180" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<12>" LOC = "P178" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<13>" LOC = "P176" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<14>" LOC = "P172" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<15>" LOC = "P171" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<16>" LOC = "P169" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<17>" LOC = "P168" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<18>" LOC = "P166" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<19>" LOC = "P165" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<1>" LOC = "P198" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<20>" LOC = "P189" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<21>" LOC = "P182" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<22>" LOC = "P175" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<23>" LOC = "P167" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<24>" LOC = "P35" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<25>" LOC = "P34" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<26>" LOC = "P33" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<27>" LOC = "P31" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<28>" LOC = "P29" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<29>" LOC = "P28" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<2>" LOC = "P196" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<30>" LOC = "P27" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<31>" LOC = "P26" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<32>" LOC = "P24" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<33>" LOC = "P22" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<34>" LOC = "P21" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<35>" LOC = "P20" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<36>" LOC = "P19" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<37>" LOC = "P18" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<38>" LOC = "P16" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<39>" LOC = "P15" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<3>" LOC = "P194" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<40>" LOC = "P13" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<41>" LOC = "P12" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<42>" LOC = "P11" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<43>" LOC = "P10" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<44>" LOC = "P9" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<45>" LOC = "P7" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<46>" LOC = "P5" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<47>" LOC = "P4" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<48>" LOC = "P123" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<49>" LOC = "P124" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<4>" LOC = "P191" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<50>" LOC = "P125" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<51>" LOC = "P126" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<52>" LOC = "P128" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<53>" LOC = "P130" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<54>" LOC = "P131" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<55>" LOC = "P132" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<56>" LOC = "P133" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<57>" LOC = "P135" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<58>" LOC = "P137" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<59>" LOC = "P138" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<5>" LOC = "P190" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<60>" LOC = "P139" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<61>" LOC = "P140" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<62>" LOC = "P141" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<63>" LOC = "P143" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<64>" LOC = "P144" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<65>" LOC = "P146" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<66>" LOC = "p147" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<67>" LOC = "P148" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<68>" LOC = "P149" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<69>" LOC = "P150" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<6>" LOC = "P187" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<70>" LOC = "P152" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<71>" LOC = "P154" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<7>" LOC = "P185" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<8>" LOC = "P184" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "IOBITS<9>" LOC = "P183" | DRIVE = 24 | SLEW = SLOW | PULLUP | IOSTANDARD = LVCMOS33 ;
|
||||
NET "LAD<0>" LOC = "P92" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<10>" LOC = "P64" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<11>" LOC = "P65" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<12>" LOC = "P71" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<13>" LOC = "P76" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<14>" LOC = "P78" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<15>" LOC = "P79" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<16>" LOC = "P80" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<17>" LOC = "P85" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<18>" LOC = "P93" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<19>" LOC = "P94" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<1>" LOC = "P90" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<20>" LOC = "P95" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<21>" LOC = "P96" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<22>" LOC = "P97" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<23>" LOC = "P100" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<24>" LOC = "P101" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<25>" LOC = "P102" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<26>" LOC = "P108" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<27>" LOC = "P109" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<28>" LOC = "P111" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<29>" LOC = "P113" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<2>" LOC = "P87" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<30>" LOC = "P114" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<31>" LOC = "P115" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<3>" LOC = "P86" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<4>" LOC = "P74" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<5>" LOC = "P72" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<6>" LOC = "P68" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<7>" LOC = "P67" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<8>" LOC = "P62" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LAD<9>" LOC = "P63" | IOSTANDARD = LVCMOS33 | DRIVE = 12 | SLEW = FAST | KEEPER ;
|
||||
NET "LCLK" LOC = "P77" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "LEDS<0>" LOC = "P83" | SLEW = SLOW | IOSTANDARD = LVCMOS33 | DRIVE = 24 ;
|
||||
NET "LEDS<1>" LOC = "P81" | SLEW = SLOW | IOSTANDARD = LVCMOS33 | DRIVE = 24 ;
|
||||
NET "LW_R" LOC = "P122" | IOSTANDARD = LVCMOS33 | PULLUP ;
|
||||
NET "READY" LOC = "P58" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ;
|
||||
NET "BTERM" LOC = "P61" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 12 ;
|
||||
# NET "RESET" LOC = "P42" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "LCLK" TNM_NET = "LCLK";
|
||||
TIMESPEC "TS_LCLK" = PERIOD "LCLK" 20 ns HIGH 50 %;
|
||||
OFFSET = OUT 20 ns AFTER "LCLK" ;
|
||||
NET "clkfx1" TNM_NET = "async_med"; # For async sserial processor
|
||||
NET "LCLK" TNM_NET = "async_low";
|
||||
TIMESPEC "TSLowToMed" = FROM "async_low" to "async_med" TIG;
|
||||
TIMESPEC "TSMedtoLow" = FROM "async_med" to "async_low" TIG;
|
||||
267
5i24/configs/hostmot2/source/5i24.ucf
Executable file
267
5i24/configs/hostmot2/source/5i24.ucf
Executable file
@@ -0,0 +1,267 @@
|
||||
|
||||
NET "NTRDY" LOC = "K11" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L42N_C6_M1LDM
|
||||
NET "AD<0>" LOC = "J14" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L43P_C5_M1DQ4
|
||||
NET "AD<10>" LOC = "P15" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L48P_HDC_M1DQ8
|
||||
NET "AD<11>" LOC = "P16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L48N_M1DQ9
|
||||
NET "AD<12>" LOC = "R15" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L49P_M1DQ10
|
||||
NET "AD<13>" LOC = "R16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L49N_M1DQ11
|
||||
NET "AD<14>" LOC = "R14" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L50P_M1UDQS
|
||||
NET "AD<15>" LOC = "T15" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L50N_M1UDQSN
|
||||
NET "AD<16>" LOC = "M9" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L29P_C3
|
||||
NET "AD<17>" LOC = "N8" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L29N_C2
|
||||
NET "AD<18>" LOC = "P8" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L30P_C1_D13
|
||||
NET "AD<19>" LOC = "T8" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L30N_C0_USRCC
|
||||
NET "AD<1>" LOC = "J16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L43N_C4_M1DQ5
|
||||
NET "AD<20>" LOC = "L8" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L62P_D5
|
||||
NET "AD<21>" LOC = "L7" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L62N_D6
|
||||
NET "AD<22>" LOC = "R7" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L32P_C29
|
||||
NET "AD<23>" LOC = "T7" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L32N_C28
|
||||
NET "AD<24>" LOC = "M7" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L31N_C30_D15
|
||||
NET "AD<25>" LOC = "P6" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L47P
|
||||
NET "AD<26>" LOC = "T6" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L47N
|
||||
NET "AD<27>" LOC = "M6" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L64P_D8
|
||||
NET "AD<28>" LOC = "N6" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L64N_D9
|
||||
NET "AD<29>" LOC = "R5" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L48P_D7
|
||||
NET "AD<2>" LOC = "K14" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L41N_C8_M1CAS
|
||||
NET "AD<30>" LOC = "T5" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L48N_RDWR_VREF
|
||||
NET "AD<31>" LOC = "N5" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L49P_D3
|
||||
NET "AD<3>" LOC = "K15" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L44P_A3_M1DQ6
|
||||
NET "AD<4>" LOC = "K16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L44N_A2_M1DQ7
|
||||
NET "AD<5>" LOC = "L14" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L47P_FWE_M1DQ0
|
||||
NET "AD<6>" LOC = "L16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L47N_LDC_M1DQ1
|
||||
NET "AD<7>" LOC = "M15" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L46P_FCS_M1DQ2
|
||||
NET "AD<8>" LOC = "N14" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L45P_A1_M1LDQS
|
||||
NET "AD<9>" LOC = "N16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L45N_A0_M1LDQS
|
||||
NET "IDSEL" LOC = "H14" | IOSTANDARD=LVTTL ; # Bank2 L39N_M1ODT
|
||||
NET "IOBITS<0>" LOC = "J4" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L42N_C24_M3LDM
|
||||
NET "IOBITS<10>" LOC = "M1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L35N_M3DQ11
|
||||
NET "IOBITS<11>" LOC = "M2" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L35P_M3DQ10
|
||||
NET "IOBITS<12>" LOC = "M3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L1N_VREF
|
||||
NET "IOBITS<13>" LOC = "M4" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L1P
|
||||
NET "IOBITS<14>" LOC = "L1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L36N_M3DQ9
|
||||
NET "IOBITS<15>" LOC = "L3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L36P_M3DQ8
|
||||
NET "IOBITS<16>" LOC = "K1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L37N_M3DQ1
|
||||
NET "IOBITS<17>" LOC = "K2" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L37P_M3DQ0
|
||||
NET "IOBITS<18>" LOC = "J1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L38N_M3DQ3
|
||||
NET "IOBITS<19>" LOC = "J3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L38P_M3DQ2
|
||||
NET "IOBITS<1>" LOC = "K3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L42P_C25_M3UDM
|
||||
NET "IOBITS<20>" LOC = "H1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L39N_M3LDQSN
|
||||
NET "IOBITS<21>" LOC = "H2" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L39P_M3LDQS
|
||||
NET "IOBITS<22>" LOC = "G1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L40N_M3DQ7
|
||||
NET "IOBITS<23>" LOC = "G3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L40P_M3DQ6
|
||||
NET "IOBITS<24>" LOC = "H3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L44N_C20_M3A6
|
||||
NET "IOBITS<25>" LOC = "H4" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L44P_C21_M3A5
|
||||
NET "IOBITS<26>" LOC = "F1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L41N_C26_M3DQ5
|
||||
NET "IOBITS<27>" LOC = "F2" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L41P_C27_M3DQ4
|
||||
NET "IOBITS<28>" LOC = "F3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L53N_M3A12
|
||||
NET "IOBITS<29>" LOC = "F4" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L53P_M3CKE
|
||||
NET "IOBITS<2>" LOC = "R1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L32N_M3DQ15
|
||||
NET "IOBITS<30>" LOC = "E1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L46N_M3CLKN
|
||||
NET "IOBITS<31>" LOC = "E2" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L46P_M3CLK
|
||||
NET "IOBITS<32>" LOC = "E3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L54N_M3A11
|
||||
NET "IOBITS<33>" LOC = "E4" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L54P_M3RESET
|
||||
NET "IOBITS<34>" LOC = "D1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L49N_M3A2
|
||||
NET "IOBITS<35>" LOC = "D3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L49P_M3A7
|
||||
NET "IOBITS<36>" LOC = "B1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L50N_M3BA2
|
||||
NET "IOBITS<37>" LOC = "C1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L50P_M3WE
|
||||
NET "IOBITS<38>" LOC = "C2" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L48N_M3BA1
|
||||
NET "IOBITS<39>" LOC = "C3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L48P_M3BA0
|
||||
NET "IOBITS<3>" LOC = "R2" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L32P_M3DQ14
|
||||
NET "IOBITS<40>" LOC = "A2" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L52N_M3A9
|
||||
NET "IOBITS<41>" LOC = "B2" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L52P_M3A8
|
||||
NET "IOBITS<42>" LOC = "A3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L83N_VREF
|
||||
NET "IOBITS<43>" LOC = "B3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L83P
|
||||
NET "IOBITS<44>" LOC = "A7" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L6N
|
||||
NET "IOBITS<45>" LOC = "C7" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L6P
|
||||
NET "IOBITS<46>" LOC = "A8" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L33N
|
||||
NET "IOBITS<47>" LOC = "B8" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L33P
|
||||
NET "IOBITS<48>" LOC = "A9" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L34N_C18
|
||||
NET "IOBITS<49>" LOC = "C9" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L34P_C19
|
||||
NET "IOBITS<4>" LOC = "P1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L33N_M3DQ13
|
||||
NET "IOBITS<50>" LOC = "A10" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L35N_C16
|
||||
NET "IOBITS<51>" LOC = "B10" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L35P_C17
|
||||
NET "IOBITS<52>" LOC = "A11" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L39N
|
||||
NET "IOBITS<53>" LOC = "C11" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L39P
|
||||
NET "IOBITS<54>" LOC = "A12" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L62N_VREF
|
||||
NET "IOBITS<55>" LOC = "B12" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L62P
|
||||
NET "IOBITS<56>" LOC = "A13" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L63N_SCP6
|
||||
NET "IOBITS<57>" LOC = "C13" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L63P_SCP7
|
||||
NET "IOBITS<58>" LOC = "A14" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L65N_SCP2
|
||||
NET "IOBITS<59>" LOC = "B14" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L65P_SCP3
|
||||
NET "IOBITS<5>" LOC = "P2" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L33P_M3DQ12
|
||||
NET "IOBITS<60>" LOC = "B16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank2 L29N_A22_M1A14
|
||||
NET "IOBITS<61>" LOC = "B15" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank2 L29P_A23_M1A13
|
||||
NET "IOBITS<62>" LOC = "C16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank2 L33N_A14_M1A4
|
||||
NET "IOBITS<63>" LOC = "C15" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank2 L33P_A15_M1A10
|
||||
NET "IOBITS<64>" LOC = "D16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank2 L31N_A18_M1A12
|
||||
NET "IOBITS<65>" LOC = "D14" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank2 L31P_A19_M1CKE
|
||||
NET "IOBITS<66>" LOC = "E16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank2 L34N_A12_M1BA2
|
||||
NET "IOBITS<67>" LOC = "E15" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank2 L34P_A13_M1WE
|
||||
NET "IOBITS<68>" LOC = "F16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank2 L35N_A10_M1A2
|
||||
NET "IOBITS<69>" LOC = "F15" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank2 L35P_A11_M1A7
|
||||
NET "IOBITS<6>" LOC = "N1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L34N_M3UDQSN
|
||||
NET "IOBITS<70>" LOC = "G16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank2 L36N_A8_M1BA1
|
||||
NET "IOBITS<71>" LOC = "G14" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank2 L36P_A9_M1BA0
|
||||
NET "IOBITS<7>" LOC = "N3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L34P_M3UDQS
|
||||
NET "IOBITS<8>" LOC = "N4" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L2N
|
||||
NET "IOBITS<9>" LOC = "M5" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L2P
|
||||
NET "LEDS<3>" LOC = "B5" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L2P
|
||||
NET "LEDS<2>" LOC = "A5" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L2N
|
||||
NET "LEDS<1>" LOC = "B6" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L4P
|
||||
NET "LEDS<0>" LOC = "A6" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L4N
|
||||
NET "NCBE<0>" LOC = "M16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L46N_FOE_M1DQ3
|
||||
NET "NCBE<1>" LOC = "T14" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L51P_M1DQ12
|
||||
NET "NCBE<2>" LOC = "P9" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L14N_D12
|
||||
NET "NCBE<3>" LOC = "P7" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L31P_C31_D14
|
||||
NET "NDEVSEL" LOC = "T9" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L23N
|
||||
NET "NFRAME" LOC = "N9" | IOSTANDARD=LVTTL ; # Bank3 L14P_D11
|
||||
#NET "NGNT" LOC = "P4" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L63P
|
||||
NET "NINIT" LOC = "T4" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 | PULLUP ; # Bank3 L63N
|
||||
NET "NINTA" LOC = "H16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 | PULLUP ; # Bank2 L37N_A6_M1A1
|
||||
NET "NIRDY" LOC = "J13" | IOSTANDARD=LVTTL ; # Bank2 L41P_C9_M1RAS
|
||||
NET "NLOCK" LOC = "R9" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L23P
|
||||
NET "NPERR" LOC = "T12" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L52N_M1DQ15
|
||||
NET "NREQ" LOC = "P5" | IOSTANDARD=LVTTL ; # Bank3 L49N_D4
|
||||
NET "NRST" LOC = "H13" | IOSTANDARD=LVTTL ; # Bank2 L39P_M1A3
|
||||
NET "NSERR" LOC = "T13" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L51N_M1DQ13
|
||||
NET "NSTOP" LOC = "M10" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L16N_VREF
|
||||
NET "PAR" LOC = "R12" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L52P_M1DQ14
|
||||
NET "PCLK" LOC = "K12" | IOSTANDARD=LVTTL ; # Bank2 L42P_C7_M1UDM
|
||||
NET "SPICLK" LOC = "R11" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L1P_CCLK
|
||||
NET "SPICS" LOC = "T3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L65N_CSO_B
|
||||
NET "SPIDI" LOC = "P10" | IOSTANDARD=LVTTL ; # Bank3 L3P_D0_MISO1
|
||||
NET "SPIDO" LOC = "T10" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L3N_CSI_MISO0
|
||||
NET "XCLK" LOC = "C10" | IOSTANDARD=LVTTL ; # Bank1 L37N_C12
|
||||
|
||||
NET "PCLK" TNM_NET = "PCLK";
|
||||
TIMESPEC "TS_PCLK" = PERIOD "PCLK" 30 ns HIGH 50 %;
|
||||
NET "XCLK" TNM_NET = "XCLK";
|
||||
TIMESPEC "TS_XCLK" = PERIOD "XCLK" 20 ns HIGH 50 %;
|
||||
NET "clkfx1" TNM_NET = "async_med"; # for async sserial processor clock
|
||||
NET "PCLK" TNM_NET = "async_low";
|
||||
TIMESPEC "TSLowToMed" = FROM "async_low" to "async_med" TIG;
|
||||
TIMESPEC "TSMedtoLow" = FROM "async_med" to "async_low" TIG;
|
||||
|
||||
#NET "NINIT" LOC = "R3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 | IOSTANDARD = LVCMOS33 | PULLUP ; # Bank3 L65P_INIT_B (error on proto)
|
||||
#NET "M0" LOC = "T11" ; # Bank3 L1N_M0_CMPMISO
|
||||
#NET "M1" LOC = "N11" ; # Bank3 L13P_M1
|
||||
#NET "PWRGOOD" LOC = "T2" ; # Bank3 PROGRAM_B
|
||||
#NET "DONE" LOC = "P13" ; # Bank3 DONE
|
||||
#NET "<3.3V>" LOC = "B13" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "B4" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "B9" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "D10" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "D15" ; # Bank2 VCCO
|
||||
#NET "<3.3V>" LOC = "D2" ; # Bank4 VCCO
|
||||
#NET "<3.3V>" LOC = "D7" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "G13" ; # Bank2 VCCO
|
||||
#NET "<3.3V>" LOC = "G4" ; # Bank4 VCCO
|
||||
#NET "<3.3V>" LOC = "J15" ; # Bank2 VCCO
|
||||
#NET "<3.3V>" LOC = "J2" ; # Bank4 VCCO
|
||||
#NET "<3.3V>" LOC = "K13" ; # Bank2 VCCO
|
||||
#NET "<3.3V>" LOC = "K4" ; # Bank4 VCCO
|
||||
#NET "<3.3V>" LOC = "L11" ; # Bank3 CMPCS_B
|
||||
#NET "<3.3V>" LOC = "N10" ; # Bank3 VCCO
|
||||
#NET "<3.3V>" LOC = "N15" ; # Bank2 VCCO
|
||||
#NET "<3.3V>" LOC = "N2" ; # Bank4 VCCO
|
||||
#NET "<3.3V>" LOC = "N7" ; # Bank3 VCCO
|
||||
#NET "<3.3V>" LOC = "R13" ; # Bank2 VCCO
|
||||
#NET "<3.3V>" LOC = "R4" ; # Bank3 VCCO
|
||||
#NET "<3.3V>" LOC = "R8" ; # Bank3 VCCO
|
||||
#NET "FPGATCK" LOC = "C14" ; # Bank5 TCK
|
||||
#NET "FPGATDI" LOC = "C12" ; # Bank5 TDI
|
||||
#NET "FPGATDO" LOC = "E14" ; # Bank5 TDO
|
||||
#NET "FPGATMS" LOC = "A15" ; # Bank5 TMS
|
||||
#NET "HSWAPEN" LOC = "C4" ; # Bank1 L1P_HSWAPEN
|
||||
#NET "NC" LOC = "A1" ; # Bank6 GND
|
||||
#NET "NC" LOC = "A16" ; # Bank6 GND
|
||||
#NET "NC" LOC = "A4" ; # Bank1 L1N_VREF
|
||||
#NET "NC" LOC = "B11" ; # Bank6 GND
|
||||
#NET "NC" LOC = "B7" ; # Bank6 GND
|
||||
#NET "NC" LOC = "C5" ; # Bank1 L3N
|
||||
#NET "NC" LOC = "C6" ; # Bank1 L7N
|
||||
#NET "NC" LOC = "C8" ; # Bank1 L38N_VREF
|
||||
#NET "NC" LOC = "D11" ; # Bank1 L66P_SCP1
|
||||
#NET "NC" LOC = "D12" ; # Bank1 L66N_SCP0
|
||||
#NET "NC" LOC = "D13" ; # Bank6 GND
|
||||
#NET "NC" LOC = "D4" ; # Bank6 GND
|
||||
#NET "NC" LOC = "D5" ; # Bank1 L3P
|
||||
#NET "NC" LOC = "D6" ; # Bank1 L7P
|
||||
#NET "NC" LOC = "D8" ; # Bank1 L38P
|
||||
#NET "NC" LOC = "D9" ; # Bank1 L40N
|
||||
#NET "NC" LOC = "E10" ; # Bank1 L37P_C13
|
||||
#NET "NC" LOC = "E11" ; # Bank1 L64N_SCP4
|
||||
#NET "NC" LOC = "E12" ; # Bank2 L1N_A24_VREF
|
||||
#NET "NC" LOC = "E13" ; # Bank2 L1P_A25
|
||||
#NET "NC" LOC = "E5" ; # Bank6 VCCAUX
|
||||
#NET "NC" LOC = "E6" ; # Bank1 L5N
|
||||
#NET "NC" LOC = "E7" ; # Bank1 L36P_C15
|
||||
#NET "NC" LOC = "E8" ; # Bank1 L36N_C14
|
||||
#NET "NC" LOC = "E9" ; # Bank6 GND
|
||||
#NET "NC" LOC = "F10" ; # Bank1 L64P_SCP5
|
||||
#NET "NC" LOC = "F11" ; # Bank6 VCCAUX
|
||||
#NET "NC" LOC = "F12" ; # Bank2 L30P_A21_M1RST
|
||||
#NET "NC" LOC = "F13" ; # Bank2 L32P_A17_M1A8
|
||||
#NET "NC" LOC = "F14" ; # Bank2 L32N_A16_M1A9
|
||||
#NET "NC" LOC = "F5" ; # Bank4 L55N_M3A14
|
||||
#NET "NC" LOC = "F6" ; # Bank4 L55P_M3A13
|
||||
#NET "NC" LOC = "F7" ; # Bank1 L5P
|
||||
#NET "NC" LOC = "F8" ; # Bank6 VCCAUX
|
||||
#NET "NC" LOC = "F9" ; # Bank1 L40P
|
||||
#NET "NC" LOC = "G10" ; # Bank6 VCCAUX
|
||||
#NET "NC" LOC = "G11" ; # Bank2 L30N_A20_M1A11
|
||||
#NET "NC" LOC = "G12" ; # Bank2 L38P_A5_M1CLK
|
||||
#NET "NC" LOC = "G15" ; # Bank6 GND
|
||||
#NET "NC" LOC = "G2" ; # Bank6 GND
|
||||
#NET "NC" LOC = "G5" ; # Bank4 L51N_M3A4
|
||||
#NET "NC" LOC = "G6" ; # Bank4 L51P_M3A10
|
||||
#NET "NC" LOC = "G7" ; # Bank6 VCCINT
|
||||
#NET "NC" LOC = "G8" ; # Bank6 GND
|
||||
#NET "NC" LOC = "G9" ; # Bank6 VCCINT
|
||||
#NET "NC" LOC = "H10" ; # Bank6 VCCINT
|
||||
#NET "NC" LOC = "H11" ; # Bank2 L38N_A4_M1CLKN
|
||||
#NET "NC" LOC = "H12" ; # Bank6 GND
|
||||
#NET "NC" LOC = "H15" ; # Bank2 L37P_A7_M1A0
|
||||
#NET "NC" LOC = "H5" ; # Bank4 L43N_C22_M3CAS
|
||||
#NET "NC" LOC = "H6" ; # Bank6 VCCAUX
|
||||
#NET "NC" LOC = "H7" ; # Bank6 GND
|
||||
#NET "NC" LOC = "H8" ; # Bank6 VCCINT
|
||||
#NET "NC" LOC = "H9" ; # Bank6 GND
|
||||
#NET "NC" LOC = "J10" ; # Bank6 VCCAUX
|
||||
#NET "NC" LOC = "J11" ; # Bank2 L40P_C11_M1A5
|
||||
#NET "NC" LOC = "J12" ; # Bank2 L40N_C10_M1A6
|
||||
#NET "NC" LOC = "J5" ; # Bank6 GND
|
||||
#NET "NC" LOC = "J6" ; # Bank4 L43P_C23_M3RAS
|
||||
#NET "NC" LOC = "J7" ; # Bank6 VCCINT
|
||||
#NET "NC" LOC = "J8" ; # Bank6 GND
|
||||
#NET "NC" LOC = "J9" ; # Bank6 VCCINT
|
||||
#NET "NC" LOC = "K10" ; # Bank6 VCCINT
|
||||
#NET "NC" LOC = "K5" ; # Bank4 L47P_M3A0
|
||||
#NET "NC" LOC = "K6" ; # Bank4 L47N_M3A1
|
||||
#NET "NC" LOC = "K7" ; # Bank6 GND
|
||||
#NET "NC" LOC = "K8" ; # Bank6 VCCINT
|
||||
#NET "NC" LOC = "K9" ; # Bank6 GND
|
||||
#NET "NC" LOC = "L10" ; # Bank3 L16P
|
||||
#NET "NC" LOC = "L12" ; # Bank2 L53P
|
||||
#NET "NC" LOC = "L13" ; # Bank2 L53N_VREF
|
||||
#NET "NC" LOC = "L15" ; # Bank6 GND
|
||||
#NET "NC" LOC = "L2" ; # Bank6 GND
|
||||
#NET "NC" LOC = "L4" ; # Bank4 L45P_M3A3
|
||||
#NET "NC" LOC = "L5" ; # Bank4 L45N_M3ODT
|
||||
#NET "NC" LOC = "L6" ; # Bank6 VCCAUX
|
||||
#NET "NC" LOC = "L9" ; # Bank6 VCCAUX
|
||||
#NET "NC" LOC = "M11" ; # Bank3 L2N_CMPMOSI
|
||||
#NET "NC" LOC = "M12" ; # Bank3 L2P_CMPCLK
|
||||
#NET "NC" LOC = "M13" ; # Bank2 L74P_AWAKE
|
||||
#NET "NC" LOC = "M14" ; # Bank2 L74N_DOUT_BUS
|
||||
#NET "NC" LOC = "M8" ; # Bank6 GND
|
||||
#NET "NC" LOC = "N12" ; # Bank3 L12P_D1_MISO2
|
||||
#NET "NC" LOC = "N13" ; # Bank6 GND
|
||||
#NET "NC" LOC = "P11" ; # Bank3 L13N_D10
|
||||
#NET "NC" LOC = "P12" ; # Bank3 L12N_D2_MISO3
|
||||
#NET "NC" LOC = "P14" ; # Bank5 SUSPEND
|
||||
#NET "NC" LOC = "P3" ; # Bank6 GND
|
||||
#NET "NC" LOC = "R10" ; # Bank6 GND
|
||||
#NET "NC" LOC = "R6" ; # Bank6 GND
|
||||
#NET "NC" LOC = "T1" ; # Bank6 GND
|
||||
#NET "NC" LOC = "T16" ; # Bank6 GND
|
||||
121
5i24/configs/hostmot2/source/5i25.ucf
Executable file
121
5i24/configs/hostmot2/source/5i25.ucf
Executable file
@@ -0,0 +1,121 @@
|
||||
NET "NREQ" LOC = "P137" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<31>" LOC = "P138" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<30>" LOC = "P139" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<29>" LOC = "P140" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<28>" LOC = "P141" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<27>" LOC = "P142" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<26>" LOC = "P143" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "PCLK" LOC = "P24" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<25>" LOC = "P1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<24>" LOC = "P2" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NCBE<3>" LOC = "P5" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<23>" LOC = "P6" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<22>" LOC = "P7" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<21>" LOC = "P8" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<20>" LOC = "P9" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<19>" LOC = "P10" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<18>" LOC = "P11" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<17>" LOC = "P12" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<16>" LOC = "P14" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NCBE<2>" LOC = "P15" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NIRDY" LOC = "P16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NFRAME" LOC = "P17" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NDEVSEL" LOC = "P21" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NTRDY" LOC = "P22" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NLOCK" LOC = "P23" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NSTOP" LOC = "P26" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NPERR" LOC = "P27" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "PAR" LOC = "P29" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NSERR" LOC = "P30" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NCBE<1>" LOC = "P32" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<15>" LOC = "P33" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<14>" LOC = "P34" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<13>" LOC = "P35" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<12>" LOC = "P40" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<11>" LOC = "P41" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<10>" LOC = "P43" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<9>" LOC = "P44" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<8>" LOC = "P45" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NCBE<0>" LOC = "P46" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<7>" LOC = "P47" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<6>" LOC = "P48" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<5>" LOC = "P50" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<4>" LOC = "P51" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<3>" LOC = "P55" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<2>" LOC = "P56" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<1>" LOC = "P57" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<0>" LOC = "P58" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "IDSEL" LOC = "P59" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NRST" LOC = "P61" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NINTA" LOC = "P62" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 | PULLUP;
|
||||
NET "XCLK" LOC = "P133" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
|
||||
NET "IOBITS<0>" LOC = "P132" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<1>" LOC = "P131" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<2>" LOC = "P127" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<3>" LOC = "P126" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<4>" LOC = "P124" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<5>" LOC = "P123" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<6>" LOC = "P121" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<7>" LOC = "P120" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<8>" LOC = "P119" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<9>" LOC = "P118" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<10>" LOC = "P117" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<11>" LOC = "P116" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<12>" LOC = "P115" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<13>" LOC = "P114" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<14>" LOC = "P112" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<15>" LOC = "P111" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<16>" LOC = "P83" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<17>" LOC = "P105" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<18>" LOC = "P104" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<19>" LOC = "P102" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<20>" LOC = "P101" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<21>" LOC = "P100" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<22>" LOC = "P99" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<23>" LOC = "P98" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<24>" LOC = "P97" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<25>" LOC = "P95" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<26>" LOC = "P94" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<27>" LOC = "P93" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<28>" LOC = "P92" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<29>" LOC = "P88" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<30>" LOC = "P87" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<31>" LOC = "P85" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<32>" LOC = "P84" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<33>" LOC = "P82" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
|
||||
NET "SPICS" LOC = "P38" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "SPIDO" LOC = "P64" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "SPIDI" LOC = "P65" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "SPICLK" LOC = "P70" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
|
||||
NET "LEDS<0>" LOC = "P74" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "LEDS<1>" LOC = "P75" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
|
||||
#NET "LIOBITS<0>" LOC = "P81" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "LIOBITS<1>" LOC = "P80" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "LIOBITS<2>" LOC = "P79" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "LIOBITS<3>" LOC = "P78" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "LIOBITS<4>" LOC = "P66" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "LIOBITS<5>" LOC = "P67" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "TMS" LOC = "P107" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "TDI" LOC = "P110" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "TDO" LOC = "P106" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "TCK" LOC = "P109" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "NPROGRAM" LOC = "P37" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "NGNT" LOC = "P134" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "M0" LOC = "P69" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "M1" LOC = "P60" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "HSWAPEN" LOC = "P144" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NINIT" LOC = "P39" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "NDONE" LOC = "P71" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
|
||||
NET "PCLK" TNM_NET = "PCLK";
|
||||
TIMESPEC "TS_PCLK" = PERIOD "PCLK" 30 ns HIGH 50 %;
|
||||
NET "XCLK" TNM_NET = "XCLK";
|
||||
TIMESPEC "TS_XCLK" = PERIOD "XCLK" 20 ns HIGH 50 %;
|
||||
NET "clkfx1" TNM_NET = "async_med"; # for async sserial processor clock
|
||||
NET "PCLK" TNM_NET = "async_low";
|
||||
TIMESPEC "TSLowToMed" = FROM "async_low" to "async_med" TIG;
|
||||
TIMESPEC "TSMedtoLow" = FROM "async_med" to "async_low" TIG;
|
||||
267
5i24/configs/hostmot2/source/6i24.ucf
Executable file
267
5i24/configs/hostmot2/source/6i24.ucf
Executable file
@@ -0,0 +1,267 @@
|
||||
|
||||
NET "NTRDY" LOC = "K11" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L42N_C6_M1LDM
|
||||
NET "AD<0>" LOC = "J14" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L43P_C5_M1DQ4
|
||||
NET "AD<10>" LOC = "P15" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L48P_HDC_M1DQ8
|
||||
NET "AD<11>" LOC = "P16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L48N_M1DQ9
|
||||
NET "AD<12>" LOC = "R15" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L49P_M1DQ10
|
||||
NET "AD<13>" LOC = "R16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L49N_M1DQ11
|
||||
NET "AD<14>" LOC = "R14" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L50P_M1UDQS
|
||||
NET "AD<15>" LOC = "T15" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L50N_M1UDQSN
|
||||
NET "AD<16>" LOC = "M9" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L29P_C3
|
||||
NET "AD<17>" LOC = "N8" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L29N_C2
|
||||
NET "AD<18>" LOC = "P8" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L30P_C1_D13
|
||||
NET "AD<19>" LOC = "T8" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L30N_C0_USRCC
|
||||
NET "AD<1>" LOC = "J16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L43N_C4_M1DQ5
|
||||
NET "AD<20>" LOC = "L8" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L62P_D5
|
||||
NET "AD<21>" LOC = "L7" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L62N_D6
|
||||
NET "AD<22>" LOC = "R7" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L32P_C29
|
||||
NET "AD<23>" LOC = "T7" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L32N_C28
|
||||
NET "AD<24>" LOC = "M7" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L31N_C30_D15
|
||||
NET "AD<25>" LOC = "P6" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L47P
|
||||
NET "AD<26>" LOC = "T6" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L47N
|
||||
NET "AD<27>" LOC = "M6" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L64P_D8
|
||||
NET "AD<28>" LOC = "N6" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L64N_D9
|
||||
NET "AD<29>" LOC = "R5" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L48P_D7
|
||||
NET "AD<2>" LOC = "K14" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L41N_C8_M1CAS
|
||||
NET "AD<30>" LOC = "T5" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L48N_RDWR_VREF
|
||||
NET "AD<31>" LOC = "N5" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L49P_D3
|
||||
NET "AD<3>" LOC = "K15" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L44P_A3_M1DQ6
|
||||
NET "AD<4>" LOC = "K16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L44N_A2_M1DQ7
|
||||
NET "AD<5>" LOC = "L14" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L47P_FWE_M1DQ0
|
||||
NET "AD<6>" LOC = "L16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L47N_LDC_M1DQ1
|
||||
NET "AD<7>" LOC = "M15" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L46P_FCS_M1DQ2
|
||||
NET "AD<8>" LOC = "N14" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L45P_A1_M1LDQS
|
||||
NET "AD<9>" LOC = "N16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L45N_A0_M1LDQS
|
||||
NET "IDSEL" LOC = "H14" | IOSTANDARD=LVTTL ; # Bank2 L39N_M1ODT
|
||||
NET "IOBITS<0>" LOC = "J4" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L42N_C24_M3LDM
|
||||
NET "IOBITS<10>" LOC = "M1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L35N_M3DQ11
|
||||
NET "IOBITS<11>" LOC = "M2" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L35P_M3DQ10
|
||||
NET "IOBITS<12>" LOC = "M3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L1N_VREF
|
||||
NET "IOBITS<13>" LOC = "M4" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L1P
|
||||
NET "IOBITS<14>" LOC = "L1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L36N_M3DQ9
|
||||
NET "IOBITS<15>" LOC = "L3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L36P_M3DQ8
|
||||
NET "IOBITS<16>" LOC = "K1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L37N_M3DQ1
|
||||
NET "IOBITS<17>" LOC = "K2" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L37P_M3DQ0
|
||||
NET "IOBITS<18>" LOC = "J1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L38N_M3DQ3
|
||||
NET "IOBITS<19>" LOC = "J3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L38P_M3DQ2
|
||||
NET "IOBITS<1>" LOC = "K3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L42P_C25_M3UDM
|
||||
NET "IOBITS<20>" LOC = "H1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L39N_M3LDQSN
|
||||
NET "IOBITS<21>" LOC = "H2" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L39P_M3LDQS
|
||||
NET "IOBITS<22>" LOC = "G1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L40N_M3DQ7
|
||||
NET "IOBITS<23>" LOC = "G3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L40P_M3DQ6
|
||||
NET "IOBITS<24>" LOC = "H3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L44N_C20_M3A6
|
||||
NET "IOBITS<25>" LOC = "H4" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L44P_C21_M3A5
|
||||
NET "IOBITS<26>" LOC = "F1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L41N_C26_M3DQ5
|
||||
NET "IOBITS<27>" LOC = "F2" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L41P_C27_M3DQ4
|
||||
NET "IOBITS<28>" LOC = "F3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L53N_M3A12
|
||||
NET "IOBITS<29>" LOC = "F4" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L53P_M3CKE
|
||||
NET "IOBITS<2>" LOC = "R1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L32N_M3DQ15
|
||||
NET "IOBITS<30>" LOC = "E1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L46N_M3CLKN
|
||||
NET "IOBITS<31>" LOC = "E2" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L46P_M3CLK
|
||||
NET "IOBITS<32>" LOC = "E3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L54N_M3A11
|
||||
NET "IOBITS<33>" LOC = "E4" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L54P_M3RESET
|
||||
NET "IOBITS<34>" LOC = "D1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L49N_M3A2
|
||||
NET "IOBITS<35>" LOC = "D3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L49P_M3A7
|
||||
NET "IOBITS<36>" LOC = "B1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L50N_M3BA2
|
||||
NET "IOBITS<37>" LOC = "C1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L50P_M3WE
|
||||
NET "IOBITS<38>" LOC = "C2" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L48N_M3BA1
|
||||
NET "IOBITS<39>" LOC = "C3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L48P_M3BA0
|
||||
NET "IOBITS<3>" LOC = "R2" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L32P_M3DQ14
|
||||
NET "IOBITS<40>" LOC = "A2" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L52N_M3A9
|
||||
NET "IOBITS<41>" LOC = "B2" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L52P_M3A8
|
||||
NET "IOBITS<42>" LOC = "A3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L83N_VREF
|
||||
NET "IOBITS<43>" LOC = "B3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L83P
|
||||
NET "IOBITS<44>" LOC = "A7" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L6N
|
||||
NET "IOBITS<45>" LOC = "C7" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L6P
|
||||
NET "IOBITS<46>" LOC = "A8" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L33N
|
||||
NET "IOBITS<47>" LOC = "B8" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L33P
|
||||
NET "IOBITS<48>" LOC = "A9" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L34N_C18
|
||||
NET "IOBITS<49>" LOC = "C9" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L34P_C19
|
||||
NET "IOBITS<4>" LOC = "P1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L33N_M3DQ13
|
||||
NET "IOBITS<50>" LOC = "A10" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L35N_C16
|
||||
NET "IOBITS<51>" LOC = "B10" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L35P_C17
|
||||
NET "IOBITS<52>" LOC = "A11" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L39N
|
||||
NET "IOBITS<53>" LOC = "C11" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L39P
|
||||
NET "IOBITS<54>" LOC = "A12" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L62N_VREF
|
||||
NET "IOBITS<55>" LOC = "B12" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L62P
|
||||
NET "IOBITS<56>" LOC = "A13" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L63N_SCP6
|
||||
NET "IOBITS<57>" LOC = "C13" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L63P_SCP7
|
||||
NET "IOBITS<58>" LOC = "A14" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L65N_SCP2
|
||||
NET "IOBITS<59>" LOC = "B14" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L65P_SCP3
|
||||
NET "IOBITS<5>" LOC = "P2" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L33P_M3DQ12
|
||||
NET "IOBITS<60>" LOC = "B16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank2 L29N_A22_M1A14
|
||||
NET "IOBITS<61>" LOC = "B15" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank2 L29P_A23_M1A13
|
||||
NET "IOBITS<62>" LOC = "C16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank2 L33N_A14_M1A4
|
||||
NET "IOBITS<63>" LOC = "C15" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank2 L33P_A15_M1A10
|
||||
NET "IOBITS<64>" LOC = "D16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank2 L31N_A18_M1A12
|
||||
NET "IOBITS<65>" LOC = "D14" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank2 L31P_A19_M1CKE
|
||||
NET "IOBITS<66>" LOC = "E16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank2 L34N_A12_M1BA2
|
||||
NET "IOBITS<67>" LOC = "E15" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank2 L34P_A13_M1WE
|
||||
NET "IOBITS<68>" LOC = "F16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank2 L35N_A10_M1A2
|
||||
NET "IOBITS<69>" LOC = "F15" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank2 L35P_A11_M1A7
|
||||
NET "IOBITS<6>" LOC = "N1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L34N_M3UDQSN
|
||||
NET "IOBITS<70>" LOC = "G16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank2 L36N_A8_M1BA1
|
||||
NET "IOBITS<71>" LOC = "G14" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank2 L36P_A9_M1BA0
|
||||
NET "IOBITS<7>" LOC = "N3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L34P_M3UDQS
|
||||
NET "IOBITS<8>" LOC = "N4" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L2N
|
||||
NET "IOBITS<9>" LOC = "M5" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank4 L2P
|
||||
NET "LEDS<3>" LOC = "B5" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L2P
|
||||
NET "LEDS<2>" LOC = "A5" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L2N
|
||||
NET "LEDS<1>" LOC = "B6" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L4P
|
||||
NET "LEDS<0>" LOC = "A6" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24 ; # Bank1 L4N
|
||||
NET "NCBE<0>" LOC = "M16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L46N_FOE_M1DQ3
|
||||
NET "NCBE<1>" LOC = "T14" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L51P_M1DQ12
|
||||
NET "NCBE<2>" LOC = "P9" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L14N_D12
|
||||
NET "NCBE<3>" LOC = "P7" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L31P_C31_D14
|
||||
NET "NDEVSEL" LOC = "T9" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L23N
|
||||
NET "NFRAME" LOC = "N9" | IOSTANDARD=LVTTL ; # Bank3 L14P_D11
|
||||
#NET "NGNT" LOC = "P4" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L63P
|
||||
NET "NINIT" LOC = "T4" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L63N
|
||||
NET "NINTA" LOC = "H16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 | PULLUP ; # Bank2 L37N_A6_M1A1
|
||||
NET "NIRDY" LOC = "J13" | IOSTANDARD=LVTTL ; # Bank2 L41P_C9_M1RAS
|
||||
NET "NLOCK" LOC = "R9" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L23P
|
||||
NET "NPERR" LOC = "T12" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L52N_M1DQ15
|
||||
NET "NREQ" LOC = "P5" | IOSTANDARD=LVTTL ; # Bank3 L49N_D4
|
||||
NET "NRST" LOC = "H13" | IOSTANDARD=LVTTL ; # Bank2 L39P_M1A3
|
||||
NET "NSERR" LOC = "T13" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L51N_M1DQ13
|
||||
NET "NSTOP" LOC = "M10" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L16N_VREF
|
||||
NET "PAR" LOC = "R12" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank2 L52P_M1DQ14
|
||||
NET "PCLK" LOC = "K12" | IOSTANDARD=LVTTL ; # Bank2 L42P_C7_M1UDM
|
||||
NET "SPICLK" LOC = "R11" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L1P_CCLK
|
||||
NET "SPICS" LOC = "T3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L65N_CSO_B
|
||||
NET "SPIDI" LOC = "P10" | IOSTANDARD=LVTTL ; # Bank3 L3P_D0_MISO1
|
||||
NET "SPIDO" LOC = "T10" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 ; # Bank3 L3N_CSI_MISO0
|
||||
NET "XCLK" LOC = "C10" | IOSTANDARD=LVTTL ; # Bank1 L37N_C12
|
||||
|
||||
NET "PCLK" TNM_NET = "PCLK";
|
||||
TIMESPEC "TS_PCLK" = PERIOD "PCLK" 30 ns HIGH 50 %;
|
||||
NET "XCLK" TNM_NET = "XCLK";
|
||||
TIMESPEC "TS_XCLK" = PERIOD "XCLK" 20 ns HIGH 50 %;
|
||||
NET "clkfx1" TNM_NET = "async_med"; # for async sserial processor clock
|
||||
NET "PCLK" TNM_NET = "async_low";
|
||||
TIMESPEC "TSLowToMed" = FROM "async_low" to "async_med" TIG;
|
||||
TIMESPEC "TSMedtoLow" = FROM "async_med" to "async_low" TIG;
|
||||
|
||||
#NET "NINIT" LOC = "R3" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 | IOSTANDARD = LVCMOS33 | PULLUP ; # Bank3 L65P_INIT_B (error on proto)
|
||||
#NET "M0" LOC = "T11" ; # Bank3 L1N_M0_CMPMISO
|
||||
#NET "M1" LOC = "N11" ; # Bank3 L13P_M1
|
||||
#NET "PWRGOOD" LOC = "T2" ; # Bank3 PROGRAM_B
|
||||
#NET "DONE" LOC = "P13" ; # Bank3 DONE
|
||||
#NET "<3.3V>" LOC = "B13" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "B4" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "B9" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "D10" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "D15" ; # Bank2 VCCO
|
||||
#NET "<3.3V>" LOC = "D2" ; # Bank4 VCCO
|
||||
#NET "<3.3V>" LOC = "D7" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "G13" ; # Bank2 VCCO
|
||||
#NET "<3.3V>" LOC = "G4" ; # Bank4 VCCO
|
||||
#NET "<3.3V>" LOC = "J15" ; # Bank2 VCCO
|
||||
#NET "<3.3V>" LOC = "J2" ; # Bank4 VCCO
|
||||
#NET "<3.3V>" LOC = "K13" ; # Bank2 VCCO
|
||||
#NET "<3.3V>" LOC = "K4" ; # Bank4 VCCO
|
||||
#NET "<3.3V>" LOC = "L11" ; # Bank3 CMPCS_B
|
||||
#NET "<3.3V>" LOC = "N10" ; # Bank3 VCCO
|
||||
#NET "<3.3V>" LOC = "N15" ; # Bank2 VCCO
|
||||
#NET "<3.3V>" LOC = "N2" ; # Bank4 VCCO
|
||||
#NET "<3.3V>" LOC = "N7" ; # Bank3 VCCO
|
||||
#NET "<3.3V>" LOC = "R13" ; # Bank2 VCCO
|
||||
#NET "<3.3V>" LOC = "R4" ; # Bank3 VCCO
|
||||
#NET "<3.3V>" LOC = "R8" ; # Bank3 VCCO
|
||||
#NET "FPGATCK" LOC = "C14" ; # Bank5 TCK
|
||||
#NET "FPGATDI" LOC = "C12" ; # Bank5 TDI
|
||||
#NET "FPGATDO" LOC = "E14" ; # Bank5 TDO
|
||||
#NET "FPGATMS" LOC = "A15" ; # Bank5 TMS
|
||||
#NET "HSWAPEN" LOC = "C4" ; # Bank1 L1P_HSWAPEN
|
||||
#NET "NC" LOC = "A1" ; # Bank6 GND
|
||||
#NET "NC" LOC = "A16" ; # Bank6 GND
|
||||
#NET "NC" LOC = "A4" ; # Bank1 L1N_VREF
|
||||
#NET "NC" LOC = "B11" ; # Bank6 GND
|
||||
#NET "NC" LOC = "B7" ; # Bank6 GND
|
||||
#NET "NC" LOC = "C5" ; # Bank1 L3N
|
||||
#NET "NC" LOC = "C6" ; # Bank1 L7N
|
||||
#NET "NC" LOC = "C8" ; # Bank1 L38N_VREF
|
||||
#NET "NC" LOC = "D11" ; # Bank1 L66P_SCP1
|
||||
#NET "NC" LOC = "D12" ; # Bank1 L66N_SCP0
|
||||
#NET "NC" LOC = "D13" ; # Bank6 GND
|
||||
#NET "NC" LOC = "D4" ; # Bank6 GND
|
||||
#NET "NC" LOC = "D5" ; # Bank1 L3P
|
||||
#NET "NC" LOC = "D6" ; # Bank1 L7P
|
||||
#NET "NC" LOC = "D8" ; # Bank1 L38P
|
||||
#NET "NC" LOC = "D9" ; # Bank1 L40N
|
||||
#NET "NC" LOC = "E10" ; # Bank1 L37P_C13
|
||||
#NET "NC" LOC = "E11" ; # Bank1 L64N_SCP4
|
||||
#NET "NC" LOC = "E12" ; # Bank2 L1N_A24_VREF
|
||||
#NET "NC" LOC = "E13" ; # Bank2 L1P_A25
|
||||
#NET "NC" LOC = "E5" ; # Bank6 VCCAUX
|
||||
#NET "NC" LOC = "E6" ; # Bank1 L5N
|
||||
#NET "NC" LOC = "E7" ; # Bank1 L36P_C15
|
||||
#NET "NC" LOC = "E8" ; # Bank1 L36N_C14
|
||||
#NET "NC" LOC = "E9" ; # Bank6 GND
|
||||
#NET "NC" LOC = "F10" ; # Bank1 L64P_SCP5
|
||||
#NET "NC" LOC = "F11" ; # Bank6 VCCAUX
|
||||
#NET "NC" LOC = "F12" ; # Bank2 L30P_A21_M1RST
|
||||
#NET "NC" LOC = "F13" ; # Bank2 L32P_A17_M1A8
|
||||
#NET "NC" LOC = "F14" ; # Bank2 L32N_A16_M1A9
|
||||
#NET "NC" LOC = "F5" ; # Bank4 L55N_M3A14
|
||||
#NET "NC" LOC = "F6" ; # Bank4 L55P_M3A13
|
||||
#NET "NC" LOC = "F7" ; # Bank1 L5P
|
||||
#NET "NC" LOC = "F8" ; # Bank6 VCCAUX
|
||||
#NET "NC" LOC = "F9" ; # Bank1 L40P
|
||||
#NET "NC" LOC = "G10" ; # Bank6 VCCAUX
|
||||
#NET "NC" LOC = "G11" ; # Bank2 L30N_A20_M1A11
|
||||
#NET "NC" LOC = "G12" ; # Bank2 L38P_A5_M1CLK
|
||||
#NET "NC" LOC = "G15" ; # Bank6 GND
|
||||
#NET "NC" LOC = "G2" ; # Bank6 GND
|
||||
#NET "NC" LOC = "G5" ; # Bank4 L51N_M3A4
|
||||
#NET "NC" LOC = "G6" ; # Bank4 L51P_M3A10
|
||||
#NET "NC" LOC = "G7" ; # Bank6 VCCINT
|
||||
#NET "NC" LOC = "G8" ; # Bank6 GND
|
||||
#NET "NC" LOC = "G9" ; # Bank6 VCCINT
|
||||
#NET "NC" LOC = "H10" ; # Bank6 VCCINT
|
||||
#NET "NC" LOC = "H11" ; # Bank2 L38N_A4_M1CLKN
|
||||
#NET "NC" LOC = "H12" ; # Bank6 GND
|
||||
#NET "NC" LOC = "H15" ; # Bank2 L37P_A7_M1A0
|
||||
#NET "NC" LOC = "H5" ; # Bank4 L43N_C22_M3CAS
|
||||
#NET "NC" LOC = "H6" ; # Bank6 VCCAUX
|
||||
#NET "NC" LOC = "H7" ; # Bank6 GND
|
||||
#NET "NC" LOC = "H8" ; # Bank6 VCCINT
|
||||
#NET "NC" LOC = "H9" ; # Bank6 GND
|
||||
#NET "NC" LOC = "J10" ; # Bank6 VCCAUX
|
||||
#NET "NC" LOC = "J11" ; # Bank2 L40P_C11_M1A5
|
||||
#NET "NC" LOC = "J12" ; # Bank2 L40N_C10_M1A6
|
||||
#NET "NC" LOC = "J5" ; # Bank6 GND
|
||||
#NET "NC" LOC = "J6" ; # Bank4 L43P_C23_M3RAS
|
||||
#NET "NC" LOC = "J7" ; # Bank6 VCCINT
|
||||
#NET "NC" LOC = "J8" ; # Bank6 GND
|
||||
#NET "NC" LOC = "J9" ; # Bank6 VCCINT
|
||||
#NET "NC" LOC = "K10" ; # Bank6 VCCINT
|
||||
#NET "NC" LOC = "K5" ; # Bank4 L47P_M3A0
|
||||
#NET "NC" LOC = "K6" ; # Bank4 L47N_M3A1
|
||||
#NET "NC" LOC = "K7" ; # Bank6 GND
|
||||
#NET "NC" LOC = "K8" ; # Bank6 VCCINT
|
||||
#NET "NC" LOC = "K9" ; # Bank6 GND
|
||||
#NET "NC" LOC = "L10" ; # Bank3 L16P
|
||||
#NET "NC" LOC = "L12" ; # Bank2 L53P
|
||||
#NET "NC" LOC = "L13" ; # Bank2 L53N_VREF
|
||||
#NET "NC" LOC = "L15" ; # Bank6 GND
|
||||
#NET "NC" LOC = "L2" ; # Bank6 GND
|
||||
#NET "NC" LOC = "L4" ; # Bank4 L45P_M3A3
|
||||
#NET "NC" LOC = "L5" ; # Bank4 L45N_M3ODT
|
||||
#NET "NC" LOC = "L6" ; # Bank6 VCCAUX
|
||||
#NET "NC" LOC = "L9" ; # Bank6 VCCAUX
|
||||
#NET "NC" LOC = "M11" ; # Bank3 L2N_CMPMOSI
|
||||
#NET "NC" LOC = "M12" ; # Bank3 L2P_CMPCLK
|
||||
#NET "NC" LOC = "M13" ; # Bank2 L74P_AWAKE
|
||||
#NET "NC" LOC = "M14" ; # Bank2 L74N_DOUT_BUS
|
||||
#NET "NC" LOC = "M8" ; # Bank6 GND
|
||||
#NET "NC" LOC = "N12" ; # Bank3 L12P_D1_MISO2
|
||||
#NET "NC" LOC = "N13" ; # Bank6 GND
|
||||
#NET "NC" LOC = "P11" ; # Bank3 L13N_D10
|
||||
#NET "NC" LOC = "P12" ; # Bank3 L12N_D2_MISO3
|
||||
#NET "NC" LOC = "P14" ; # Bank5 SUSPEND
|
||||
#NET "NC" LOC = "P3" ; # Bank6 GND
|
||||
#NET "NC" LOC = "R10" ; # Bank6 GND
|
||||
#NET "NC" LOC = "R6" ; # Bank6 GND
|
||||
#NET "NC" LOC = "T1" ; # Bank6 GND
|
||||
#NET "NC" LOC = "T16" ; # Bank6 GND
|
||||
123
5i24/configs/hostmot2/source/6i25.ucf
Executable file
123
5i24/configs/hostmot2/source/6i25.ucf
Executable file
@@ -0,0 +1,123 @@
|
||||
NET "NREQ" LOC = "P137" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<31>" LOC = "P138" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<30>" LOC = "P139" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<29>" LOC = "P140" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<28>" LOC = "P141" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<27>" LOC = "P142" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<26>" LOC = "P143" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "PCLK" LOC = "P24" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<25>" LOC = "P1" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<24>" LOC = "P2" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NCBE<3>" LOC = "P5" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<23>" LOC = "P6" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<22>" LOC = "P7" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<21>" LOC = "P8" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<20>" LOC = "P9" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<19>" LOC = "P10" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<18>" LOC = "P11" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<17>" LOC = "P12" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<16>" LOC = "P14" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NCBE<2>" LOC = "P15" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NIRDY" LOC = "P16" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NFRAME" LOC = "P17" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NDEVSEL" LOC = "P21" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NTRDY" LOC = "P22" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NLOCK" LOC = "P23" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NSTOP" LOC = "P26" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NPERR" LOC = "P27" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "PAR" LOC = "P29" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NSERR" LOC = "P30" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NCBE<1>" LOC = "P32" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<15>" LOC = "P33" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<14>" LOC = "P34" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<13>" LOC = "P35" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<12>" LOC = "P40" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<11>" LOC = "P41" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<10>" LOC = "P43" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<9>" LOC = "P44" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<8>" LOC = "P45" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NCBE<0>" LOC = "P46" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<7>" LOC = "P47" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<6>" LOC = "P48" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<5>" LOC = "P50" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<4>" LOC = "P51" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<3>" LOC = "P55" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<2>" LOC = "P56" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<1>" LOC = "P57" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "AD<0>" LOC = "P58" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "IDSEL" LOC = "P59" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NRST" LOC = "P61" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NINTA" LOC = "P62" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12 | PULLUP;
|
||||
NET "XCLK" LOC = "P133" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
|
||||
NET "IOBITS<0>" LOC = "P132" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<1>" LOC = "P131" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<2>" LOC = "P127" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<3>" LOC = "P126" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<4>" LOC = "P124" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<5>" LOC = "P123" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<6>" LOC = "P121" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<7>" LOC = "P120" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<8>" LOC = "P119" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<9>" LOC = "P118" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<10>" LOC = "P117" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<11>" LOC = "P116" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<12>" LOC = "P115" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<13>" LOC = "P114" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<14>" LOC = "P112" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<15>" LOC = "P111" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<16>" LOC = "P83" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<17>" LOC = "P105" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<18>" LOC = "P104" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<19>" LOC = "P102" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<20>" LOC = "P101" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<21>" LOC = "P100" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<22>" LOC = "P99" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<23>" LOC = "P98" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<24>" LOC = "P97" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<25>" LOC = "P95" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<26>" LOC = "P94" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<27>" LOC = "P93" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<28>" LOC = "P92" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<29>" LOC = "P88" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<30>" LOC = "P87" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<31>" LOC = "P85" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<32>" LOC = "P84" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
NET "IOBITS<33>" LOC = "P82" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=24;
|
||||
|
||||
NET "SPICS" LOC = "P38" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "SPIDO" LOC = "P64" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "SPIDI" LOC = "P65" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "SPICLK" LOC = "P70" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
|
||||
NET "LEDS<0>" LOC = "P74" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "LEDS<1>" LOC = "P75" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
|
||||
#NET "LIOBITS<0>" LOC = "P81" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "LIOBITS<1>" LOC = "P80" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "LIOBITS<2>" LOC = "P79" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "LIOBITS<3>" LOC = "P78" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "LIOBITS<4>" LOC = "P66" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "LIOBITS<5>" LOC = "P67" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "TMS" LOC = "P107" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "TDI" LOC = "P110" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "TDO" LOC = "P106" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "TCK" LOC = "P109" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "NPROGRAM" LOC = "P37" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "NGNT" LOC = "P134" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "M0" LOC = "P69" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "M1" LOC = "P60" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "HSWAPEN" LOC = "P144" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
NET "NINIT" LOC = "P39" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
#NET "NDONE" LOC = "P71" | IOSTANDARD=LVTTL | SLEW=SLOW | DRIVE=12;
|
||||
|
||||
|
||||
NET "PCLK" TNM_NET = "PCLK";
|
||||
TIMESPEC "TS_PCLK" = PERIOD "PCLK" 15 ns HIGH 50 %;
|
||||
NET "XCLK" TNM_NET = "XCLK";
|
||||
TIMESPEC "TS_XCLK" = PERIOD "XCLK" 20 ns HIGH 50 %;
|
||||
|
||||
NET "clkfx1" TNM_NET = "async_med"; # for async sserial processor clock
|
||||
NET "PCLK" TNM_NET = "async_low";
|
||||
TIMESPEC "TSLowToMed" = FROM "async_low" to "async_med" TIG;
|
||||
TIMESPEC "TSMedtoLow" = FROM "async_med" to "async_low" TIG;
|
||||
93
5i24/configs/hostmot2/source/7c80epp.ucf
Executable file
93
5i24/configs/hostmot2/source/7c80epp.ucf
Executable file
@@ -0,0 +1,93 @@
|
||||
NET "CLK" TNM_NET = "CLK";
|
||||
TIMESPEC "TS_CLK" = PERIOD "CLK" 19.9 ns HIGH 50 %;
|
||||
TIMESPEC "TS_P2P" = FROM "PADS" TO "PADS" 50 ns;
|
||||
NET "EPP_DATABUS<0>" LOC ="P30" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ; # RPIO4
|
||||
NET "EPP_DATABUS<1>" LOC ="P29" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ; # RPIO14
|
||||
NET "EPP_DATABUS<2>" LOC ="P27" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ; # RPIO15
|
||||
NET "EPP_DATABUS<3>" LOC ="P24" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ; # RPIO18
|
||||
NET "EPP_DATABUS<4>" LOC ="P23" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ; # RPIO27
|
||||
NET "EPP_DATABUS<5>" LOC ="P22" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ; # RPIO22
|
||||
NET "EPP_DATABUS<6>" LOC ="P21" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ; # RPIO23
|
||||
NET "EPP_DATABUS<7>" LOC ="P17" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ; # RPIO24
|
||||
NET "EPP_DSTROBE" LOC ="P32" | IOSTANDARD = LVTTL | PULLUP ; # RPIO3
|
||||
NET "EPP_ASTROBE" LOC ="P26" | IOSTANDARD = LVTTL | PULLUP ; # RPIO17
|
||||
NET "EPP_READ" LOC ="P33" | IOSTANDARD = LVTTL | PULLUP ; # RPIO2
|
||||
NET "EPP_WAIT" LOC ="P16" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ; # RPIO10
|
||||
NET "RECONFIG" LOC ="P67" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPICS" LOC ="P38" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPIIN" LOC ="P65" | IOSTANDARD = LVTTL ;
|
||||
NET "SPIOUT" LOC ="P64" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPICLK" LOC ="P70" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "NINIT" LOC ="P39" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ;
|
||||
NET "CLK" LOC ="P50" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "LEDS<3>" LOC ="P140" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LEDS<2>" LOC ="P141" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LEDS<1>" LOC ="P142" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LEDS<0>" LOC ="P143" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<0>" LOC ="P139" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<1>" LOC ="P138" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<2>" LOC ="P137" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<3>" LOC ="P134" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<4>" LOC ="P34" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<5>" LOC ="P35" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<6>" LOC ="P40" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<7>" LOC ="P41" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<8>" LOC ="P43" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<9>" LOC ="P44" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<10>" LOC ="P45" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<11>" LOC ="P46" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<12>" LOC ="P114" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<13>" LOC ="P112" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<14>" LOC ="P111" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<15>" LOC ="P105" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<16>" LOC ="P104" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<17>" LOC ="P102" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<18>" LOC ="P101" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<19>" LOC ="P100" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<20>" LOC ="P99" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<21>" LOC ="P98" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<22>" LOC ="P117" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<23>" LOC ="P116" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<24>" LOC ="P115" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<25>" LOC ="P118" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<26>" LOC ="P119" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<27>" LOC ="P120" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<28>" LOC ="P47" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<29>" LOC ="P48" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<30>" LOC ="P51" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<31>" LOC ="P55" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<32>" LOC ="P56" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<33>" LOC ="P57" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<34>" LOC ="P58" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<35>" LOC ="P59" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<36>" LOC ="P61" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<37>" LOC ="P97" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<38>" LOC ="P95" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<39>" LOC ="P94" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<40>" LOC ="P93" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<41>" LOC ="P92" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<42>" LOC ="P88" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<43>" LOC ="P87" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<44>" LOC ="P85" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<45>" LOC ="P84" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<46>" LOC ="P83" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<47>" LOC ="P82" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<48>" LOC ="P81" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<49>" LOC ="P80" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<50>" LOC ="P79" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<51>" LOC ="P78" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<52>" LOC ="P66" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<53>" LOC ="P62" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
|
||||
#NET "OPTS<1>" LOC ="P127" | IOSTANDARD = LVTTL ;
|
||||
#NET "OPTS<0>" LOC ="P131" | IOSTANDARD = LVTTL ;
|
||||
|
||||
#NET "DONE" LOC ="P71" ;
|
||||
#NET "RDWR" LOC ="P47" ;
|
||||
#NET "PROGRAM" LOC ="P37" ;
|
||||
#NET "M0" LOC ="P69" ;
|
||||
#NET "FPGATMS" LOC ="P107" ;
|
||||
#NET "FPGATDI" LOC ="P110" ;
|
||||
#NET "FPGATDO" LOC ="P106" ;
|
||||
#NET "FPGACLK" LOC ="P109" ;
|
||||
#NET "HOST5" LOC ="P59" ;
|
||||
91
5i24/configs/hostmot2/source/7c80spi.ucf
Executable file
91
5i24/configs/hostmot2/source/7c80spi.ucf
Executable file
@@ -0,0 +1,91 @@
|
||||
NET "CLK" TNM_NET = "CLK";
|
||||
TIMESPEC "TS_CLK" = PERIOD "CLK" 19.9 ns HIGH 50 %;
|
||||
|
||||
NET "COM_SPICLK" TNM_NET = "COM_SPICLK";
|
||||
TIMESPEC "TS_COM_SPICLK" = PERIOD "COM_SPICLK" 10 ns HIGH 50 %;
|
||||
|
||||
NET "COM_SPICLK" LOC ="P14" | IOSTANDARD = LVTTL; # RPIO11
|
||||
NET "COM_SPIIN" LOC ="P16" | IOSTANDARD = LVTTL; # RPIO9
|
||||
NET "COM_SPIOUT" LOC ="P15" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = FAST ; # RPIO10
|
||||
#NET "COM_SPICS" LOC ="P12" | IOSTANDARD = LVTTL; # proto RPIO8 open shorted to RPIO25
|
||||
NET "COM_SPICS" LOC ="P132" | IOSTANDARD = LVTTL; # prod RPIO8
|
||||
NET "TEST0" LOC ="P74" | IOSTANDARD = LVTTL;
|
||||
|
||||
NET "RECONFIG" LOC ="P67" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPICS" LOC ="P38" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPIIN" LOC ="P65" | IOSTANDARD = LVTTL ;
|
||||
NET "SPIOUT" LOC ="P64" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPICLK" LOC ="P70" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "NINIT" LOC ="P39" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ;
|
||||
NET "CLK" LOC ="P50" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "LEDS<3>" LOC ="P140" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LEDS<2>" LOC ="P141" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LEDS<1>" LOC ="P142" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LEDS<0>" LOC ="P143" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<0>" LOC ="P139" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<1>" LOC ="P138" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<2>" LOC ="P137" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<3>" LOC ="P134" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<4>" LOC ="P34" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<5>" LOC ="P35" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<6>" LOC ="P40" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<7>" LOC ="P41" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<8>" LOC ="P43" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<9>" LOC ="P44" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<10>" LOC ="P45" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<11>" LOC ="P46" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<12>" LOC ="P114" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<13>" LOC ="P112" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<14>" LOC ="P111" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<15>" LOC ="P105" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<16>" LOC ="P104" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<17>" LOC ="P102" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<18>" LOC ="P101" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<19>" LOC ="P100" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<20>" LOC ="P99" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<21>" LOC ="P98" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<22>" LOC ="P117" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<23>" LOC ="P116" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<24>" LOC ="P115" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<25>" LOC ="P118" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<26>" LOC ="P119" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<27>" LOC ="P120" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<28>" LOC ="P47" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<29>" LOC ="P48" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<30>" LOC ="P51" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<31>" LOC ="P55" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<32>" LOC ="P56" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<33>" LOC ="P57" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<34>" LOC ="P58" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<35>" LOC ="P59" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<36>" LOC ="P61" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<37>" LOC ="P97" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<38>" LOC ="P95" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<39>" LOC ="P94" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<40>" LOC ="P93" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<41>" LOC ="P92" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<42>" LOC ="P88" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<43>" LOC ="P87" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<44>" LOC ="P85" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<45>" LOC ="P84" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<46>" LOC ="P83" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<47>" LOC ="P82" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<48>" LOC ="P81" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<49>" LOC ="P80" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<50>" LOC ="P79" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<51>" LOC ="P78" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<52>" LOC ="P66" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<53>" LOC ="P62" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
|
||||
#NET "OPTS<1>" LOC ="P127" | IOSTANDARD = LVTTL ;
|
||||
#NET "OPTS<0>" LOC ="P131" | IOSTANDARD = LVTTL ;
|
||||
|
||||
#NET "DONE" LOC ="P71" ;
|
||||
#NET "RDWR" LOC ="P47" ;
|
||||
#NET "PROGRAM" LOC ="P37" ;
|
||||
#NET "M0" LOC ="P69" ;
|
||||
#NET "FPGATMS" LOC ="P107" ;
|
||||
#NET "FPGATDI" LOC ="P110" ;
|
||||
#NET "FPGATDO" LOC ="P106" ;
|
||||
#NET "FPGACLK" LOC ="P109" ;
|
||||
#NET "HOST5" LOC ="P59" ;
|
||||
96
5i24/configs/hostmot2/source/7c81epp.ucf
Executable file
96
5i24/configs/hostmot2/source/7c81epp.ucf
Executable file
@@ -0,0 +1,96 @@
|
||||
NET "CLK" TNM_NET = "CLK";
|
||||
TIMESPEC "TS_CLK" = PERIOD "CLK" 19.9 ns HIGH 50 %;
|
||||
TIMESPEC "TS_P2P" = FROM "PADS" TO "PADS" 50 ns;
|
||||
NET "EPP_DATABUS<0>" LOC ="P30" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ; # RPIO4
|
||||
NET "EPP_DATABUS<1>" LOC ="P29" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ; # RPIO14
|
||||
NET "EPP_DATABUS<2>" LOC ="P27" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ; # RPIO15
|
||||
NET "EPP_DATABUS<3>" LOC ="P24" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ; # RPIO18
|
||||
NET "EPP_DATABUS<4>" LOC ="P23" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ; # RPIO27
|
||||
NET "EPP_DATABUS<5>" LOC ="P22" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ; # RPIO22
|
||||
NET "EPP_DATABUS<6>" LOC ="P21" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ; # RPIO23
|
||||
NET "EPP_DATABUS<7>" LOC ="P17" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ; # RPIO24
|
||||
NET "EPP_DSTROBE" LOC ="P32" | IOSTANDARD = LVTTL | PULLUP ; # RPIO3
|
||||
NET "EPP_ASTROBE" LOC ="P26" | IOSTANDARD = LVTTL | PULLUP ; # RPIO17
|
||||
NET "EPP_READ" LOC ="P33" | IOSTANDARD = LVTTL | PULLUP ; # RPIO2
|
||||
NET "EPP_WAIT" LOC ="P16" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ; # RPIO10
|
||||
NET "RECONFIG" LOC ="P67" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPICS" LOC ="P38" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPIIN" LOC ="P65" | IOSTANDARD = LVTTL ;
|
||||
NET "SPIOUT" LOC ="P64" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPICLK" LOC ="P70" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "NINIT" LOC ="P39" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ;
|
||||
NET "CLK" LOC ="P50" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "LEDS<3>" LOC ="P45" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LEDS<2>" LOC ="P46" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LEDS<1>" LOC ="P47" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LEDS<0>" LOC ="P48" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<0>" LOC ="P119" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<1>" LOC ="P118" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<2>" LOC ="P117" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<3>" LOC ="P116" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<4>" LOC ="P115" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<5>" LOC ="P114" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<6>" LOC ="P112" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<7>" LOC ="P111" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<8>" LOC ="P105" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<9>" LOC ="P104" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<10>" LOC ="P102" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<11>" LOC ="P101" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<12>" LOC ="P100" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<13>" LOC ="P99" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<14>" LOC ="P98" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<15>" LOC ="P97" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<16>" LOC ="P95" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<17>" LOC ="P35" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<18>" LOC ="P43" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<19>" LOC ="P94" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<20>" LOC ="P93" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<21>" LOC ="P92" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<22>" LOC ="P88" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<23>" LOC ="P87" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<24>" LOC ="P85" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<25>" LOC ="P84" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<26>" LOC ="P83" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<27>" LOC ="P82" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<28>" LOC ="P81" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<29>" LOC ="P80" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<30>" LOC ="P79" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<31>" LOC ="P78" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<32>" LOC ="P75" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<33>" LOC ="P62" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<34>" LOC ="P61" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<35>" LOC ="P59" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<36>" LOC ="P40" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<37>" LOC ="P44" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<38>" LOC ="P143" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<39>" LOC ="P142" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<40>" LOC ="P141" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<41>" LOC ="P140" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<42>" LOC ="P139" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<43>" LOC ="P138" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<44>" LOC ="P137" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<45>" LOC ="P134" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<46>" LOC ="P133" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<47>" LOC ="P132" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<48>" LOC ="P131" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<49>" LOC ="P127" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<50>" LOC ="P126" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<51>" LOC ="P124" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<52>" LOC ="P123" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<53>" LOC ="P121" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<54>" LOC ="P120" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<55>" LOC ="P34" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<56>" LOC ="P41" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
|
||||
#NET "OPTS<1>" LOC ="P55" | IOSTANDARD = LVTTL ;
|
||||
#NET "OPTS<0>" LOC ="P51" | IOSTANDARD = LVTTL ;
|
||||
|
||||
#NET "DONE" LOC ="P71" ;
|
||||
#NET "RDWR" LOC ="P47" ;
|
||||
#NET "PROGRAM" LOC ="P37" ;
|
||||
#NET "M0" LOC ="P69" ;
|
||||
#NET "FPGATMS" LOC ="P107" ;
|
||||
#NET "FPGATDI" LOC ="P110" ;
|
||||
#NET "FPGATDO" LOC ="P106" ;
|
||||
#NET "FPGACLK" LOC ="P109" ;
|
||||
#NET "HOST5" LOC ="P59" ;
|
||||
93
5i24/configs/hostmot2/source/7c81spi.ucf
Executable file
93
5i24/configs/hostmot2/source/7c81spi.ucf
Executable file
@@ -0,0 +1,93 @@
|
||||
NET "CLK" TNM_NET = "CLK";
|
||||
TIMESPEC "TS_CLK" = PERIOD "CLK" 19.9 ns HIGH 50 %;
|
||||
|
||||
NET "COM_SPICLK" TNM_NET = "COM_SPICLK";
|
||||
TIMESPEC "TS_COM_SPICLK" = PERIOD "COM_SPICLK" 10 ns HIGH 50 %;
|
||||
|
||||
NET "COM_SPICLK" LOC ="P14" | IOSTANDARD = LVTTL; # RPIO11
|
||||
NET "COM_SPIIN" LOC ="P16" | IOSTANDARD = LVTTL; # RPIO9
|
||||
NET "COM_SPIOUT" LOC ="P15" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = FAST ; # RPIO10
|
||||
NET "COM_SPICS" LOC ="P56" | IOSTANDARD = LVTTL; # RPIO8
|
||||
NET "TEST0" LOC ="P74" | IOSTANDARD = LVTTL;
|
||||
|
||||
NET "RECONFIG" LOC ="P67" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPICS" LOC ="P38" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPIIN" LOC ="P65" | IOSTANDARD = LVTTL ;
|
||||
NET "SPIOUT" LOC ="P64" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPICLK" LOC ="P70" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "NINIT" LOC ="P39" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ;
|
||||
NET "CLK" LOC ="P50" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "LEDS<3>" LOC ="P45" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LEDS<2>" LOC ="P46" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LEDS<1>" LOC ="P47" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LEDS<0>" LOC ="P48" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<0>" LOC ="P119" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<1>" LOC ="P118" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<2>" LOC ="P117" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<3>" LOC ="P116" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<4>" LOC ="P115" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<5>" LOC ="P114" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<6>" LOC ="P112" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<7>" LOC ="P111" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<8>" LOC ="P105" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<9>" LOC ="P104" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<10>" LOC ="P102" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<11>" LOC ="P101" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<12>" LOC ="P100" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<13>" LOC ="P99" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<14>" LOC ="P98" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<15>" LOC ="P97" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<16>" LOC ="P95" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<17>" LOC ="P35" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<18>" LOC ="P43" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<19>" LOC ="P94" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<20>" LOC ="P93" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<21>" LOC ="P92" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<22>" LOC ="P88" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<23>" LOC ="P87" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<24>" LOC ="P85" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<25>" LOC ="P84" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<26>" LOC ="P83" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<27>" LOC ="P82" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<28>" LOC ="P81" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<29>" LOC ="P80" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<30>" LOC ="P79" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<31>" LOC ="P78" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<32>" LOC ="P75" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<33>" LOC ="P62" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<34>" LOC ="P61" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<35>" LOC ="P59" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<36>" LOC ="P40" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<37>" LOC ="P44" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<38>" LOC ="P143" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<39>" LOC ="P142" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<40>" LOC ="P141" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<41>" LOC ="P140" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<42>" LOC ="P139" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<43>" LOC ="P138" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<44>" LOC ="P137" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<45>" LOC ="P134" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<46>" LOC ="P133" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<47>" LOC ="P132" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<48>" LOC ="P131" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<49>" LOC ="P127" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<50>" LOC ="P126" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<51>" LOC ="P124" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<52>" LOC ="P123" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<53>" LOC ="P121" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<54>" LOC ="P120" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<55>" LOC ="P34" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<56>" LOC ="P41" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
|
||||
#NET "OPTS<1>" LOC ="P55" | IOSTANDARD = LVTTL ;
|
||||
#NET "OPTS<0>" LOC ="P51" | IOSTANDARD = LVTTL ;
|
||||
|
||||
#NET "DONE" LOC ="P71" ;
|
||||
#NET "RDWR" LOC ="P47" ;
|
||||
#NET "PROGRAM" LOC ="P37" ;
|
||||
#NET "M0" LOC ="P69" ;
|
||||
#NET "FPGATMS" LOC ="P107" ;
|
||||
#NET "FPGATDI" LOC ="P110" ;
|
||||
#NET "FPGATDO" LOC ="P106" ;
|
||||
#NET "FPGACLK" LOC ="P109" ;
|
||||
#NET "HOST5" LOC ="P59" ;
|
||||
88
5i24/configs/hostmot2/source/7i43.ucf
Executable file
88
5i24/configs/hostmot2/source/7i43.ucf
Executable file
@@ -0,0 +1,88 @@
|
||||
#NET "INIT" LOC = "p58" | IOSTANDARD = LVCMOS33
|
||||
#NET "SPIIN" LOC = "p76" | IOSTANDARD = LVCMOS33 | PULLUP
|
||||
NET "CLK" TNM_NET = "CLK";
|
||||
TIMESPEC "TS_CLK" = PERIOD "CLK" 20 ns HIGH 50 %;
|
||||
TIMESPEC "TS_P2P" = FROM "PADS" TO "PADS" 50 ns;
|
||||
#PACE: Start of Constraints generated by PACE
|
||||
|
||||
#PACE: Start of PACE I/O Pin Assignments
|
||||
NET "CLK" LOC = "p53" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "EPP_ASTROBE" LOC = "p80" | IOSTANDARD = LVCMOS33 | PULLUP ;
|
||||
NET "EPP_DATABUS<0>" LOC = "p68" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | KEEPER ;
|
||||
NET "EPP_DATABUS<1>" LOC = "p63" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | KEEPER ;
|
||||
NET "EPP_DATABUS<2>" LOC = "p60" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | KEEPER ;
|
||||
NET "EPP_DATABUS<3>" LOC = "p59" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | KEEPER ;
|
||||
NET "EPP_DATABUS<4>" LOC = "p51" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | KEEPER ;
|
||||
NET "EPP_DATABUS<5>" LOC = "p50" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | KEEPER ;
|
||||
NET "EPP_DATABUS<6>" LOC = "p47" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | KEEPER ;
|
||||
NET "EPP_DATABUS<7>" LOC = "p46" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | KEEPER ;
|
||||
NET "EPP_DSTROBE" LOC = "p79" | IOSTANDARD = LVCMOS33 | PULLUP ;
|
||||
NET "EPP_READ" LOC = "p84" | IOSTANDARD = LVCMOS33 | PULLUP ;
|
||||
NET "EPP_WAIT" LOC = "p82" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<0>" LOC = "p127" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<10>" LOC = "p11" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<11>" LOC = "p8" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<12>" LOC = "p6" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<13>" LOC = "p4" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<14>" LOC = "p135" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<15>" LOC = "p131" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<16>" LOC = "p129" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<17>" LOC = "p124" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<18>" LOC = "p122" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<19>" LOC = "p118" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<1>" LOC = "p33" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<20>" LOC = "p98" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<21>" LOC = "p100" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<22>" LOC = "p103" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<23>" LOC = "p105" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<24>" LOC = "p128" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<25>" LOC = "p32" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<26>" LOC = "p30" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<27>" LOC = "p27" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<28>" LOC = "p25" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<29>" LOC = "p23" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<2>" LOC = "p31" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<30>" LOC = "p20" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<31>" LOC = "p17" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<32>" LOC = "p14" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<33>" LOC = "p12" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<34>" LOC = "p10" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<35>" LOC = "p7" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<36>" LOC = "p5" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<37>" LOC = "p137" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<38>" LOC = "p132" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<39>" LOC = "p130" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<3>" LOC = "p28" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<40>" LOC = "p125" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<41>" LOC = "p123" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<42>" LOC = "p119" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<43>" LOC = "p116" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<44>" LOC = "p97" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<45>" LOC = "p99" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<46>" LOC = "p102" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<47>" LOC = "p104" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<4>" LOC = "p26" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<5>" LOC = "p24" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<6>" LOC = "p21" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<7>" LOC = "p18" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<8>" LOC = "p15" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<9>" LOC = "p13" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "LEDS<0>" LOC = "p96" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
|
||||
NET "LEDS<1>" LOC = "p95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
|
||||
NET "LEDS<2>" LOC = "p93" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
|
||||
NET "LEDS<3>" LOC = "p92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
|
||||
NET "LEDS<4>" LOC = "p90" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
|
||||
NET "LEDS<5>" LOC = "p89" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
|
||||
NET "LEDS<6>" LOC = "p87" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
|
||||
NET "LEDS<7>" LOC = "p86" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
|
||||
NET "PARACONFIG" LOC = "p40" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "RECONFIG" LOC = "p52" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPICLK" LOC = "p70" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPICS" LOC = "p78" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPIOUT" LOC = "p77" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "USBRD" LOC = "p55" | SLEW = SLOW | IOSTANDARD = LVCMOS33 | DRIVE = 4 ;
|
||||
NET "USBWR" LOC = "p56" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "clkfx1" TNM_NET = "async_med"; # only for async sserial
|
||||
NET "CLK" TNM_NET = "async_low";
|
||||
TIMESPEC "TSLowToMed" = FROM "async_low" to "async_med" TIG;
|
||||
TIMESPEC "TSMedtoLow" = FROM "async_med" to "async_low" TIG;
|
||||
152
5i24/configs/hostmot2/source/7i43u.ucf
Executable file
152
5i24/configs/hostmot2/source/7i43u.ucf
Executable file
@@ -0,0 +1,152 @@
|
||||
#
|
||||
# Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
# http://www.mesanet.com
|
||||
#
|
||||
# This program is is licensed under a disjunctive dual license giving you
|
||||
# the choice of one of the two following sets of free software/open source
|
||||
# licensing terms:
|
||||
#
|
||||
# * GNU General Public License (GPL), version 2.0 or later
|
||||
# * 3-clause BSD License
|
||||
#
|
||||
#
|
||||
# The GNU GPL License:
|
||||
#
|
||||
# This program is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; either version 2 of the License, or
|
||||
# (at your option) any later version.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with this program; if not, write to the Free Software
|
||||
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
#
|
||||
#
|
||||
# The 3-clause BSD License:
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
|
||||
# * Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
#
|
||||
# * Redistributions in binary form must reproduce the above
|
||||
# copyright notice, this list of conditions and the following
|
||||
# disclaimer in the documentation and/or other materials
|
||||
# provided with the distribution.
|
||||
#
|
||||
# * Neither the name of Mesa Electronics nor the names of its
|
||||
# contributors may be used to endorse or promote products
|
||||
# derived from this software without specific prior written
|
||||
# permission.
|
||||
#
|
||||
#
|
||||
# Disclaimer:
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
#NET "INIT" LOC = "p58" | IOSTANDARD = LVCMOS33
|
||||
#NET "SPIIN" LOC = "p76" | IOSTANDARD = LVCMOS33 | PULLUP
|
||||
NET "CLK" TNM_NET = "CLK";
|
||||
TIMESPEC "TS_CLK" = PERIOD "CLK" 19.5 ns HIGH 50 %;
|
||||
TIMESPEC "TS_P2P" = FROM "PADS" TO "PADS" 50 ns;
|
||||
#PACE: Start of Constraints generated by PACE
|
||||
|
||||
#PACE: Start of PACE I/O Pin Assignments
|
||||
NET "CLK" LOC = "p53" | IOSTANDARD = LVCMOS33 ;
|
||||
NET "DATABUS<0>" LOC = "p68" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | KEEPER ;
|
||||
NET "DATABUS<1>" LOC = "p63" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | KEEPER ;
|
||||
NET "DATABUS<2>" LOC = "p60" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | KEEPER ;
|
||||
NET "DATABUS<3>" LOC = "p59" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | KEEPER ;
|
||||
NET "DATABUS<4>" LOC = "p51" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | KEEPER ;
|
||||
NET "DATABUS<5>" LOC = "p50" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | KEEPER ;
|
||||
NET "DATABUS<6>" LOC = "p47" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | KEEPER ;
|
||||
NET "DATABUS<7>" LOC = "p46" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | KEEPER ;
|
||||
NET "IOBITS<0>" LOC = "p127" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<10>" LOC = "p11" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<11>" LOC = "p8" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<12>" LOC = "p6" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<13>" LOC = "p4" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<14>" LOC = "p135" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<15>" LOC = "p131" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<16>" LOC = "p129" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<17>" LOC = "p124" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<18>" LOC = "p122" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<19>" LOC = "p118" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<1>" LOC = "p33" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<20>" LOC = "p98" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<21>" LOC = "p100" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<22>" LOC = "p103" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<23>" LOC = "p105" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<24>" LOC = "p128" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<25>" LOC = "p32" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<26>" LOC = "p30" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<27>" LOC = "p27" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<28>" LOC = "p25" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<29>" LOC = "p23" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<2>" LOC = "p31" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<30>" LOC = "p20" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<31>" LOC = "p17" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<32>" LOC = "p14" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<33>" LOC = "p12" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<34>" LOC = "p10" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<35>" LOC = "p7" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<36>" LOC = "p5" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<37>" LOC = "p137" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<38>" LOC = "p132" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<39>" LOC = "p130" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<3>" LOC = "p28" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<40>" LOC = "p125" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<41>" LOC = "p123" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<42>" LOC = "p119" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<43>" LOC = "p116" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<44>" LOC = "p97" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<45>" LOC = "p99" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<46>" LOC = "p102" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<47>" LOC = "p104" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<4>" LOC = "p26" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<5>" LOC = "p24" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<6>" LOC = "p21" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<7>" LOC = "p18" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<8>" LOC = "p15" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<9>" LOC = "p13" | IOSTANDARD = LVCMOS33 | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "LEDS<0>" LOC = "p96" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
|
||||
NET "LEDS<1>" LOC = "p95" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
|
||||
NET "LEDS<2>" LOC = "p93" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
|
||||
NET "LEDS<3>" LOC = "p92" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
|
||||
NET "LEDS<4>" LOC = "p90" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
|
||||
NET "LEDS<5>" LOC = "p89" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
|
||||
NET "LEDS<6>" LOC = "p87" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
|
||||
NET "LEDS<7>" LOC = "p86" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
|
||||
NET "PARACONFIG" LOC = "p40" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "RECONFIG" LOC = "p52" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "HRECONFIG" LOC = "p44" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPICLK" LOC = "p70" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPICS" LOC = "p78" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPIIN" LOC = "p76" | IOSTANDARD = LVCMOS33 | PULLUP ;
|
||||
NET "SPIOUT" LOC = "p77" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "USB_RD" LOC = "p55" | SLEW = SLOW | IOSTANDARD = LVCMOS33 | DRIVE = 4 ;
|
||||
NET "USB_RXF" LOC = "p69" | IOSTANDARD = LVCMOS33 | PULLUP ;
|
||||
NET "USB_TXE" LOC = "p83" | IOSTANDARD = LVCMOS33 | PULLUP ;
|
||||
NET "USB_WRITE" LOC = "p56" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "clk0fx" TNM_NET = "async_med"; # For async sserial processor
|
||||
NET "CLK" TNM_NET = "async_low";
|
||||
TIMESPEC "TSLowToMed" = FROM "async_low" to "async_med" TIG;
|
||||
TIMESPEC "TSMedtoLow" = FROM "async_med" to "async_low" TIG;
|
||||
260
5i24/configs/hostmot2/source/7i61.ucf
Executable file
260
5i24/configs/hostmot2/source/7i61.ucf
Executable file
@@ -0,0 +1,260 @@
|
||||
NET "HSWAPEN_<0>" LOC = "C4" ; # Bank0 1P_HSWAPEN
|
||||
NET "***<000003>" LOC = "A4" ; # Bank0 1N_VREF
|
||||
NET "***<000002>" LOC = "B5" ; # Bank0 2P
|
||||
NET "LED<0>" LOC = "A5" ; # Bank0 2N
|
||||
NET "LED<1>" LOC = "D5" ; # Bank0 3P
|
||||
NET "LED<2>" LOC = "C5" ; # Bank0 3N
|
||||
NET "LED<3>" LOC = "B6" ; # Bank0 4P
|
||||
NET "LED<4>" LOC = "A6" ; # Bank0 4N
|
||||
NET "LED<5>" LOC = "D6" ; # Bank0 7P
|
||||
NET "LED<6>" LOC = "C6" ; # Bank0 7N
|
||||
NET "LED<7>" LOC = "D9" ; # Bank0 40N
|
||||
#NET "NC" LOC = "F7" ; # Bank0 5P
|
||||
#NET "NC" LOC = "E6" ; # Bank0 5N
|
||||
NET "IOBITS<51>" LOC = "C7" ; # Bank0 6P
|
||||
NET "IOBITS<50>" LOC = "A7" ; # Bank0 6N
|
||||
NET "IOBITS<49>" LOC = "E7" ; # Bank0 36P_C15
|
||||
NET "IOBITS<48>" LOC = "E8" ; # Bank0 36N_C14
|
||||
NET "IOBITS<53>" LOC = "B8" ; # Bank0 33P
|
||||
NET "IOBITS<52>" LOC = "A8" ; # Bank0 33N
|
||||
NET "IOBITS<55>" LOC = "D8" ; # Bank0 38P
|
||||
NET "IOBITS<54>" LOC = "C8" ; # Bank0 38N_VREF
|
||||
NET "IOBITS<57>" LOC = "C9" ; # Bank0 34P_C19
|
||||
NET "IOBITS<56>" LOC = "A9" ; # Bank0 34N_C18
|
||||
#NET "NC" LOC = "F9" ; # Bank0 40P
|
||||
NET "IOBITS<59>" LOC = "B10" ; # Bank0 35P_C17
|
||||
NET "IOBITS<58>" LOC = "A10" ; # Bank0 35N_C16
|
||||
NET "IOBITS<61>" LOC = "E10" ; # Bank0 37P_C13
|
||||
NET "IOBITS<60>" LOC = "C10" ; # Bank0 37N_C12
|
||||
#NET "NC" LOC = "F10" ; # Bank0 64P_SCP5
|
||||
#NET "NC" LOC = "E11" ; # Bank0 64N_SCP4
|
||||
NET "IOBITS<63>" LOC = "C11" ; # Bank0 39P
|
||||
NET "IOBITS<62>" LOC = "A11" ; # Bank0 39N
|
||||
NET "IOBITS<65>" LOC = "D11" ; # Bank0 66P_SCP1
|
||||
NET "IOBITS<64>" LOC = "D12" ; # Bank0 66N_SCP0
|
||||
NET "IOBITS<67>" LOC = "B12" ; # Bank0 62P
|
||||
NET "IOBITS<66>" LOC = "A12" ; # Bank0 62N_VREF
|
||||
NET "IOBITS<69>" LOC = "C13" ; # Bank0 63P_SCP7
|
||||
NET "IOBITS<68>" LOC = "A13" ; # Bank0 63N_SCP6
|
||||
NET "IOBITS<71>" LOC = "B14" ; # Bank0 65P_SCP3
|
||||
NET "IOBITS<70>" LOC = "A14" ; # Bank0 65N_SCP2
|
||||
#NET "<3.3V>" LOC = "B13" ; # Bank0 CCO
|
||||
#NET "<3.3V>" LOC = "B4" ; # Bank0 CCO
|
||||
#NET "<3.3V>" LOC = "B9" ; # Bank0 CCO
|
||||
#NET "<3.3V>" LOC = "D10" ; # Bank0 CCO
|
||||
#NET "<3.3V>" LOC = "D7" ; # Bank0 CCO
|
||||
NET "IOBITS<75>" LOC = "B15" ; # Bank1 29P_A23_M1A13
|
||||
NET "IOBITS<74>" LOC = "B16" ; # Bank1 29N_A22_M1A14
|
||||
NET "IOBITS<77>" LOC = "C15" ; # Bank1 33P_A15_M1A10
|
||||
NET "IOBITS<76>" LOC = "C16" ; # Bank1 33N_A14_M1A4
|
||||
NET "IOBITS<79>" LOC = "D14" ; # Bank1 31P_A19_M1CKE
|
||||
NET "IOBITS<78>" LOC = "D16" ; # Bank1 31N_A18_M1A12
|
||||
NET "IOBITS<81>" LOC = "E15" ; # Bank1 34P_A13_M1WE
|
||||
NET "IOBITS<80>" LOC = "E16" ; # Bank1 34N_A12_M1BA2
|
||||
NET "IOBITS<83>" LOC = "E13" ; # Bank1 1P_A25
|
||||
NET "IOBITS<82>" LOC = "E12" ; # Bank1 1N_A24_VREF
|
||||
NET "IOBITS<85>" LOC = "F15" ; # Bank1 35P_A11_M1A7
|
||||
NET "IOBITS<84>" LOC = "F16" ; # Bank1 35N_A10_M1A2
|
||||
NET "IOBITS<87>" LOC = "F13" ; # Bank1 32P_A17_M1A8
|
||||
NET "IOBITS<86>" LOC = "F14" ; # Bank1 32N_A16_M1A9
|
||||
#NET "NC" LOC = "F12" ; # Bank1 30P_A21_M1RST
|
||||
#NET "NC" LOC = "G11" ; # Bank1 30N_A20_M1A11
|
||||
NET "IOBITS<89>" LOC = "G14" ; # Bank1 36P_A9_M1BA0
|
||||
NET "IOBITS<88>" LOC = "G16" ; # Bank1 36N_A8_M1BA1
|
||||
NET "IOBITS<91>" LOC = "G12" ; # Bank1 38P_A5_M1CLK
|
||||
NET "IOBITS<90>" LOC = "H11" ; # Bank1 38N_A4_M1CLKN
|
||||
NET "IOBITS<93>" LOC = "H15" ; # Bank1 37P_A7_M1A0
|
||||
NET "IOBITS<92>" LOC = "H16" ; # Bank1 37N_A6_M1A1
|
||||
#NET "NC" LOC = "H13" ; # Bank1 39P_M1A3
|
||||
#NET "NC" LOC = "H14" ; # Bank1 39N_M1ODT
|
||||
NET "IOBITS<73>" LOC = "J14" ; # Bank1 43P_C5_M1DQ4
|
||||
NET "IOBITS<72>" LOC = "J16" ; # Bank1 43N_C4_M1DQ5
|
||||
NET "IOBITS<95>" LOC = "J13" ; # Bank1 41P_C9_M1RAS
|
||||
NET "IOBITS<94>" LOC = "K14" ; # Bank1 41N_C8_M1CAS
|
||||
#NET "NC" LOC = "J11" ; # Bank1 40P_C11_M1A5
|
||||
#NET "NC" LOC = "J12" ; # Bank1 40N_C10_M1A6
|
||||
NET "HOST<33>" LOC = "K15" ; # Bank1 44P_A3_M1DQ6
|
||||
NET "HOST<32>" LOC = "K16" ; # Bank1 44N_A2_M1DQ7
|
||||
NET "HOSTCLK" LOC = "K12" ; # Bank1 42P_C7_M1UDM
|
||||
#NET "NC" LOC = "K11" ; # Bank1 42N_C6_M1LDM
|
||||
NET "HOST<31>" LOC = "L14" ; # Bank1 47P_FWE_M1DQ0
|
||||
NET "HOST<30>" LOC = "L16" ; # Bank1 47N_LDC_M1DQ1
|
||||
#NET "NC" LOC = "L12" ; # Bank1 53P
|
||||
#NET "NC" LOC = "L13" ; # Bank1 53N_VREF
|
||||
NET "HOST<29>" LOC = "M15" ; # Bank1 46P_FCS_M1DQ2
|
||||
NET "HOST<28>" LOC = "M16" ; # Bank1 46N_FOE_M1DQ3
|
||||
#NET "NC" LOC = "M13" ; # Bank1 74P_AWAKE
|
||||
#NET "NC" LOC = "M14" ; # Bank1 74N_DOUT_BUS
|
||||
NET "HOST<27>" LOC = "N14" ; # Bank1 45P_A1_M1LDQS
|
||||
NET "HOST<26>" LOC = "N16" ; # Bank1 45N_A0_M1LDQS
|
||||
NET "HOST<25>" LOC = "P15" ; # Bank1 48P_HDC_M1DQ8
|
||||
NET "HOST<24>" LOC = "P16" ; # Bank1 48N_M1DQ9
|
||||
NET "HOST<23>" LOC = "R15" ; # Bank1 49P_M1DQ10
|
||||
NET "HOST<22>" LOC = "R16" ; # Bank1 49N_M1DQ11
|
||||
NET "HOST<21>" LOC = "R14" ; # Bank1 50P_M1UDQS
|
||||
NET "HOST<20>" LOC = "T15" ; # Bank1 50N_M1UDQSN
|
||||
NET "HOST<19>" LOC = "T14" ; # Bank1 51P_M1DQ12
|
||||
NET "HOST<18>" LOC = "T13" ; # Bank1 51N_M1DQ13
|
||||
NET "HOST<17>" LOC = "R12" ; # Bank1 52P_M1DQ14
|
||||
NET "HOST<16>" LOC = "T12" ; # Bank1 52N_M1DQ15
|
||||
#NET "<3.3V>" LOC = "D15" ; # Bank1 CCO
|
||||
#NET "<3.3V>" LOC = "G13" ; # Bank1 CCO
|
||||
#NET "<3.3V>" LOC = "J15" ; # Bank1 CCO
|
||||
#NET "<3.3V>" LOC = "K13" ; # Bank1 CCO
|
||||
#NET "<3.3V>" LOC = "N15" ; # Bank1 CCO
|
||||
#NET "<3.3V>" LOC = "R13" ; # Bank1 CCO
|
||||
#NET "<3.3V>" LOC = "L11" ; # Bank2 MPCS_B
|
||||
NET "DONE" LOC = "P13" ; # Bank2 ONE
|
||||
NET "D<1>" LOC = "N12" ; # Bank2 12P_D1_MISO2
|
||||
NET "D<2>" LOC = "P12" ; # Bank2 12N_D2_MISO3
|
||||
#NET "NC" LOC = "M12" ; # Bank2 2P_CMPCLK
|
||||
#NET "NC" LOC = "M11" ; # Bank2 2N_CMPMOSI
|
||||
NET "***<000004>" LOC = "R11" ; # Bank2 1P_CCLK
|
||||
NET "M<0>" LOC = "T11" ; # Bank2 1N_M0_CMPMISO
|
||||
NET "M<1>" LOC = "N11" ; # Bank2 13P_M1
|
||||
#NET "NC" LOC = "P11" ; # Bank2 13N_D10
|
||||
NET "SDIN" LOC = "P10" ; # Bank2 3P_D0_MISO1
|
||||
NET "SDOUT" LOC = "T10" ; # Bank2 3N_CSI_MISO0
|
||||
#NET "NC" LOC = "L10" ; # Bank2 16P
|
||||
NET "/RECONFIG" LOC = "M10" ; # Bank2 16N_VREF
|
||||
NET "HOST<15>" LOC = "R9" ; # Bank2 23P
|
||||
NET "HOST<14>" LOC = "T9" ; # Bank2 23N
|
||||
NET "HOST<13>" LOC = "N9" ; # Bank2 14P_D11
|
||||
NET "HOST<12>" LOC = "P9" ; # Bank2 14N_D12
|
||||
NET "HOST<11>" LOC = "M9" ; # Bank2 29P_C3
|
||||
NET "HOST<10>" LOC = "N8" ; # Bank2 29N_C2
|
||||
NET "HOST<9>" LOC = "P8" ; # Bank2 30P_C1_D13
|
||||
NET "HOST<8>" LOC = "T8" ; # Bank2 30N_C0_USRCC
|
||||
NET "D<5>" LOC = "L8" ; # Bank2 62P_D5
|
||||
NET "D<6>" LOC = "L7" ; # Bank2 62N_D6
|
||||
NET "HOST<7>" LOC = "R7" ; # Bank2 32P_C29
|
||||
NET "HOST<6>" LOC = "T7" ; # Bank2 32N_C28
|
||||
NET "D<0>" LOC = "P7" ; # Bank2 31P_C31_D14
|
||||
NET "FPGACLK" LOC = "M7" ; # Bank2 31N_C30_D15
|
||||
NET "HOST<5>" LOC = "P6" ; # Bank2 47P
|
||||
NET "HOST<4>" LOC = "T6" ; # Bank2 47N
|
||||
NET "HOST<3>" LOC = "M6" ; # Bank2 64P_D8
|
||||
NET "HOST<2>" LOC = "N6" ; # Bank2 64N_D9
|
||||
NET "D<7>" LOC = "R5" ; # Bank2 48P_D7
|
||||
NET "RDWR" LOC = "T5" ; # Bank2 48N_RDWR_VREF
|
||||
NET "D<3>" LOC = "N5" ; # Bank2 49P_D3
|
||||
NET "D<4>" LOC = "P5" ; # Bank2 49N_D4
|
||||
NET "HOST<1>" LOC = "P4" ; # Bank2 63P
|
||||
NET "HOST<0>" LOC = "T4" ; # Bank2 63N
|
||||
NET "/INIT" LOC = "R3" ; # Bank2 65P_INIT_B
|
||||
NET "/CSO" LOC = "T3" ; # Bank2 65N_CSO_B
|
||||
NET "/PROGRAM" LOC = "T2" ; # Bank2 ROGRAM_B
|
||||
#NET "<3.3V>" LOC = "N10" ; # Bank2 CCO
|
||||
#NET "<3.3V>" LOC = "N7" ; # Bank2 CCO
|
||||
#NET "<3.3V>" LOC = "R4" ; # Bank2 CCO
|
||||
#NET "<3.3V>" LOC = "R8" ; # Bank2 CCO
|
||||
NET "IOBITS<3>" LOC = "R2" ; # Bank3 32P_M3DQ14
|
||||
NET "IOBITS<2>" LOC = "R1" ; # Bank3 32N_M3DQ15
|
||||
NET "IOBITS<5>" LOC = "P2" ; # Bank3 33P_M3DQ12
|
||||
NET "IOBITS<4>" LOC = "P1" ; # Bank3 33N_M3DQ13
|
||||
NET "IOBITS<7>" LOC = "N3" ; # Bank3 34P_M3UDQS
|
||||
NET "IOBITS<6>" LOC = "N1" ; # Bank3 34N_M3UDQSN
|
||||
NET "IOBITS<9>" LOC = "M5" ; # Bank3 2P
|
||||
NET "IOBITS<8>" LOC = "N4" ; # Bank3 2N
|
||||
NET "IOBITS<11>" LOC = "M2" ; # Bank3 35P_M3DQ10
|
||||
NET "IOBITS<10>" LOC = "M1" ; # Bank3 35N_M3DQ11
|
||||
NET "IOBITS<13>" LOC = "M4" ; # Bank3 1P
|
||||
NET "IOBITS<12>" LOC = "M3" ; # Bank3 1N_VREF
|
||||
NET "IOBITS<15>" LOC = "L3" ; # Bank3 36P_M3DQ8
|
||||
NET "IOBITS<14>" LOC = "L1" ; # Bank3 36N_M3DQ9
|
||||
NET "IOBITS<17>" LOC = "L4" ; # Bank3 45P_M3A3
|
||||
NET "IOBITS<16>" LOC = "L5" ; # Bank3 45N_M3ODT
|
||||
NET "IOBITS<19>" LOC = "K2" ; # Bank3 37P_M3DQ0
|
||||
NET "IOBITS<18>" LOC = "K1" ; # Bank3 37N_M3DQ1
|
||||
NET "IOBITS<1>" LOC = "K3" ; # Bank3 42P_C25_M3UDM
|
||||
NET "IOBITS<0>" LOC = "J4" ; # Bank3 42N_C24_M3LDM
|
||||
#NET "NC" LOC = "K5" ; # Bank3 47P_M3A0
|
||||
#NET "NC" LOC = "K6" ; # Bank3 47N_M3A1
|
||||
NET "IOBITS<21>" LOC = "J3" ; # Bank3 38P_M3DQ2
|
||||
NET "IOBITS<20>" LOC = "J1" ; # Bank3 38N_M3DQ3
|
||||
NET "IOBITS<25>" LOC = "J6" ; # Bank3 43P_C23_M3RAS
|
||||
NET "IOBITS<24>" LOC = "H5" ; # Bank3 43N_C22_M3CAS
|
||||
NET "IOBITS<23>" LOC = "H2" ; # Bank3 39P_M3LDQS
|
||||
NET "IOBITS<22>" LOC = "H1" ; # Bank3 39N_M3LDQSN
|
||||
NET "IOBITS<27>" LOC = "H4" ; # Bank3 44P_C21_M3A5
|
||||
NET "IOBITS<26>" LOC = "H3" ; # Bank3 44N_C20_M3A6
|
||||
NET "IOBITS<29>" LOC = "G3" ; # Bank3 40P_M3DQ6
|
||||
NET "IOBITS<28>" LOC = "G1" ; # Bank3 40N_M3DQ7
|
||||
#NET "NC" LOC = "G6" ; # Bank3 51P_M3A10
|
||||
#NET "NC" LOC = "G5" ; # Bank3 51N_M3A4
|
||||
NET "IOBITS<31>" LOC = "F2" ; # Bank3 41P_C27_M3DQ4
|
||||
NET "IOBITS<30>" LOC = "F1" ; # Bank3 41N_C26_M3DQ5
|
||||
NET "IOBITS<33>" LOC = "F4" ; # Bank3 53P_M3CKE
|
||||
NET "IOBITS<32>" LOC = "F3" ; # Bank3 53N_M3A12
|
||||
#NET "NC" LOC = "F6" ; # Bank3 55P_M3A13
|
||||
#NET "NC" LOC = "F5" ; # Bank3 55N_M3A14
|
||||
NET "IOBITS<35>" LOC = "E2" ; # Bank3 46P_M3CLK
|
||||
NET "IOBITS<34>" LOC = "E1" ; # Bank3 46N_M3CLKN
|
||||
NET "IOBITS<37>" LOC = "E4" ; # Bank3 54P_M3RESET
|
||||
NET "IOBITS<36>" LOC = "E3" ; # Bank3 54N_M3A11
|
||||
NET "IOBITS<39>" LOC = "D3" ; # Bank3 49P_M3A7
|
||||
NET "IOBITS<38>" LOC = "D1" ; # Bank3 49N_M3A2
|
||||
NET "IOBITS<41>" LOC = "C1" ; # Bank3 50P_M3WE
|
||||
NET "IOBITS<40>" LOC = "B1" ; # Bank3 50N_M3BA2
|
||||
NET "IOBITS<43>" LOC = "C3" ; # Bank3 48P_M3BA0
|
||||
NET "IOBITS<42>" LOC = "C2" ; # Bank3 48N_M3BA1
|
||||
NET "IOBITS<45>" LOC = "B2" ; # Bank3 52P_M3A8
|
||||
NET "IOBITS<44>" LOC = "A2" ; # Bank3 52N_M3A9
|
||||
NET "IOBITS<47>" LOC = "B3" ; # Bank3 83P
|
||||
NET "IOBITS<46>" LOC = "A3" ; # Bank3 83N_VREF
|
||||
#NET "<3.3V>" LOC = "D2" ; # Bank3 CCO
|
||||
#NET "<3.3V>" LOC = "G4" ; # Bank3 CCO
|
||||
#NET "<3.3V>" LOC = "J2" ; # Bank3 CCO
|
||||
#NET "<3.3V>" LOC = "K4" ; # Bank3 CCO
|
||||
#NET "<3.3V>" LOC = "N2" ; # Bank3 CCO
|
||||
NET "FPGATCK" LOC = "C14" ; # Bank4 CK
|
||||
NET "FPGATDI" LOC = "C12" ; # Bank4 DI
|
||||
NET "FPGATMS" LOC = "A15" ; # Bank4 MS
|
||||
NET "FPGATDO" LOC = "E14" ; # Bank4 DO
|
||||
#NET "NC" LOC = "P14" ; # Bank4 USPEND
|
||||
#NET "GND" LOC = "A1" ; # Bank5 ND
|
||||
#NET "GND" LOC = "A16" ; # Bank5 ND
|
||||
#NET "GND" LOC = "B11" ; # Bank5 ND
|
||||
#NET "GND" LOC = "B7" ; # Bank5 ND
|
||||
#NET "GND" LOC = "D13" ; # Bank5 ND
|
||||
#NET "GND" LOC = "D4" ; # Bank5 ND
|
||||
#NET "GND" LOC = "E9" ; # Bank5 ND
|
||||
#NET "GND" LOC = "G15" ; # Bank5 ND
|
||||
#NET "GND" LOC = "G2" ; # Bank5 ND
|
||||
#NET "GND" LOC = "G8" ; # Bank5 ND
|
||||
#NET "GND" LOC = "H12" ; # Bank5 ND
|
||||
#NET "GND" LOC = "H7" ; # Bank5 ND
|
||||
#NET "GND" LOC = "H9" ; # Bank5 ND
|
||||
#NET "GND" LOC = "J5" ; # Bank5 ND
|
||||
#NET "GND" LOC = "J8" ; # Bank5 ND
|
||||
#NET "GND" LOC = "K7" ; # Bank5 ND
|
||||
#NET "GND" LOC = "K9" ; # Bank5 ND
|
||||
#NET "GND" LOC = "L15" ; # Bank5 ND
|
||||
#NET "GND" LOC = "L2" ; # Bank5 ND
|
||||
#NET "GND" LOC = "M8" ; # Bank5 ND
|
||||
#NET "GND" LOC = "N13" ; # Bank5 ND
|
||||
#NET "GND" LOC = "P3" ; # Bank5 ND
|
||||
#NET "GND" LOC = "R10" ; # Bank5 ND
|
||||
#NET "GND" LOC = "R6" ; # Bank5 ND
|
||||
#NET "GND" LOC = "T1" ; # Bank5 ND
|
||||
#NET "GND" LOC = "T16" ; # Bank5 ND
|
||||
#NET "<3.3V>" LOC = "E5" ; # Bank5 CCAUX
|
||||
#NET "<3.3V>" LOC = "F11" ; # Bank5 CCAUX
|
||||
#NET "<3.3V>" LOC = "F8" ; # Bank5 CCAUX
|
||||
#NET "<3.3V>" LOC = "G10" ; # Bank5 CCAUX
|
||||
#NET "<3.3V>" LOC = "H6" ; # Bank5 CCAUX
|
||||
#NET "<3.3V>" LOC = "J10" ; # Bank5 CCAUX
|
||||
#NET "<3.3V>" LOC = "L6" ; # Bank5 CCAUX
|
||||
#NET "<3.3V>" LOC = "L9" ; # Bank5 CCAUX
|
||||
#NET "<1.2V>" LOC = "G7" ; # Bank5 CCINT
|
||||
#NET "<1.2V>" LOC = "G9" ; # Bank5 CCINT
|
||||
#NET "<1.2V>" LOC = "H10" ; # Bank5 CCINT
|
||||
#NET "<1.2V>" LOC = "H8" ; # Bank5 CCINT
|
||||
#NET "<1.2V>" LOC = "J7" ; # Bank5 CCINT
|
||||
#NET "<1.2V>" LOC = "J9" ; # Bank5 CCINT
|
||||
#NET "<1.2V>" LOC = "K10" ; # Bank5 CCINT
|
||||
#NET "<1.2V>" LOC = "K8" ; # Bank5 CCINT
|
||||
NET "clkfx1" TNM_NET = "async_med"; # only for async sserial
|
||||
NET "CLK" TNM_NET = "async_low";
|
||||
TIMESPEC "TSLowToMed" = FROM "async_low" to "async_med" TIG;
|
||||
TIMESPEC "TSMedtoLow" = FROM "async_med" to "async_low" TIG;
|
||||
275
5i24/configs/hostmot2/source/7i61u.ucf
Executable file
275
5i24/configs/hostmot2/source/7i61u.ucf
Executable file
@@ -0,0 +1,275 @@
|
||||
NET "CLK" TNM_NET = "CLK";
|
||||
TIMESPEC "TS_CLK" = PERIOD "CLK" 19.5 ns HIGH 50 %;
|
||||
TIMESPEC "TS_P2P" = FROM "PADS" TO "PADS" 50 ns;
|
||||
|
||||
|
||||
NET "LEDS<7>" LOC = "A5" ; # Bank0 2N backwards in schematic!
|
||||
NET "LEDS<6>" LOC = "D5" ; # Bank0 3P
|
||||
NET "LEDS<5>" LOC = "C5" ; # Bank0 3N
|
||||
NET "LEDS<4>" LOC = "B6" ; # Bank0 4P
|
||||
NET "LEDS<3>" LOC = "A6" ; # Bank0 4N
|
||||
NET "LEDS<2>" LOC = "D6" ; # Bank0 7P
|
||||
NET "LEDS<1>" LOC = "C6" ; # Bank0 7N
|
||||
NET "LEDS<0>" LOC = "D9" ; # Bank0 40N
|
||||
|
||||
NET "IOBITS<0>" LOC = "J4" ; # Bank3 42N_C24_M3LDM
|
||||
NET "IOBITS<1>" LOC = "K3" ; # Bank3 42P_C25_M3UDM
|
||||
NET "IOBITS<2>" LOC = "R1" ; # Bank3 32N_M3DQ15
|
||||
NET "IOBITS<3>" LOC = "R2" ; # Bank3 32P_M3DQ14
|
||||
NET "IOBITS<4>" LOC = "P1" ; # Bank3 33N_M3DQ13
|
||||
NET "IOBITS<5>" LOC = "P2" ; # Bank3 33P_M3DQ12
|
||||
NET "IOBITS<6>" LOC = "N1" ; # Bank3 34N_M3UDQSN
|
||||
NET "IOBITS<7>" LOC = "N3" ; # Bank3 34P_M3UDQS
|
||||
NET "IOBITS<8>" LOC = "N4" ; # Bank3 2N
|
||||
NET "IOBITS<9>" LOC = "M5" ; # Bank3 2P
|
||||
NET "IOBITS<10>" LOC = "M1" ; # Bank3 35N_M3DQ11
|
||||
NET "IOBITS<11>" LOC = "M2" ; # Bank3 35P_M3DQ10
|
||||
NET "IOBITS<12>" LOC = "M3" ; # Bank3 1N_VREF
|
||||
NET "IOBITS<13>" LOC = "M4" ; # Bank3 1P
|
||||
NET "IOBITS<14>" LOC = "L1" ; # Bank3 36N_M3DQ9
|
||||
NET "IOBITS<15>" LOC = "L3" ; # Bank3 36P_M3DQ8
|
||||
NET "IOBITS<16>" LOC = "L5" ; # Bank3 45N_M3ODT
|
||||
NET "IOBITS<17>" LOC = "L4" ; # Bank3 45P_M3A3
|
||||
NET "IOBITS<18>" LOC = "K1" ; # Bank3 37N_M3DQ1
|
||||
NET "IOBITS<19>" LOC = "K2" ; # Bank3 37P_M3DQ0
|
||||
NET "IOBITS<20>" LOC = "J1" ; # Bank3 38N_M3DQ3
|
||||
NET "IOBITS<21>" LOC = "J3" ; # Bank3 38P_M3DQ2
|
||||
NET "IOBITS<22>" LOC = "H1" ; # Bank3 39N_M3LDQSN
|
||||
NET "IOBITS<23>" LOC = "H2" ; # Bank3 39P_M3LDQS
|
||||
NET "IOBITS<24>" LOC = "H5" ; # Bank3 43N_C22_M3CAS
|
||||
NET "IOBITS<25>" LOC = "J6" ; # Bank3 43P_C23_M3RAS
|
||||
NET "IOBITS<26>" LOC = "H3" ; # Bank3 44N_C20_M3A6
|
||||
NET "IOBITS<27>" LOC = "H4" ; # Bank3 44P_C21_M3A5
|
||||
NET "IOBITS<28>" LOC = "G1" ; # Bank3 40N_M3DQ7
|
||||
NET "IOBITS<29>" LOC = "G3" ; # Bank3 40P_M3DQ6
|
||||
NET "IOBITS<30>" LOC = "F1" ; # Bank3 41N_C26_M3DQ5
|
||||
NET "IOBITS<31>" LOC = "F2" ; # Bank3 41P_C27_M3DQ4
|
||||
NET "IOBITS<32>" LOC = "F3" ; # Bank3 53N_M3A12
|
||||
NET "IOBITS<33>" LOC = "F4" ; # Bank3 53P_M3CKE
|
||||
NET "IOBITS<34>" LOC = "E1" ; # Bank3 46N_M3CLKN
|
||||
NET "IOBITS<35>" LOC = "E2" ; # Bank3 46P_M3CLK
|
||||
NET "IOBITS<36>" LOC = "E3" ; # Bank3 54N_M3A11
|
||||
NET "IOBITS<37>" LOC = "E4" ; # Bank3 54P_M3RESET
|
||||
NET "IOBITS<38>" LOC = "D1" ; # Bank3 49N_M3A2
|
||||
NET "IOBITS<39>" LOC = "D3" ; # Bank3 49P_M3A7
|
||||
NET "IOBITS<40>" LOC = "B1" ; # Bank3 50N_M3BA2
|
||||
NET "IOBITS<41>" LOC = "C1" ; # Bank3 50P_M3WE
|
||||
NET "IOBITS<42>" LOC = "C2" ; # Bank3 48N_M3BA1
|
||||
NET "IOBITS<43>" LOC = "C3" ; # Bank3 48P_M3BA0
|
||||
NET "IOBITS<44>" LOC = "A2" ; # Bank3 52N_M3A9
|
||||
NET "IOBITS<45>" LOC = "B2" ; # Bank3 52P_M3A8
|
||||
NET "IOBITS<46>" LOC = "A3" ; # Bank3 83N_VREF
|
||||
NET "IOBITS<47>" LOC = "B3" ; # Bank3 83P
|
||||
NET "IOBITS<48>" LOC = "E8" ; # Bank0 36N_C14
|
||||
NET "IOBITS<49>" LOC = "E7" ; # Bank0 36P_C15
|
||||
NET "IOBITS<50>" LOC = "A7" ; # Bank0 6N
|
||||
NET "IOBITS<51>" LOC = "C7" ; # Bank0 6P
|
||||
NET "IOBITS<52>" LOC = "A8" ; # Bank0 33N
|
||||
NET "IOBITS<53>" LOC = "B8" ; # Bank0 33P
|
||||
NET "IOBITS<54>" LOC = "C8" ; # Bank0 38N_VREF
|
||||
NET "IOBITS<55>" LOC = "D8" ; # Bank0 38P
|
||||
NET "IOBITS<56>" LOC = "A9" ; # Bank0 34N_C18
|
||||
NET "IOBITS<57>" LOC = "C9" ; # Bank0 34P_C19
|
||||
NET "IOBITS<58>" LOC = "A10" ; # Bank0 35N_C16
|
||||
NET "IOBITS<59>" LOC = "B10" ; # Bank0 35P_C17
|
||||
NET "IOBITS<60>" LOC = "C10" ; # Bank0 37N_C12
|
||||
NET "IOBITS<61>" LOC = "E10" ; # Bank0 37P_C13
|
||||
NET "IOBITS<62>" LOC = "A11" ; # Bank0 39N
|
||||
NET "IOBITS<63>" LOC = "C11" ; # Bank0 39P
|
||||
NET "IOBITS<64>" LOC = "D12" ; # Bank0 66N_SCP0
|
||||
NET "IOBITS<65>" LOC = "D11" ; # Bank0 66P_SCP1
|
||||
NET "IOBITS<66>" LOC = "A12" ; # Bank0 62N_VREF
|
||||
NET "IOBITS<67>" LOC = "B12" ; # Bank0 62P
|
||||
NET "IOBITS<68>" LOC = "A13" ; # Bank0 63N_SCP6
|
||||
NET "IOBITS<69>" LOC = "C13" ; # Bank0 63P_SCP7
|
||||
NET "IOBITS<70>" LOC = "A14" ; # Bank0 65N_SCP2
|
||||
NET "IOBITS<71>" LOC = "B14" ; # Bank0 65P_SCP3
|
||||
NET "IOBITS<72>" LOC = "J16" ; # Bank1 43N_C4_M1DQ5
|
||||
NET "IOBITS<73>" LOC = "J14" ; # Bank1 43P_C5_M1DQ4
|
||||
NET "IOBITS<74>" LOC = "B16" ; # Bank1 29N_A22_M1A14
|
||||
NET "IOBITS<75>" LOC = "B15" ; # Bank1 29P_A23_M1A13
|
||||
NET "IOBITS<76>" LOC = "C16" ; # Bank1 33N_A14_M1A4
|
||||
NET "IOBITS<77>" LOC = "C15" ; # Bank1 33P_A15_M1A10
|
||||
NET "IOBITS<78>" LOC = "D16" ; # Bank1 31N_A18_M1A12
|
||||
NET "IOBITS<79>" LOC = "D14" ; # Bank1 31P_A19_M1CKE
|
||||
NET "IOBITS<80>" LOC = "E16" ; # Bank1 34N_A12_M1BA2
|
||||
NET "IOBITS<81>" LOC = "E15" ; # Bank1 34P_A13_M1WE
|
||||
NET "IOBITS<82>" LOC = "E12" ; # Bank1 1N_A24_VREF
|
||||
NET "IOBITS<83>" LOC = "E13" ; # Bank1 1P_A25
|
||||
NET "IOBITS<84>" LOC = "F16" ; # Bank1 35N_A10_M1A2
|
||||
NET "IOBITS<86>" LOC = "F14" ; # Bank1 32N_A16_M1A9
|
||||
NET "IOBITS<85>" LOC = "F15" ; # Bank1 35P_A11_M1A7
|
||||
NET "IOBITS<87>" LOC = "F13" ; # Bank1 32P_A17_M1A8
|
||||
NET "IOBITS<88>" LOC = "G16" ; # Bank1 36N_A8_M1BA1
|
||||
NET "IOBITS<89>" LOC = "G14" ; # Bank1 36P_A9_M1BA0
|
||||
NET "IOBITS<90>" LOC = "H11" ; # Bank1 38N_A4_M1CLKN
|
||||
NET "IOBITS<91>" LOC = "G12" ; # Bank1 38P_A5_M1CLK
|
||||
NET "IOBITS<92>" LOC = "H16" ; # Bank1 37N_A6_M1A1
|
||||
NET "IOBITS<93>" LOC = "H15" ; # Bank1 37P_A7_M1A0
|
||||
NET "IOBITS<94>" LOC = "K14" ; # Bank1 41N_C8_M1CAS
|
||||
NET "IOBITS<95>" LOC = "J13" ; # Bank1 41P_C9_M1RAS
|
||||
|
||||
NET "DATABUS<0>" LOC = "P7" ; # Bank2 31P_C31_D14 "D<0>"
|
||||
NET "DATABUS<1>" LOC = "N12" ; # Bank2 12P_D1_MISO2 "D<1>"
|
||||
NET "DATABUS<2>" LOC = "P12" ; # Bank2 12N_D2_MISO3 "D<2>"
|
||||
NET "DATABUS<3>" LOC = "N5" ; # Bank2 49P_D3 "D<3>"
|
||||
NET "DATABUS<4>" LOC = "P5" ; # Bank2 49N_D4 "D<4>"
|
||||
NET "DATABUS<5>" LOC = "L8" ; # Bank2 62P_D5 "D<5>"
|
||||
NET "DATABUS<6>" LOC = "L7" ; # Bank2 62N_D6 "D<6>"
|
||||
NET "DATABUS<7>" LOC = "R5" ; # Bank2 48P_D7 "D<7>"
|
||||
|
||||
#NET "HOST<0>" LOC = "T4" ; # Bank2 63N EPP_READ
|
||||
#NET "HOST<1>" LOC = "P4" ; # Bank2 63P EPP_DSTROBE
|
||||
#NET "HOST<2>" LOC = "N6" ; # Bank2 64N EPP_ASTROBE
|
||||
#NET "HOST<3>" LOC = "M6" ; # Bank2 64P EPP_WAIT
|
||||
|
||||
#NET "HOST<4>" LOC = "T6" ; # Bank2 47N ACBUS4
|
||||
#NET "HOST<5>" LOC = "P6" ; # Bank2 47P ACBUS5
|
||||
#NET "HOST<6>" LOC = "T7" ; # Bank2 32N_C28 ACBUS6
|
||||
#NET "HOST<7>" LOC = "R7" ; # Bank2 32P_C29 ACBUS7
|
||||
#NET "HOST<8>" LOC = "T8" ; # Bank2 30N_C0_USRCC BDBUS0
|
||||
#NET "HOST<9>" LOC = "P8" ; # Bank2 30P_C1_D13 BDBUS1
|
||||
#NET "HOST<10>" LOC = "N8" ; # Bank2 29N_C2 BDBUS2
|
||||
#NET "HOST<11>" LOC = "M9" ; # Bank2 29P_C3 BDBUS3
|
||||
#NET "HOST<12>" LOC = "P9" ; # Bank2 14N_D12 BDBUS4
|
||||
#NET "HOST<13>" LOC = "N9" ; # Bank2 14P_D11 BDBUS5
|
||||
#NET "HOST<14>" LOC = "T9" ; # Bank2 23N BDBUS6
|
||||
#NET "HOST<15>" LOC = "R9" ; # Bank2 23P BDBUS7
|
||||
#NET "HOST<16>" LOC = "T12" ; # Bank1 52N_M1DQ15 BCBUS0
|
||||
#NET "HOST<17>" LOC = "R12" ; # Bank1 52P_M1DQ14 BCBUS1
|
||||
#NET "HOST<18>" LOC = "T13" ; # Bank1 51N_M1DQ13 BCBUS2
|
||||
#NET "HOST<19>" LOC = "T14" ; # Bank1 51P_M1DQ12 BCBUS3
|
||||
#NET "HOST<20>" LOC = "T15" ; # Bank1 50N_M1UDQSN BCBUS4
|
||||
#NET "HOST<21>" LOC = "R14" ; # Bank1 50P_M1UDQS BCBUS5
|
||||
#NET "HOST<22>" LOC = "R16" ; # Bank1 49N_M1DQ11 BCBUS6
|
||||
#NET "HOST<23>" LOC = "R15" ; # Bank1 49P_M1DQ10 BCBUS7
|
||||
NET "USB_RXF" LOC = "P16" ; # Bank1 48N_M1DQ9 "HOST<24>" ACBUS0
|
||||
NET "USB_TXE" LOC = "P15" ; # Bank1 48P_HDC_M1DQ8 "HOST<25>" ACBUS1
|
||||
NET "USB_RD" LOC = "N16" ; # Bank1 45N_A0_M1LDQS "HOST<26>" ACBUS2
|
||||
NET "USB_WRITE" LOC = "N14" ; # Bank1 45P_A1_M1LDQS "HOST<27>" ACBUS3
|
||||
#NET "HOST<28>" LOC = "M16" ; # Bank1 46N_FOE_M1DQ3
|
||||
#NET "HOST<29>" LOC = "M15" ; # Bank1 46P_FCS_M1DQ2
|
||||
#NET "HOST<30>" LOC = "L16" ; # Bank1 47N_LDC_M1DQ1
|
||||
#NET "HOST<31>" LOC = "L14" ; # Bank1 47P_FWE_M1DQ0
|
||||
#NET "HOST<32>" LOC = "K16" ; # Bank1 44N_A2_M1DQ7
|
||||
|
||||
|
||||
NET "PARACONFIG" LOC = "K15" ; # Bank1 44P_A3_M1DQ6 "HOST<33>"
|
||||
NET "/RECONFIG" LOC = "M10" ; # Bank2 16N_VREF
|
||||
|
||||
NET "CLK" LOC = "M7" ; # Bank2 31N_C30_D15 "FPGACLK"
|
||||
|
||||
NET "SPIIN" LOC = "P10" ; # Bank2 3P_D0_MISO1 "SDIN"
|
||||
NET "SPIOUT" LOC = "T10" ; # Bank2 3N_CSI_MISO0 "SDOUT"
|
||||
NET "SPICS" LOC = "T3" ; # Bank2 65N_CSO_B "/CSO"
|
||||
|
||||
#NET "***<000003>" LOC = "A4" ; # Bank0 1N_VREF option jumper
|
||||
#NET "***<000002>" LOC = "B5" ; # Bank0 2P option jumper
|
||||
#NET "CCLK" LOC = "R11" ; # Bank2 1P_CCLK
|
||||
NET "SPICLK" LOC = "T5" ; # Bank2 48N_RDWR_VREF "RDWR"
|
||||
#NET "HOSTCLK" LOC = "K12" ; # Bank1 42P_C7_M1UDM
|
||||
#NET "M<0>" LOC = "T11" ; # Bank2 1N_M0_CMPMISO
|
||||
#NET "M<1>" LOC = "N11" ; # Bank2 13P_M1
|
||||
#NET "DONE" LOC = "P13" ; # Bank2 ONE
|
||||
#NET "NINIT" LOC = "R3" ; # Bank2 65P_INIT_B maybe use for blinkylight?
|
||||
|
||||
#NET "/PROGRAM" LOC = "T2" ; # Bank2 ROGRAM_B
|
||||
#NET "HSWAPEN_<0>" LOC = "C4" ; # Bank0 1P_HSWAPEN
|
||||
#NET "FPGATCK" LOC = "C14" ; # Bank4 CK
|
||||
#NET "FPGATDI" LOC = "C12" ; # Bank4 DI
|
||||
#NET "FPGATMS" LOC = "A15" ; # Bank4 MS
|
||||
#NET "FPGATDO" LOC = "E14" ; # Bank4 DO
|
||||
#NET "NC" LOC = "P14" ; # Bank4 USPEND
|
||||
NET "HRECONFIG" LOC = "F6" ; # Bank3 55P_M3A13 dummy unused
|
||||
#NET "NC" LOC = "F5" ; # Bank3 55N_M3A14
|
||||
#NET "NC" LOC = "G6" ; # Bank3 51P_M3A10
|
||||
#NET "NC" LOC = "G5" ; # Bank3 51N_M3A4
|
||||
#NET "NC" LOC = "K5" ; # Bank3 47P_M3A0
|
||||
#NET "NC" LOC = "K6" ; # Bank3 47N_M3A1
|
||||
#NET "NC" LOC = "L10" ; # Bank2 16P
|
||||
#NET "NC" LOC = "P11" ; # Bank2 13N_D10
|
||||
#NET "NC" LOC = "M12" ; # Bank2 2P_CMPCLK
|
||||
#NET "NC" LOC = "M11" ; # Bank2 2N_CMPMOSI
|
||||
#NET "NC" LOC = "M13" ; # Bank1 74P_AWAKE
|
||||
#NET "NC" LOC = "M14" ; # Bank1 74N_DOUT_BUS
|
||||
#NET "NC" LOC = "L12" ; # Bank1 53P
|
||||
#NET "NC" LOC = "L13" ; # Bank1 53N_VREF
|
||||
#NET "NC" LOC = "K11" ; # Bank1 42N_C6_M1LDM
|
||||
#NET "NC" LOC = "J11" ; # Bank1 40P_C11_M1A5
|
||||
#NET "NC" LOC = "J12" ; # Bank1 40N_C10_M1A6
|
||||
#NET "NC" LOC = "H13" ; # Bank1 39P_M1A3
|
||||
#NET "NC" LOC = "H14" ; # Bank1 39N_M1ODT
|
||||
#NET "NC" LOC = "F12" ; # Bank1 30P_A21_M1RST
|
||||
#NET "NC" LOC = "G11" ; # Bank1 30N_A20_M1A11
|
||||
#NET "NC" LOC = "F10" ; # Bank0 64P_SCP5
|
||||
#NET "NC" LOC = "E11" ; # Bank0 64N_SCP4
|
||||
#NET "NC" LOC = "F9" ; # Bank0 40P
|
||||
#NET "NC" LOC = "F7" ; # Bank0 5P
|
||||
#NET "NC" LOC = "E6" ; # Bank0 5N
|
||||
#NET "<3.3V>" LOC = "N10" ; # Bank2 CCO
|
||||
#NET "<3.3V>" LOC = "N7" ; # Bank2 CCO
|
||||
#NET "<3.3V>" LOC = "R4" ; # Bank2 CCO
|
||||
#NET "<3.3V>" LOC = "R8" ; # Bank2 CCO
|
||||
#NET "<3.3V>" LOC = "D15" ; # Bank1 CCO
|
||||
#NET "<3.3V>" LOC = "G13" ; # Bank1 CCO
|
||||
#NET "<3.3V>" LOC = "J15" ; # Bank1 CCO
|
||||
#NET "<3.3V>" LOC = "K13" ; # Bank1 CCO
|
||||
#NET "<3.3V>" LOC = "N15" ; # Bank1 CCO
|
||||
#NET "<3.3V>" LOC = "R13" ; # Bank1 CCO
|
||||
#NET "<3.3V>" LOC = "L11" ; # Bank2 MPCS_B
|
||||
#NET "<3.3V>" LOC = "B13" ; # Bank0 CCO
|
||||
#NET "<3.3V>" LOC = "B4" ; # Bank0 CCO
|
||||
#NET "<3.3V>" LOC = "B9" ; # Bank0 CCO
|
||||
#NET "<3.3V>" LOC = "D10" ; # Bank0 CCO
|
||||
#NET "<3.3V>" LOC = "D7" ; # Bank0 CCO
|
||||
#NET "<3.3V>" LOC = "E5" ; # Bank5 CCAUX
|
||||
#NET "<3.3V>" LOC = "F11" ; # Bank5 CCAUX
|
||||
#NET "<3.3V>" LOC = "F8" ; # Bank5 CCAUX
|
||||
#NET "<3.3V>" LOC = "G10" ; # Bank5 CCAUX
|
||||
#NET "<3.3V>" LOC = "H6" ; # Bank5 CCAUX
|
||||
#NET "<3.3V>" LOC = "J10" ; # Bank5 CCAUX
|
||||
#NET "<3.3V>" LOC = "L6" ; # Bank5 CCAUX
|
||||
#NET "<3.3V>" LOC = "L9" ; # Bank5 CCAUX
|
||||
#NET "<1.2V>" LOC = "G7" ; # Bank5 CCINT
|
||||
#NET "<1.2V>" LOC = "G9" ; # Bank5 CCINT
|
||||
#NET "<1.2V>" LOC = "H10" ; # Bank5 CCINT
|
||||
#NET "<1.2V>" LOC = "H8" ; # Bank5 CCINT
|
||||
#NET "<1.2V>" LOC = "J7" ; # Bank5 CCINT
|
||||
#NET "<1.2V>" LOC = "J9" ; # Bank5 CCINT
|
||||
#NET "<1.2V>" LOC = "K10" ; # Bank5 CCINT
|
||||
#NET "<1.2V>" LOC = "K8" ; # Bank5 CCINT
|
||||
#NET "<3.3V>" LOC = "D2" ; # Bank3 CCO
|
||||
#NET "<3.3V>" LOC = "G4" ; # Bank3 CCO
|
||||
#NET "<3.3V>" LOC = "J2" ; # Bank3 CCO
|
||||
#NET "<3.3V>" LOC = "K4" ; # Bank3 CCO
|
||||
#NET "<3.3V>" LOC = "N2" ; # Bank3 CCO
|
||||
#NET "GND" LOC = "A1" ; # Bank5 ND
|
||||
#NET "GND" LOC = "A16" ; # Bank5 ND
|
||||
#NET "GND" LOC = "B11" ; # Bank5 ND
|
||||
#NET "GND" LOC = "B7" ; # Bank5 ND
|
||||
#NET "GND" LOC = "D13" ; # Bank5 ND
|
||||
#NET "GND" LOC = "D4" ; # Bank5 ND
|
||||
#NET "GND" LOC = "E9" ; # Bank5 ND
|
||||
#NET "GND" LOC = "G15" ; # Bank5 ND
|
||||
#NET "GND" LOC = "G2" ; # Bank5 ND
|
||||
#NET "GND" LOC = "G8" ; # Bank5 ND
|
||||
#NET "GND" LOC = "H12" ; # Bank5 ND
|
||||
#NET "GND" LOC = "H7" ; # Bank5 ND
|
||||
#NET "GND" LOC = "H9" ; # Bank5 ND
|
||||
#NET "GND" LOC = "J5" ; # Bank5 ND
|
||||
#NET "GND" LOC = "J8" ; # Bank5 ND
|
||||
#NET "GND" LOC = "K7" ; # Bank5 ND
|
||||
#NET "GND" LOC = "K9" ; # Bank5 ND
|
||||
#NET "GND" LOC = "L15" ; # Bank5 ND
|
||||
#NET "GND" LOC = "L2" ; # Bank5 ND
|
||||
#NET "GND" LOC = "M8" ; # Bank5 ND
|
||||
#NET "GND" LOC = "N13" ; # Bank5 ND
|
||||
#NET "GND" LOC = "P3" ; # Bank5 ND
|
||||
#NET "GND" LOC = "R10" ; # Bank5 ND
|
||||
#NET "GND" LOC = "R6" ; # Bank5 ND
|
||||
#NET "GND" LOC = "T1" ; # Bank5 ND
|
||||
#NET "GND" LOC = "T16" ; # Bank5 ND
|
||||
NET "clkfx0" TNM_NET = "async_med"; # For async sserial processor
|
||||
NET "CLK" TNM_NET = "async_low";
|
||||
TIMESPEC "TSLowToMed" = FROM "async_low" to "async_med" TIG;
|
||||
TIMESPEC "TSMedtoLow" = FROM "async_med" to "async_low" TIG;
|
||||
333
5i24/configs/hostmot2/source/7i68.ucf
Executable file
333
5i24/configs/hostmot2/source/7i68.ucf
Executable file
@@ -0,0 +1,333 @@
|
||||
#NET "NC" LOC = "A3" ;
|
||||
#NET "NCRP" LOC = "B4" ;
|
||||
#NET "NCRN" LOC = "A4" ;
|
||||
#NET "NC" LOC = "A10" ;
|
||||
#NET "NC" LOC = "C7" ;
|
||||
#NET "NC" LOC = "D9" ;
|
||||
#NET "NC" LOC = "D10" ;
|
||||
#NET "NC" LOC = "E5" ;
|
||||
#NET "NC" LOC = "F9" ;
|
||||
#NET "NC" LOC = "E9" ;
|
||||
#NET "NC" LOC = "F10" ;
|
||||
#NET "NC" LOC = "E10" ;
|
||||
#NET "NC" LOC = "F11" ;
|
||||
#NET "NC" LOC = "E11" ;
|
||||
#NET "NC" LOC = "F6" ;
|
||||
#NET "NC" LOC = "F7" ;
|
||||
#NET "NC" LOC = "A12" ;
|
||||
#NET "NCRN" LOC = "B20" ;
|
||||
#NET "NCRP" LOC = "C19" ;
|
||||
#NET "NC" LOC = "D12" ;
|
||||
#NET "NC" LOC = "E12" ;
|
||||
#NET "NC" LOC = "D14" ;
|
||||
#NET "NC" LOC = "E14" ;
|
||||
#NET "NC" LOC = "D15" ;
|
||||
#NET "NC" LOC = "E15" ;
|
||||
#NET "NC" LOC = "E13" ;
|
||||
#NET "NC" LOC = "E16" ;
|
||||
#NET "NC" LOC = "F12" ;
|
||||
#NET "NC" LOC = "F13" ;
|
||||
#NET "NC" LOC = "F14" ;
|
||||
#NET "NC" LOC = "F16" ;
|
||||
#NET "NC" LOC = "F17" ;
|
||||
#NET "NCRP" LOC = "C20" ;
|
||||
#NET "NCRN" LOC = "C21" ;
|
||||
#NET "NC" LOC = "C22" ;
|
||||
#NET "NC" LOC = "D20" ;
|
||||
#NET "NC" LOC = "D19" ;
|
||||
#NET "NC" LOC = "E18" ;
|
||||
#NET "NC" LOC = "F18" ;
|
||||
#NET "NC" LOC = "F19" ;
|
||||
#NET "NC" LOC = "G19" ;
|
||||
#NET "NC" LOC = "G17" ;
|
||||
#NET "NC" LOC = "G18" ;
|
||||
#NET "NC" LOC = "G20" ;
|
||||
#NET "NC" LOC = "H19" ;
|
||||
#NET "NC" LOC = "H18" ;
|
||||
#NET "NC" LOC = "J17" ;
|
||||
#NET "NC" LOC = "K17" ;
|
||||
#NET "NC" LOC = "K18" ;
|
||||
#NET "NC" LOC = "L17" ;
|
||||
#NET "NC" LOC = "L18" ;
|
||||
#NET "NC" LOC = "M18" ;
|
||||
#NET "NC" LOC = "M17" ;
|
||||
#NET "NC" LOC = "N18" ;
|
||||
#NET "NC" LOC = "N17" ;
|
||||
#NET "NC" LOC = "P18" ;
|
||||
#NET "NC" LOC = "P17" ;
|
||||
#NET "NC" LOC = "P19" ;
|
||||
#NET "NC" LOC = "R19" ;
|
||||
#NET "NC" LOC = "R18" ;
|
||||
#NET "NC" LOC = "T18" ;
|
||||
#NET "NC" LOC = "T17" ;
|
||||
#NET "NC" LOC = "U18" ;
|
||||
#NET "NC" LOC = "U19" ;
|
||||
#NET "NC" LOC = "V20" ;
|
||||
#NET "NC" LOC = "V19" ;
|
||||
#NET "NC" LOC = "W19" ;
|
||||
#NET "NCRP" LOC = "Y20" ;
|
||||
#NET "NCRN" LOC = "Y19" ;
|
||||
#NET "NC" LOC = "Y21" ;
|
||||
#NET "NC" LOC = "U16" ;
|
||||
#NET "NC" LOC = "U17" ;
|
||||
#NET "NC" LOC = "V17" ;
|
||||
#NET "NC" LOC = "V18" ;
|
||||
#NET "NC" LOC = "Y12" ;
|
||||
#NET "DT/R" LOC = "W18" ;
|
||||
#NET "ALE" LOC = "Y18" ;
|
||||
#NET "CONFD0" LOC = "AA14" ;
|
||||
#NET "NC" LOC = "U6" ;
|
||||
#NET "NC" LOC = "U7" ;
|
||||
#NET "NC" LOC = "U9" ;
|
||||
#NET "NC" LOC = "U10" ;
|
||||
#NET "NC" LOC = "U11" ;
|
||||
#NET "NC" LOC = "W6" ;
|
||||
#NET "NC" LOC = "V6" ;
|
||||
#NET "NC" LOC = "V7" ;
|
||||
#NET "BREQO" LOC = "W8" ;
|
||||
#NET "NC" LOC = "V8" ;
|
||||
#NET "NC" LOC = "W9" ;
|
||||
#NET "NC" LOC = "V9" ;
|
||||
#NET "NC" LOC = "V10" ;
|
||||
#NET "DMPAF" LOC = "Y5" ;
|
||||
#NET "PMEIN" LOC = "W5" ;
|
||||
#NET "NC" LOC = "W7" ;
|
||||
#NET "SERR" LOC = "Y10" ;
|
||||
#NET "NC" LOC = "Y6" ;
|
||||
#NET "DACK1" LOC = "AB4" ;
|
||||
#NET "DRQ1" LOC = "AA4" ;
|
||||
#NET "DACK0" LOC = "AB5" ;
|
||||
NET "DREQ" LOC = "AA5" | IOSTANDARD = LVTTL | PULLUP | SLEW = FAST ; # DRQ0 = 4I68/5I22/5I23 emulation
|
||||
#NET "INTI" LOC = "Y7" ;
|
||||
#NET "NC" LOC = "M6" ;
|
||||
#NET "NC" LOC = "M5" ;
|
||||
#NET "NC" LOC = "N6" ;
|
||||
#NET "NC" LOC = "N5" ;
|
||||
#NET "NC" LOC = "P5" ;
|
||||
#NET "NC" LOC = "P4" ;
|
||||
#NET "NC" LOC = "R5" ;
|
||||
#NET "NC" LOC = "P6" ;
|
||||
#NET "NC" LOC = "U4" ;
|
||||
#NET "NC" LOC = "T4" ;
|
||||
#NET "NC" LOC = "T6" ;
|
||||
#NET "REVERSE" LOC = "T5" ;
|
||||
#NET "RECONFIG" LOC = "V5" ;
|
||||
#NET "NCRP" LOC = "Y3" ;
|
||||
#NET "NCRN" LOC = "Y2" ;
|
||||
#NET "NC" LOC = "C2" ;
|
||||
#NET "NCRP" LOC = "C3" ;
|
||||
#NET "NCRN" LOC = "C4" ;
|
||||
#NET "NC" LOC = "G6" ;
|
||||
#NET "NC" LOC = "F5" ;
|
||||
#NET "NC" LOC = "H5" ;
|
||||
#NET "NC" LOC = "G5" ;
|
||||
#NET "NC" LOC = "J5" ;
|
||||
#NET "NC" LOC = "J6" ;
|
||||
#NET "NC" LOC = "K3" ;
|
||||
#NET "NC" LOC = "K4" ;
|
||||
#NET "NC" LOC = "K5" ;
|
||||
#NET "NC" LOC = "K6" ;
|
||||
#NET "NC" LOC = "L1" ;
|
||||
#NET "NC" LOC = "L2" ;
|
||||
#NET "NC" LOC = "L3" ;
|
||||
#NET "NC" LOC = "L4" ;
|
||||
#NET "NC" LOC = "L5" ;
|
||||
#NET "NC" LOC = "L6" ;
|
||||
NET "LCLK" TNM_NET = LCLK;
|
||||
TIMESPEC TS_LCLK = PERIOD "LCLK" 20 ns HIGH 50%;
|
||||
OFFSET = OUT 16.7 ns AFTER "LCLK";
|
||||
#PACE: Start of Constraints generated by PACE
|
||||
|
||||
#PACE: Start of PACE I/O Pin Assignments
|
||||
NET "ADS" LOC = "AB8" | IOSTANDARD = LVTTL | PULLUP ;
|
||||
NET"BTERM" LOC = "AA11" | IOSTANDARD = LVTTL ;
|
||||
NET "BLAST" LOC = "AA8" | IOSTANDARD = LVTTL | PULLUP ;
|
||||
NET "CCS" LOC = "AA7" | IOSTANDARD = LVTTL | PULLUP ;
|
||||
NET "HOLD" LOC = "AB10" | IOSTANDARD = LVTTL | PULLUP ;
|
||||
NET "HOLDA" LOC = "AA10" | IOSTANDARD = LVTTL ;
|
||||
NET "INT" LOC = "AB7" | IOSTANDARD = LVTTL ;
|
||||
|
||||
NET "IOBITS<0>" LOC = "D11" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<100>" LOC = "P22" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<101>" LOC = "P21" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<102>" LOC = "M22" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<103>" LOC = "M21" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<104>" LOC = "L19" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<105>" LOC = "L20" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<106>" LOC = "J21" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<107>" LOC = "J22" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<108>" LOC = "G21" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<109>" LOC = "G22" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<10>" LOC = "F4" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<110>" LOC = "E19" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<111>" LOC = "E20" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<112>" LOC = "A18" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<113>" LOC = "B18" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<114>" LOC = "D17" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<115>" LOC = "E17" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<116>" LOC = "B15" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<117>" LOC = "A15" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<118>" LOC = "C13" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<119>" LOC = "D13" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<11>" LOC = "E3" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<120>" LOC = "V22" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<121>" LOC = "V21" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<122>" LOC = "T20" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<123>" LOC = "T19" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<124>" LOC = "N22" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<125>" LOC = "N21" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<126>" LOC = "M20" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<127>" LOC = "M19" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<128>" LOC = "K21" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<129>" LOC = "K22" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<12>" LOC = "G3" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<130>" LOC = "J18" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<131>" LOC = "J19" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<132>" LOC = "F20" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<133>" LOC = "F21" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<134>" LOC = "D21" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<135>" LOC = "D22" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<136>" LOC = "C18" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<137>" LOC = "D18" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<138>" LOC = "A16" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<139>" LOC = "B16" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<13>" LOC = "G4" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<140>" LOC = "A14" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<141>" LOC = "B14" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<142>" LOC = "B12" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<143>" LOC = "C12" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<14>" LOC = "J1" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<15>" LOC = "J2" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<16>" LOC = "M4" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<17>" LOC = "M3" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<18>" LOC = "P2" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<19>" LOC = "P1" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<1>" LOC = "C11" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<20>" LOC = "T2" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<21>" LOC = "T1" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<22>" LOC = "V4" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<23>" LOC = "V3" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<24>" LOC = "C10" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<25>" LOC = "B10" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<26>" LOC = "E8" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<27>" LOC = "D8" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<28>" LOC = "C6" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<29>" LOC = "B6" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<2>" LOC = "B8" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<30>" LOC = "B5" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<31>" LOC = "A5" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<32>" LOC = "E4" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<33>" LOC = "D4" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<34>" LOC = "F2" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<35>" LOC = "F3" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<36>" LOC = "H1" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<37>" LOC = "H2" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<38>" LOC = "K1" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<39>" LOC = "K2" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<3>" LOC = "A8" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<40>" LOC = "N2" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<41>" LOC = "N1" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<42>" LOC = "R2" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<43>" LOC = "R1" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<44>" LOC = "U3" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<45>" LOC = "U2" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<46>" LOC = "W2" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<47>" LOC = "W1" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<48>" LOC = "B11" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<49>" LOC = "A11" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<4>" LOC = "E7" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<50>" LOC = "B9" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<51>" LOC = "A9" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<52>" LOC = "B7" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<53>" LOC = "A7" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<54>" LOC = "E6" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<55>" LOC = "D6" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<56>" LOC = "D1" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<57>" LOC = "C1" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<58>" LOC = "E1" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<59>" LOC = "E2" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<5>" LOC = "D7" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<60>" LOC = "G1" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<61>" LOC = "G2" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<62>" LOC = "J4" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<63>" LOC = "H4" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<64>" LOC = "M2" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<65>" LOC = "M1" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<66>" LOC = "N4" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<67>" LOC = "N3" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<68>" LOC = "T3" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<69>" LOC = "R4" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<6>" LOC = "D5" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<70>" LOC = "V2" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<71>" LOC = "V1" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<72>" LOC = "W22" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<73>" LOC = "Y22" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<74>" LOC = "U21" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<75>" LOC = "U20" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<76>" LOC = "R22" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<77>" LOC = "R21" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<78>" LOC = "N20" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<79>" LOC = "N19" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<7>" LOC = "C5" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<80>" LOC = "L21" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<81>" LOC = "L22" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<82>" LOC = "K19" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<83>" LOC = "K20" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<84>" LOC = "H21" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<85>" LOC = "H22" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<86>" LOC = "E21" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<87>" LOC = "E22" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<88>" LOC = "A19" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<89>" LOC = "B19" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<8>" LOC = "D3" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<90>" LOC = "B17" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<91>" LOC = "C17" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<92>" LOC = "C16" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<93>" LOC = "D16" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<94>" LOC = "A13" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<95>" LOC = "B13" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<96>" LOC = "W21" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<97>" LOC = "W20" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<98>" LOC = "T22" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<99>" LOC = "T21" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "IOBITS<9>" LOC = "D2" | IOSTANDARD = LVTTL | PULLUP | SLEW = SLOW ;
|
||||
NET "LAD<0>" LOC = "AB11" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<10>" LOC = "V13" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<11>" LOC = "U13" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<12>" LOC = "AB13" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<13>" LOC = "AA13" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<14>" LOC = "Y13" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<15>" LOC = "W13" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<16>" LOC = "U14" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<17>" LOC = "V16" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<18>" LOC = "W14" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<19>" LOC = "V14" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<1>" LOC = "AB14" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<20>" LOC = "AB15" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<21>" LOC = "AA15" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<22>" LOC = "W15" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<23>" LOC = "V15" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<24>" LOC = "AB16" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<25>" LOC = "AA16" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<26>" LOC = "Y16" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<27>" LOC = "W16" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<28>" LOC = "AA17" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<29>" LOC = "Y17" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<2>" LOC = "U12" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<30>" LOC = "AB18" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<31>" LOC = "AA18" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<3>" LOC = "V12" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<4>" LOC = "W11" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<5>" LOC = "V11" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<6>" LOC = "AB9" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<7>" LOC = "AA9" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<8>" LOC = "AB12" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LAD<9>" LOC = "AA12" | IOSTANDARD = LVTTL | KEEPER ;
|
||||
NET "LCLK" LOC = "Y11" | IOSTANDARD = LVTTL ;
|
||||
NET "LEDS<0>" LOC = "W12" | IOSTANDARD = LVTTL | SLEW = SLOW ;
|
||||
NET "LW_R" LOC = "W17" | IOSTANDARD = LVTTL | PULLUP ;
|
||||
NET "READY" LOC = "Y4" | IOSTANDARD = LVTTL | PULLDOWN ;
|
||||
NET "clkfx1" TNM_NET = "async_med"; # For async sserial processor
|
||||
NET "LCLK" TNM_NET = "async_low";
|
||||
TIMESPEC "TSLowToMed" = FROM "async_low" to "async_med" TIG;
|
||||
TIMESPEC "TSMedtoLow" = FROM "async_med" to "async_low" TIG;
|
||||
238
5i24/configs/hostmot2/source/7i76e.ucf
Executable file
238
5i24/configs/hostmot2/source/7i76e.ucf
Executable file
@@ -0,0 +1,238 @@
|
||||
NET "CLK" TNM_NET = "CLK";
|
||||
TIMESPEC "TS_CLK" = PERIOD "CLK" 19.9 ns HIGH 50 %;
|
||||
NET "SPICLK" LOC = "R11" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L1P_CCLK
|
||||
NET "SPICS" LOC = "T3" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L65N_CSO_B
|
||||
NET "SPIIN" LOC = "P10" | IOSTANDARD = LVTTL; # Bank2 L3P_D0_MISO1
|
||||
NET "SPIOUT" LOC = "T10" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L3N_CSI_MISO0
|
||||
NET "ECLK" LOC = "P16" | IOSTANDARD = LVTTL | DRIVE = 4 ; # Bank1 L48N_M1DQ9
|
||||
NET "NECS" LOC = "T4" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L63N
|
||||
NET "ECMD" LOC = "P4" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L63P
|
||||
NET "NEREAD" LOC = "T5" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L48N_RDWR_VREF
|
||||
NET "NEWRITE" LOC = "P5" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L49N_D4
|
||||
NET "NERST" LOC = "P15" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L48P_HDC_M1DQ8
|
||||
NET "EINT" LOC = "R5" | IOSTANDARD = LVTTL | PULLUP; # Bank2 L48P_D7
|
||||
NET "CLK" LOC = "P7" | IOSTANDARD = LVTTL; # Bank2 L31P_C31_D14
|
||||
NET "ED<0>" LOC = "T6" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L47N
|
||||
NET "ED<1>" LOC = "P6" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L47P
|
||||
NET "ED<2>" LOC = "T7" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L32N_C28
|
||||
NET "ED<3>" LOC = "R7" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L32P_C29
|
||||
NET "ED<4>" LOC = "T8" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L30N_C0_USRCC
|
||||
NET "ED<5>" LOC = "P8" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L30P_C1_D13
|
||||
NET "ED<6>" LOC = "P9" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L14N_D12
|
||||
NET "ED<7>" LOC = "T9" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L23N
|
||||
NET "ED<8>" LOC = "R9" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L23P
|
||||
NET "ED<9>" LOC = "T12" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L52N_M1DQ15
|
||||
NET "ED<10>" LOC = "R12" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L52P_M1DQ14
|
||||
NET "ED<11>" LOC = "T13" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L51N_M1DQ13
|
||||
NET "ED<12>" LOC = "T14" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L51P_M1DQ12
|
||||
NET "ED<13>" LOC = "T15" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L50N_M1UDQSN
|
||||
NET "ED<14>" LOC = "R16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L49N_M1DQ11
|
||||
NET "ED<15>" LOC = "R15" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L49P_M1DQ10
|
||||
NET "IOBITS<0>" LOC = "A12" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L62N_VREF
|
||||
NET "IOBITS<1>" LOC = "C11" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L39P
|
||||
NET "IOBITS<2>" LOC = "A11" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L39N
|
||||
NET "IOBITS<3>" LOC = "B10" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L35P_C17
|
||||
NET "IOBITS<4>" LOC = "A10" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L35N_C16
|
||||
NET "IOBITS<5>" LOC = "C9" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L34P_C19
|
||||
NET "IOBITS<6>" LOC = "A9" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L34N_C18
|
||||
NET "IOBITS<7>" LOC = "B8" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L33P
|
||||
NET "IOBITS<8>" LOC = "A8" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L33N
|
||||
NET "IOBITS<9>" LOC = "C7" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L6P
|
||||
NET "IOBITS<10>" LOC = "A7" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L6N
|
||||
NET "IOBITS<11>" LOC = "B6" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L4P
|
||||
NET "IOBITS<12>" LOC = "A6" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L4N
|
||||
NET "IOBITS<13>" LOC = "B5" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L2P
|
||||
NET "IOBITS<14>" LOC = "A5" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L2N
|
||||
NET "IOBITS<15>" LOC = "B3" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L83P
|
||||
NET "IOBITS<16>" LOC = "A3" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L83N_VREF
|
||||
NET "IOBITS<17>" LOC = "M3" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L1N_VREF
|
||||
NET "IOBITS<18>" LOC = "M4" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L1P
|
||||
NET "IOBITS<19>" LOC = "L1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L36N_M3DQ9
|
||||
NET "IOBITS<20>" LOC = "L3" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L36P_M3DQ8
|
||||
NET "IOBITS<21>" LOC = "K1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L37N_M3DQ1
|
||||
NET "IOBITS<22>" LOC = "K2" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L37P_M3DQ0
|
||||
NET "IOBITS<23>" LOC = "J1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L38N_M3DQ3
|
||||
NET "IOBITS<24>" LOC = "J3" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L38P_M3DQ2
|
||||
NET "IOBITS<25>" LOC = "H1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L39N_M3LDQSN
|
||||
NET "IOBITS<26>" LOC = "H2" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L39P_M3LDQS
|
||||
NET "IOBITS<27>" LOC = "G1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L40N_M3DQ7
|
||||
NET "IOBITS<28>" LOC = "G3" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L40P_M3DQ6
|
||||
NET "IOBITS<29>" LOC = "F1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L41N_C26_M3DQ5
|
||||
NET "IOBITS<30>" LOC = "F2" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L41P_C27_M3DQ4
|
||||
NET "IOBITS<31>" LOC = "E1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L46N_M3CLKN
|
||||
NET "IOBITS<32>" LOC = "E2" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L46P_M3CLK
|
||||
NET "IOBITS<33>" LOC = "D1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L49N_M3A2
|
||||
NET "IOBITS<34>" LOC = "C16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L33N_A14_M1A4
|
||||
NET "IOBITS<35>" LOC = "C15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L33P_A15_M1A10
|
||||
NET "IOBITS<36>" LOC = "D16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L31N_A18_M1A12
|
||||
NET "IOBITS<37>" LOC = "D14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L31P_A19_M1CKE
|
||||
NET "IOBITS<38>" LOC = "E16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L34N_A12_M1BA2
|
||||
NET "IOBITS<39>" LOC = "E15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L34P_A13_M1WE
|
||||
NET "IOBITS<40>" LOC = "F16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L35N_A10_M1A2
|
||||
NET "IOBITS<41>" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L35P_A11_M1A7
|
||||
NET "IOBITS<42>" LOC = "G16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L36N_A8_M1BA1
|
||||
NET "IOBITS<43>" LOC = "G14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L36P_A9_M1BA0
|
||||
NET "IOBITS<44>" LOC = "H16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L37N_A6_M1A1
|
||||
NET "IOBITS<45>" LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L37P_A7_M1A0
|
||||
NET "IOBITS<46>" LOC = "J16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L43N_C4_M1DQ5
|
||||
NET "IOBITS<47>" LOC = "J14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L43P_C5_M1DQ4
|
||||
NET "IOBITS<48>" LOC = "K16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L44N_A2_M1DQ7
|
||||
NET "IOBITS<49>" LOC = "K15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L44P_A3_M1DQ6
|
||||
NET "IOBITS<50>" LOC = "L16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L47N_LDC_M1DQ1
|
||||
NET "LIOBITS<0>" LOC = "C5" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # TXEN1 Bank0 L3N
|
||||
NET "LEDS<3>" LOC = "R2" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L32P_M3DQ14
|
||||
NET "LEDS<2>" LOC = "R1" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L32N_M3DQ15
|
||||
NET "LEDS<1>" LOC = "P2" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L33P_M3DQ12
|
||||
NET "LEDS<0>" LOC = "P1" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L33N_M3DQ13
|
||||
NET "OPTS<0>" LOC = "N3" ; # Bank3 L34P_M3UDQS
|
||||
NET "OPTS<1>" LOC = "N1" ; # Bank3 L34N_M3UDQSN
|
||||
NET "TP<0>" LOC = "M2" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank3 L35P_M3DQ10
|
||||
NET "TP<1>" LOC = "M1" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank3 L35N_M3DQ11
|
||||
NET "NINIT" LOC = "R3" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L65P_INIT_B
|
||||
|
||||
#NET "M<0>" LOC = "T11" ; # Bank2 L1N_M0_CMPMISO
|
||||
#NET "M<1>" LOC = "N11" ; # Bank2 L13P_M1
|
||||
#NET "HSWAPEN_<3>" LOC = "C4" ; # Bank0 L1P_HSWAPEN
|
||||
#NET "DONE" LOC = "P13" ; # Bank2 DONE
|
||||
#NET "PWRGD" LOC = "T2" ; # Bank2 PROGRAM_B
|
||||
#NET "FPGATCK" LOC = "C14" ; # Bank4 TCK
|
||||
#NET "FPGATDI" LOC = "C12" ; # Bank4 TDI
|
||||
#NET "FPGATDO" LOC = "E14" ; # Bank4 TDO
|
||||
#NET "FPGATMS" LOC = "A15" ; # Bank4 TMS
|
||||
#NET "<1.2V>" LOC = "G7" ; # Bank5 VCCINT
|
||||
#NET "<1.2V>" LOC = "G9" ; # Bank5 VCCINT
|
||||
#NET "<1.2V>" LOC = "H10" ; # Bank5 VCCINT
|
||||
#NET "<1.2V>" LOC = "H8" ; # Bank5 VCCINT
|
||||
#NET "<1.2V>" LOC = "J7" ; # Bank5 VCCINT
|
||||
#NET "<1.2V>" LOC = "J9" ; # Bank5 VCCINT
|
||||
#NET "<1.2V>" LOC = "K10" ; # Bank5 VCCINT
|
||||
#NET "<1.2V>" LOC = "K8" ; # Bank5 VCCINT
|
||||
#NET "<3.3V>" LOC = "B13" ; # Bank0 VCCO
|
||||
#NET "<3.3V>" LOC = "B4" ; # Bank0 VCCO
|
||||
#NET "<3.3V>" LOC = "B9" ; # Bank0 VCCO
|
||||
#NET "<3.3V>" LOC = "D10" ; # Bank0 VCCO
|
||||
#NET "<3.3V>" LOC = "D15" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "D2" ; # Bank3 VCCO
|
||||
#NET "<3.3V>" LOC = "D7" ; # Bank0 VCCO
|
||||
#NET "<3.3V>" LOC = "E5" ; # Bank5 VCCAUX
|
||||
#NET "<3.3V>" LOC = "F11" ; # Bank5 VCCAUX
|
||||
#NET "<3.3V>" LOC = "F8" ; # Bank5 VCCAUX
|
||||
#NET "<3.3V>" LOC = "G10" ; # Bank5 VCCAUX
|
||||
#NET "<3.3V>" LOC = "G13" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "G4" ; # Bank3 VCCO
|
||||
#NET "<3.3V>" LOC = "H6" ; # Bank5 VCCAUX
|
||||
#NET "<3.3V>" LOC = "J10" ; # Bank5 VCCAUX
|
||||
#NET "<3.3V>" LOC = "J15" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "J2" ; # Bank3 VCCO
|
||||
#NET "<3.3V>" LOC = "K13" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "K4" ; # Bank3 VCCO
|
||||
#NET "<3.3V>" LOC = "L11" ; # Bank2 CMPCS_B
|
||||
#NET "<3.3V>" LOC = "L6" ; # Bank5 VCCAUX
|
||||
#NET "<3.3V>" LOC = "L9" ; # Bank5 VCCAUX
|
||||
#NET "<3.3V>" LOC = "N10" ; # Bank2 VCCO
|
||||
#NET "<3.3V>" LOC = "N15" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "N2" ; # Bank3 VCCO
|
||||
#NET "<3.3V>" LOC = "N7" ; # Bank2 VCCO
|
||||
#NET "<3.3V>" LOC = "R13" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "R4" ; # Bank2 VCCO
|
||||
#NET "<3.3V>" LOC = "R8" ; # Bank2 VCCO
|
||||
#NET "GND" LOC = "A1" ; # Bank5 GND
|
||||
#NET "GND" LOC = "A16" ; # Bank5 GND
|
||||
#NET "GND" LOC = "B11" ; # Bank5 GND
|
||||
#NET "GND" LOC = "B7" ; # Bank5 GND
|
||||
#NET "GND" LOC = "D13" ; # Bank5 GND
|
||||
#NET "GND" LOC = "D4" ; # Bank5 GND
|
||||
#NET "GND" LOC = "E9" ; # Bank5 GND
|
||||
#NET "GND" LOC = "G15" ; # Bank5 GND
|
||||
#NET "GND" LOC = "G2" ; # Bank5 GND
|
||||
#NET "GND" LOC = "G8" ; # Bank5 GND
|
||||
#NET "GND" LOC = "H12" ; # Bank5 GND
|
||||
#NET "GND" LOC = "H7" ; # Bank5 GND
|
||||
#NET "GND" LOC = "H9" ; # Bank5 GND
|
||||
#NET "GND" LOC = "J5" ; # Bank5 GND
|
||||
#NET "GND" LOC = "J8" ; # Bank5 GND
|
||||
#NET "GND" LOC = "K7" ; # Bank5 GND
|
||||
#NET "GND" LOC = "K9" ; # Bank5 GND
|
||||
#NET "GND" LOC = "L15" ; # Bank5 GND
|
||||
#NET "GND" LOC = "L2" ; # Bank5 GND
|
||||
#NET "GND" LOC = "M8" ; # Bank5 GND
|
||||
#NET "GND" LOC = "N13" ; # Bank5 GND
|
||||
#NET "GND" LOC = "P3" ; # Bank5 GND
|
||||
#NET "GND" LOC = "R10" ; # Bank5 GND
|
||||
#NET "GND" LOC = "R6" ; # Bank5 GND
|
||||
#NET "GND" LOC = "T1" ; # Bank5 GND
|
||||
#NET "GND" LOC = "T16" ; # Bank5 GND
|
||||
#NET "NC" LOC = "A4" ; # Bank0 L1N_VREF
|
||||
#NET "NC" LOC = "C10" ; # Bank0 L37N_C12
|
||||
#NET "NC" LOC = "C6" ; # Bank0 L7N
|
||||
#NET "NC" LOC = "C8" ; # Bank0 L38N_VREF
|
||||
#NET "NC" LOC = "D11" ; # Bank0 L66P_SCP1
|
||||
#NET "NC" LOC = "D12" ; # Bank0 L66N_SCP0
|
||||
#NET "NC" LOC = "D5" ; # Bank0 L3P
|
||||
#NET "NC" LOC = "D6" ; # Bank0 L7P
|
||||
#NET "NC" LOC = "D8" ; # Bank0 L38P
|
||||
#NET "NC" LOC = "D9" ; # Bank0 L40N
|
||||
#NET "NC" LOC = "E10" ; # Bank0 L37P_C13
|
||||
#NET "NC" LOC = "E11" ; # Bank0 L64N_SCP4
|
||||
#NET "NC" LOC = "E12" ; # Bank1 L1N_A24_VREF
|
||||
#NET "NC" LOC = "E13" ; # Bank1 L1P_A25
|
||||
#NET "NC" LOC = "E3" ; # Bank3 L54N_M3A11
|
||||
#NET "NC" LOC = "E4" ; # Bank3 L54P_M3RESET
|
||||
#NET "NC" LOC = "E6" ; # Bank0 L5N
|
||||
#NET "NC" LOC = "E7" ; # Bank0 L36P_C15
|
||||
#NET "NC" LOC = "E8" ; # Bank0 L36N_C14
|
||||
#NET "NC" LOC = "F10" ; # Bank0 L64P_SCP5
|
||||
#NET "NC" LOC = "F12" ; # Bank1 L30P_A21_M1RST
|
||||
#NET "NC" LOC = "F13" ; # Bank1 L32P_A17_M1A8
|
||||
#NET "NC" LOC = "F14" ; # Bank1 L32N_A16_M1A9
|
||||
#NET "NC" LOC = "F3" ; # Bank3 L53N_M3A12
|
||||
#NET "NC" LOC = "F4" ; # Bank3 L53P_M3CKE
|
||||
#NET "NC" LOC = "F5" ; # Bank3 L55N_M3A14
|
||||
#NET "NC" LOC = "F6" ; # Bank3 L55P_M3A13
|
||||
#NET "NC" LOC = "F7" ; # Bank0 L5P
|
||||
#NET "NC" LOC = "F9" ; # Bank0 L40P
|
||||
#NET "NC" LOC = "G11" ; # Bank1 L30N_A20_M1A11
|
||||
#NET "NC" LOC = "G12" ; # Bank1 L38P_A5_M1CLK
|
||||
#NET "NC" LOC = "G5" ; # Bank3 L51N_M3A4
|
||||
#NET "NC" LOC = "G6" ; # Bank3 L51P_M3A10
|
||||
#NET "NC" LOC = "H11" ; # Bank1 L38N_A4_M1CLKN
|
||||
#NET "NC" LOC = "H13" ; # Bank1 L39P_M1A3
|
||||
#NET "NC" LOC = "H14" ; # Bank1 L39N_M1ODT
|
||||
#NET "NC" LOC = "H3" ; # Bank3 L44N_C20_M3A6
|
||||
#NET "NC" LOC = "H4" ; # Bank3 L44P_C21_M3A5
|
||||
#NET "NC" LOC = "H5" ; # Bank3 L43N_C22_M3CAS
|
||||
#NET "NC" LOC = "J11" ; # Bank1 L40P_C11_M1A5
|
||||
#NET "NC" LOC = "J12" ; # Bank1 L40N_C10_M1A6
|
||||
#NET "NC" LOC = "J13" ; # Bank1 L41P_C9_M1RAS
|
||||
#NET "NC" LOC = "J4" ; # Bank3 L42N_C24_M3LDM
|
||||
#NET "NC" LOC = "J6" ; # Bank3 L43P_C23_M3RAS
|
||||
#NET "NC" LOC = "K11" ; # Bank1 L42N_C6_M1LDM
|
||||
#NET "NC" LOC = "K12" ; # Bank1 L42P_C7_M1UDM
|
||||
#NET "NC" LOC = "K14" ; # Bank1 L41N_C8_M1CAS
|
||||
#NET "NC" LOC = "K3" ; # Bank3 L42P_C25_M3UDM
|
||||
#NET "NC" LOC = "K5" ; # Bank3 L47P_M3A0
|
||||
#NET "NC" LOC = "K6" ; # Bank3 L47N_M3A1
|
||||
#NET "NC" LOC = "L10" ; # Bank2 L16P
|
||||
#NET "NC" LOC = "L12" ; # Bank1 L53P
|
||||
#NET "NC" LOC = "L13" ; # Bank1 L53N_VREF
|
||||
#NET "NC" LOC = "L4" ; # Bank3 L45P_M3A3
|
||||
#NET "NC" LOC = "L5" ; # Bank3 L45N_M3ODT
|
||||
#NET "NC" LOC = "L7" ; # Bank2 L62N_D6
|
||||
#NET "NC" LOC = "L8" ; # Bank2 L62P_D5
|
||||
#NET "NC" LOC = "M10" ; # Bank2 L16N_VREF
|
||||
#NET "NC" LOC = "M11" ; # Bank2 L2N_CMPMOSI
|
||||
#NET "NC" LOC = "M12" ; # Bank2 L2P_CMPCLK
|
||||
#NET "NC" LOC = "M5" ; # Bank3 L2P
|
||||
#NET "NC" LOC = "M6" ; # Bank2 L64P_D8
|
||||
#NET "NC" LOC = "M7" ; # Bank2 L31N_C30_D15
|
||||
#NET "NC" LOC = "M9" ; # Bank2 L29P_C3
|
||||
#NET "NC" LOC = "N12" ; # Bank2 L12P_D1_MISO2
|
||||
#NET "NC" LOC = "N4" ; # Bank3 L2N
|
||||
#NET "NC" LOC = "N5" ; # Bank2 L49P_D3
|
||||
#NET "NC" LOC = "N6" ; # Bank2 L64N_D9
|
||||
#NET "NC" LOC = "N8" ; # Bank2 L29N_C2
|
||||
#NET "NC" LOC = "N9" ; # Bank2 L14P_D11
|
||||
#NET "NC" LOC = "P11" ; # Bank2 L13N_D10
|
||||
#NET "NC" LOC = "P12" ; # Bank2 L12N_D2_MISO3
|
||||
#NET "NC" LOC = "P14" ; # Bank4 SUSPEND
|
||||
#NET "NC" LOC = "R14" ; # Bank1 L50P_M1UDQS
|
||||
259
5i24/configs/hostmot2/source/7i80db.ucf
Executable file
259
5i24/configs/hostmot2/source/7i80db.ucf
Executable file
@@ -0,0 +1,259 @@
|
||||
NET "CLK" TNM_NET = "CLK";
|
||||
TIMESPEC "TS_CLK" = PERIOD "CLK" 19.9 ns HIGH 50 %;
|
||||
NET "SPICLK" LOC = "R11" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L1P_CCLK
|
||||
NET "SPICS" LOC = "T3" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L65N_CSO_B
|
||||
NET "SPIIN" LOC = "P10" | IOSTANDARD = LVTTL; # Bank2 L3P_D0_MISO1
|
||||
NET "SPIOUT" LOC = "T10" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L3N_CSI_MISO0
|
||||
NET "ECLK" LOC = "P16" | IOSTANDARD = LVTTL | DRIVE = 4 ; # Bank1 L48N_M1DQ9
|
||||
NET "NECS" LOC = "T4" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L63N
|
||||
NET "ECMD" LOC = "P4" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L63P
|
||||
NET "NEREAD" LOC = "T5" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L48N_RDWR_VREF
|
||||
NET "NEWRITE" LOC = "P5" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L49N_D4
|
||||
NET "NERST" LOC = "P15" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L48P_HDC_M1DQ8
|
||||
NET "EINT" LOC = "R5" | IOSTANDARD = LVTTL | PULLUP; # Bank2 L48P_D7
|
||||
NET "CLK" LOC = "P7" | IOSTANDARD = LVTTL; # Bank2 L31P_C31_D14
|
||||
NET "ED<0>" LOC = "T6" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L47N
|
||||
NET "ED<1>" LOC = "P6" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L47P
|
||||
NET "ED<2>" LOC = "T7" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L32N_C28
|
||||
NET "ED<3>" LOC = "R7" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L32P_C29
|
||||
NET "ED<4>" LOC = "T8" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L30N_C0_USRCC
|
||||
NET "ED<5>" LOC = "P8" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L30P_C1_D13
|
||||
NET "ED<6>" LOC = "P9" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L14N_D12
|
||||
NET "ED<7>" LOC = "T9" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L23N
|
||||
NET "ED<8>" LOC = "R9" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L23P
|
||||
NET "ED<9>" LOC = "T12" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L52N_M1DQ15
|
||||
NET "ED<10>" LOC = "R12" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L52P_M1DQ14
|
||||
NET "ED<11>" LOC = "T13" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L51N_M1DQ13
|
||||
NET "ED<12>" LOC = "T14" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L51P_M1DQ12
|
||||
NET "ED<13>" LOC = "T15" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L50N_M1UDQSN
|
||||
NET "ED<14>" LOC = "R16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L49N_M1DQ11
|
||||
NET "ED<15>" LOC = "R15" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L49P_M1DQ10
|
||||
NET "IOBITS<0>" LOC = "M3" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L1N_VREF
|
||||
NET "IOBITS<1>" LOC = "M4" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L1P
|
||||
NET "IOBITS<2>" LOC = "L1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L36N_M3DQ9
|
||||
NET "IOBITS<3>" LOC = "L3" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L36P_M3DQ8
|
||||
NET "IOBITS<4>" LOC = "K1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L37N_M3DQ1
|
||||
NET "IOBITS<5>" LOC = "K2" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L37P_M3DQ0
|
||||
NET "IOBITS<6>" LOC = "J1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L38N_M3DQ3
|
||||
NET "IOBITS<7>" LOC = "J3" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L38P_M3DQ2
|
||||
NET "IOBITS<8>" LOC = "H1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L39N_M3LDQSN
|
||||
NET "IOBITS<9>" LOC = "H2" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L39P_M3LDQS
|
||||
NET "IOBITS<10>" LOC = "G1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L40N_M3DQ7
|
||||
NET "IOBITS<11>" LOC = "G3" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L40P_M3DQ6
|
||||
NET "IOBITS<12>" LOC = "F1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L41N_C26_M3DQ5
|
||||
NET "IOBITS<13>" LOC = "F2" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L41P_C27_M3DQ4
|
||||
NET "IOBITS<14>" LOC = "E1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L46N_M3CLKN
|
||||
NET "IOBITS<15>" LOC = "E2" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L46P_M3CLK
|
||||
NET "IOBITS<16>" LOC = "D1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L49N_M3A2
|
||||
NET "IOBITS<17>" LOC = "D3" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L49P_M3A7
|
||||
NET "IOBITS<18>" LOC = "B1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L50N_M3BA2
|
||||
NET "IOBITS<19>" LOC = "C1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L50P_M3WE
|
||||
NET "IOBITS<20>" LOC = "C2" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L48N_M3BA1
|
||||
NET "IOBITS<21>" LOC = "C3" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L48P_M3BA0
|
||||
NET "IOBITS<22>" LOC = "A2" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L52N_M3A9
|
||||
NET "IOBITS<23>" LOC = "B2" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L52P_M3A8
|
||||
NET "IOBITS<24>" LOC = "A3" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L83N_VREF
|
||||
NET "IOBITS<25>" LOC = "B3" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L83P
|
||||
NET "IOBITS<26>" LOC = "A5" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L2N
|
||||
NET "IOBITS<27>" LOC = "B5" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L2P
|
||||
NET "IOBITS<28>" LOC = "A6" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L4N
|
||||
NET "IOBITS<29>" LOC = "B6" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L4P
|
||||
NET "IOBITS<30>" LOC = "A7" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L6N
|
||||
NET "IOBITS<31>" LOC = "C7" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L6P
|
||||
NET "IOBITS<32>" LOC = "A8" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L33N
|
||||
NET "IOBITS<33>" LOC = "B8" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L33P
|
||||
NET "IOBITS<34>" LOC = "A9" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L34N_C18
|
||||
NET "IOBITS<35>" LOC = "C9" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L34P_C19
|
||||
NET "IOBITS<36>" LOC = "A10" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L35N_C16
|
||||
NET "IOBITS<37>" LOC = "B10" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L35P_C17
|
||||
NET "IOBITS<38>" LOC = "A11" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L39N
|
||||
NET "IOBITS<39>" LOC = "C11" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L39P
|
||||
NET "IOBITS<40>" LOC = "A12" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L62N_VREF
|
||||
NET "IOBITS<41>" LOC = "B12" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L62P
|
||||
NET "IOBITS<42>" LOC = "A13" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L63N_SCP6
|
||||
NET "IOBITS<43>" LOC = "C13" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L63P_SCP7
|
||||
NET "IOBITS<44>" LOC = "A14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L65N_SCP2
|
||||
NET "IOBITS<45>" LOC = "B14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L65P_SCP3
|
||||
NET "IOBITS<46>" LOC = "B16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L29N_A22_M1A14
|
||||
NET "IOBITS<47>" LOC = "B15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L29P_A23_M1A13
|
||||
NET "IOBITS<48>" LOC = "C16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L33N_A14_M1A4
|
||||
NET "IOBITS<49>" LOC = "C15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L33P_A15_M1A10
|
||||
NET "IOBITS<50>" LOC = "D16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L31N_A18_M1A12
|
||||
NET "IOBITS<51>" LOC = "D14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L31P_A19_M1CKE
|
||||
NET "IOBITS<52>" LOC = "E16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L34N_A12_M1BA2
|
||||
NET "IOBITS<53>" LOC = "E15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L34P_A13_M1WE
|
||||
NET "IOBITS<54>" LOC = "F16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L35N_A10_M1A2
|
||||
NET "IOBITS<55>" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L35P_A11_M1A7
|
||||
NET "IOBITS<56>" LOC = "G16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L36N_A8_M1BA1
|
||||
NET "IOBITS<57>" LOC = "G14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L36P_A9_M1BA0
|
||||
NET "IOBITS<58>" LOC = "H16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L37N_A6_M1A1
|
||||
NET "IOBITS<59>" LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L37P_A7_M1A0
|
||||
NET "IOBITS<60>" LOC = "J16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L43N_C4_M1DQ5
|
||||
NET "IOBITS<61>" LOC = "J14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L43P_C5_M1DQ4
|
||||
NET "IOBITS<62>" LOC = "K16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L44N_A2_M1DQ7
|
||||
NET "IOBITS<63>" LOC = "K15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L44P_A3_M1DQ6
|
||||
NET "IOBITS<64>" LOC = "L16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L47N_LDC_M1DQ1
|
||||
NET "IOBITS<65>" LOC = "L14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L47P_FWE_M1DQ0
|
||||
NET "IOBITS<66>" LOC = "M16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L46N_FOE_M1DQ3
|
||||
NET "IOBITS<67>" LOC = "M15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L46P_FCS_M1DQ2
|
||||
#NET "IOBITS<68>" LOC = "M14" ; # Bank1 L74N_DOUT_BUS 7I80HD only
|
||||
#NET "IOBITS<69>" LOC = "M13" ; # Bank1 L74P_AWAKE 7I80HD only
|
||||
#NET "IOBITS<70>" LOC = "N16" ; # Bank1 L45N_A0_M1LDQS 7I80HD only
|
||||
#NET "IOBITS<71>" LOC = "N14" ; # Bank1 L45P_A1_M1LDQS 7I80HD only
|
||||
NET "LEDS<3>" LOC = "R2" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L32P_M3DQ14
|
||||
NET "LEDS<2>" LOC = "R1" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L32N_M3DQ15
|
||||
NET "LEDS<1>" LOC = "P2" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L33P_M3DQ12
|
||||
NET "LEDS<0>" LOC = "P1" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L33N_M3DQ13
|
||||
NET "OPTS<0>" LOC = "N3" ; # Bank3 L34P_M3UDQS
|
||||
NET "OPTS<1>" LOC = "N1" ; # Bank3 L34N_M3UDQSN
|
||||
NET "TP<0>" LOC = "M2" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank3 L35P_M3DQ10
|
||||
NET "TP<1>" LOC = "M1" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank3 L35N_M3DQ11
|
||||
NET "NINIT" LOC = "R3" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L65P_INIT_B
|
||||
|
||||
#NET "M<0>" LOC = "T11" ; # Bank2 L1N_M0_CMPMISO
|
||||
#NET "M<1>" LOC = "N11" ; # Bank2 L13P_M1
|
||||
#NET "HSWAPEN_<3>" LOC = "C4" ; # Bank0 L1P_HSWAPEN
|
||||
#NET "DONE" LOC = "P13" ; # Bank2 DONE
|
||||
#NET "PWRGD" LOC = "T2" ; # Bank2 PROGRAM_B
|
||||
#NET "FPGATCK" LOC = "C14" ; # Bank4 TCK
|
||||
#NET "FPGATDI" LOC = "C12" ; # Bank4 TDI
|
||||
#NET "FPGATDO" LOC = "E14" ; # Bank4 TDO
|
||||
#NET "FPGATMS" LOC = "A15" ; # Bank4 TMS
|
||||
#NET "<1.2V>" LOC = "G7" ; # Bank5 VCCINT
|
||||
#NET "<1.2V>" LOC = "G9" ; # Bank5 VCCINT
|
||||
#NET "<1.2V>" LOC = "H10" ; # Bank5 VCCINT
|
||||
#NET "<1.2V>" LOC = "H8" ; # Bank5 VCCINT
|
||||
#NET "<1.2V>" LOC = "J7" ; # Bank5 VCCINT
|
||||
#NET "<1.2V>" LOC = "J9" ; # Bank5 VCCINT
|
||||
#NET "<1.2V>" LOC = "K10" ; # Bank5 VCCINT
|
||||
#NET "<1.2V>" LOC = "K8" ; # Bank5 VCCINT
|
||||
#NET "<3.3V>" LOC = "B13" ; # Bank0 VCCO
|
||||
#NET "<3.3V>" LOC = "B4" ; # Bank0 VCCO
|
||||
#NET "<3.3V>" LOC = "B9" ; # Bank0 VCCO
|
||||
#NET "<3.3V>" LOC = "D10" ; # Bank0 VCCO
|
||||
#NET "<3.3V>" LOC = "D15" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "D2" ; # Bank3 VCCO
|
||||
#NET "<3.3V>" LOC = "D7" ; # Bank0 VCCO
|
||||
#NET "<3.3V>" LOC = "E5" ; # Bank5 VCCAUX
|
||||
#NET "<3.3V>" LOC = "F11" ; # Bank5 VCCAUX
|
||||
#NET "<3.3V>" LOC = "F8" ; # Bank5 VCCAUX
|
||||
#NET "<3.3V>" LOC = "G10" ; # Bank5 VCCAUX
|
||||
#NET "<3.3V>" LOC = "G13" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "G4" ; # Bank3 VCCO
|
||||
#NET "<3.3V>" LOC = "H6" ; # Bank5 VCCAUX
|
||||
#NET "<3.3V>" LOC = "J10" ; # Bank5 VCCAUX
|
||||
#NET "<3.3V>" LOC = "J15" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "J2" ; # Bank3 VCCO
|
||||
#NET "<3.3V>" LOC = "K13" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "K4" ; # Bank3 VCCO
|
||||
#NET "<3.3V>" LOC = "L11" ; # Bank2 CMPCS_B
|
||||
#NET "<3.3V>" LOC = "L6" ; # Bank5 VCCAUX
|
||||
#NET "<3.3V>" LOC = "L9" ; # Bank5 VCCAUX
|
||||
#NET "<3.3V>" LOC = "N10" ; # Bank2 VCCO
|
||||
#NET "<3.3V>" LOC = "N15" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "N2" ; # Bank3 VCCO
|
||||
#NET "<3.3V>" LOC = "N7" ; # Bank2 VCCO
|
||||
#NET "<3.3V>" LOC = "R13" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "R4" ; # Bank2 VCCO
|
||||
#NET "<3.3V>" LOC = "R8" ; # Bank2 VCCO
|
||||
#NET "GND" LOC = "A1" ; # Bank5 GND
|
||||
#NET "GND" LOC = "A16" ; # Bank5 GND
|
||||
#NET "GND" LOC = "B11" ; # Bank5 GND
|
||||
#NET "GND" LOC = "B7" ; # Bank5 GND
|
||||
#NET "GND" LOC = "D13" ; # Bank5 GND
|
||||
#NET "GND" LOC = "D4" ; # Bank5 GND
|
||||
#NET "GND" LOC = "E9" ; # Bank5 GND
|
||||
#NET "GND" LOC = "G15" ; # Bank5 GND
|
||||
#NET "GND" LOC = "G2" ; # Bank5 GND
|
||||
#NET "GND" LOC = "G8" ; # Bank5 GND
|
||||
#NET "GND" LOC = "H12" ; # Bank5 GND
|
||||
#NET "GND" LOC = "H7" ; # Bank5 GND
|
||||
#NET "GND" LOC = "H9" ; # Bank5 GND
|
||||
#NET "GND" LOC = "J5" ; # Bank5 GND
|
||||
#NET "GND" LOC = "J8" ; # Bank5 GND
|
||||
#NET "GND" LOC = "K7" ; # Bank5 GND
|
||||
#NET "GND" LOC = "K9" ; # Bank5 GND
|
||||
#NET "GND" LOC = "L15" ; # Bank5 GND
|
||||
#NET "GND" LOC = "L2" ; # Bank5 GND
|
||||
#NET "GND" LOC = "M8" ; # Bank5 GND
|
||||
#NET "GND" LOC = "N13" ; # Bank5 GND
|
||||
#NET "GND" LOC = "P3" ; # Bank5 GND
|
||||
#NET "GND" LOC = "R10" ; # Bank5 GND
|
||||
#NET "GND" LOC = "R6" ; # Bank5 GND
|
||||
#NET "GND" LOC = "T1" ; # Bank5 GND
|
||||
#NET "GND" LOC = "T16" ; # Bank5 GND
|
||||
#NET "NC" LOC = "A4" ; # Bank0 L1N_VREF
|
||||
#NET "NC" LOC = "C10" ; # Bank0 L37N_C12
|
||||
#NET "NC" LOC = "C5" ; # Bank0 L3N
|
||||
#NET "NC" LOC = "C6" ; # Bank0 L7N
|
||||
#NET "NC" LOC = "C8" ; # Bank0 L38N_VREF
|
||||
#NET "NC" LOC = "D11" ; # Bank0 L66P_SCP1
|
||||
#NET "NC" LOC = "D12" ; # Bank0 L66N_SCP0
|
||||
#NET "NC" LOC = "D5" ; # Bank0 L3P
|
||||
#NET "NC" LOC = "D6" ; # Bank0 L7P
|
||||
#NET "NC" LOC = "D8" ; # Bank0 L38P
|
||||
#NET "NC" LOC = "D9" ; # Bank0 L40N
|
||||
#NET "NC" LOC = "E10" ; # Bank0 L37P_C13
|
||||
#NET "NC" LOC = "E11" ; # Bank0 L64N_SCP4
|
||||
#NET "NC" LOC = "E12" ; # Bank1 L1N_A24_VREF
|
||||
#NET "NC" LOC = "E13" ; # Bank1 L1P_A25
|
||||
#NET "NC" LOC = "E3" ; # Bank3 L54N_M3A11
|
||||
#NET "NC" LOC = "E4" ; # Bank3 L54P_M3RESET
|
||||
#NET "NC" LOC = "E6" ; # Bank0 L5N
|
||||
#NET "NC" LOC = "E7" ; # Bank0 L36P_C15
|
||||
#NET "NC" LOC = "E8" ; # Bank0 L36N_C14
|
||||
#NET "NC" LOC = "F10" ; # Bank0 L64P_SCP5
|
||||
#NET "NC" LOC = "F12" ; # Bank1 L30P_A21_M1RST
|
||||
#NET "NC" LOC = "F13" ; # Bank1 L32P_A17_M1A8
|
||||
#NET "NC" LOC = "F14" ; # Bank1 L32N_A16_M1A9
|
||||
#NET "NC" LOC = "F3" ; # Bank3 L53N_M3A12
|
||||
#NET "NC" LOC = "F4" ; # Bank3 L53P_M3CKE
|
||||
#NET "NC" LOC = "F5" ; # Bank3 L55N_M3A14
|
||||
#NET "NC" LOC = "F6" ; # Bank3 L55P_M3A13
|
||||
#NET "NC" LOC = "F7" ; # Bank0 L5P
|
||||
#NET "NC" LOC = "F9" ; # Bank0 L40P
|
||||
#NET "NC" LOC = "G11" ; # Bank1 L30N_A20_M1A11
|
||||
#NET "NC" LOC = "G12" ; # Bank1 L38P_A5_M1CLK
|
||||
#NET "NC" LOC = "G5" ; # Bank3 L51N_M3A4
|
||||
#NET "NC" LOC = "G6" ; # Bank3 L51P_M3A10
|
||||
#NET "NC" LOC = "H11" ; # Bank1 L38N_A4_M1CLKN
|
||||
#NET "NC" LOC = "H13" ; # Bank1 L39P_M1A3
|
||||
#NET "NC" LOC = "H14" ; # Bank1 L39N_M1ODT
|
||||
#NET "NC" LOC = "H3" ; # Bank3 L44N_C20_M3A6
|
||||
#NET "NC" LOC = "H4" ; # Bank3 L44P_C21_M3A5
|
||||
#NET "NC" LOC = "H5" ; # Bank3 L43N_C22_M3CAS
|
||||
#NET "NC" LOC = "J11" ; # Bank1 L40P_C11_M1A5
|
||||
#NET "NC" LOC = "J12" ; # Bank1 L40N_C10_M1A6
|
||||
#NET "NC" LOC = "J13" ; # Bank1 L41P_C9_M1RAS
|
||||
#NET "NC" LOC = "J4" ; # Bank3 L42N_C24_M3LDM
|
||||
#NET "NC" LOC = "J6" ; # Bank3 L43P_C23_M3RAS
|
||||
#NET "NC" LOC = "K11" ; # Bank1 L42N_C6_M1LDM
|
||||
#NET "NC" LOC = "K12" ; # Bank1 L42P_C7_M1UDM
|
||||
#NET "NC" LOC = "K14" ; # Bank1 L41N_C8_M1CAS
|
||||
#NET "NC" LOC = "K3" ; # Bank3 L42P_C25_M3UDM
|
||||
#NET "NC" LOC = "K5" ; # Bank3 L47P_M3A0
|
||||
#NET "NC" LOC = "K6" ; # Bank3 L47N_M3A1
|
||||
#NET "NC" LOC = "L10" ; # Bank2 L16P
|
||||
#NET "NC" LOC = "L12" ; # Bank1 L53P
|
||||
#NET "NC" LOC = "L13" ; # Bank1 L53N_VREF
|
||||
#NET "NC" LOC = "L4" ; # Bank3 L45P_M3A3
|
||||
#NET "NC" LOC = "L5" ; # Bank3 L45N_M3ODT
|
||||
#NET "NC" LOC = "L7" ; # Bank2 L62N_D6
|
||||
#NET "NC" LOC = "L8" ; # Bank2 L62P_D5
|
||||
#NET "NC" LOC = "M10" ; # Bank2 L16N_VREF
|
||||
#NET "NC" LOC = "M11" ; # Bank2 L2N_CMPMOSI
|
||||
#NET "NC" LOC = "M12" ; # Bank2 L2P_CMPCLK
|
||||
#NET "NC" LOC = "M5" ; # Bank3 L2P
|
||||
#NET "NC" LOC = "M6" ; # Bank2 L64P_D8
|
||||
#NET "NC" LOC = "M7" ; # Bank2 L31N_C30_D15
|
||||
#NET "NC" LOC = "M9" ; # Bank2 L29P_C3
|
||||
#NET "NC" LOC = "N12" ; # Bank2 L12P_D1_MISO2
|
||||
#NET "NC" LOC = "N4" ; # Bank3 L2N
|
||||
#NET "NC" LOC = "N5" ; # Bank2 L49P_D3
|
||||
#NET "NC" LOC = "N6" ; # Bank2 L64N_D9
|
||||
#NET "NC" LOC = "N8" ; # Bank2 L29N_C2
|
||||
#NET "NC" LOC = "N9" ; # Bank2 L14P_D11
|
||||
#NET "NC" LOC = "P11" ; # Bank2 L13N_D10
|
||||
#NET "NC" LOC = "P12" ; # Bank2 L12N_D2_MISO3
|
||||
#NET "NC" LOC = "P14" ; # Bank4 SUSPEND
|
||||
#NET "NC" LOC = "R14" ; # Bank1 L50P_M1UDQS
|
||||
259
5i24/configs/hostmot2/source/7i80hd.ucf
Executable file
259
5i24/configs/hostmot2/source/7i80hd.ucf
Executable file
@@ -0,0 +1,259 @@
|
||||
NET "CLK" TNM_NET = "CLK";
|
||||
TIMESPEC "TS_CLK" = PERIOD "CLK" 19.5 ns HIGH 50 %;
|
||||
NET "SPICLK" LOC = "R11" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L1P_CCLK
|
||||
NET "SPICS" LOC = "T3" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L65N_CSO_B
|
||||
NET "SPIIN" LOC = "P10" | IOSTANDARD = LVTTL; # Bank2 L3P_D0_MISO1
|
||||
NET "SPIOUT" LOC = "T10" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L3N_CSI_MISO0
|
||||
NET "ECLK" LOC = "P16" | IOSTANDARD = LVTTL | DRIVE = 4 ; # Bank1 L48N_M1DQ9
|
||||
NET "NECS" LOC = "T4" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L63N
|
||||
NET "ECMD" LOC = "P4" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L63P
|
||||
NET "NEREAD" LOC = "T5" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L48N_RDWR_VREF
|
||||
NET "NEWRITE" LOC = "P5" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L49N_D4
|
||||
NET "NERST" LOC = "P15" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L48P_HDC_M1DQ8
|
||||
NET "EINT" LOC = "R5" | IOSTANDARD = LVTTL | PULLUP; # Bank2 L48P_D7
|
||||
NET "CLK" LOC = "P7" | IOSTANDARD = LVTTL; # Bank2 L31P_C31_D14
|
||||
NET "ED<0>" LOC = "T6" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L47N
|
||||
NET "ED<1>" LOC = "P6" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L47P
|
||||
NET "ED<2>" LOC = "T7" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L32N_C28
|
||||
NET "ED<3>" LOC = "R7" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L32P_C29
|
||||
NET "ED<4>" LOC = "T8" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L30N_C0_USRCC
|
||||
NET "ED<5>" LOC = "P8" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L30P_C1_D13
|
||||
NET "ED<6>" LOC = "P9" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L14N_D12
|
||||
NET "ED<7>" LOC = "T9" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L23N
|
||||
NET "ED<8>" LOC = "R9" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L23P
|
||||
NET "ED<9>" LOC = "T12" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L52N_M1DQ15
|
||||
NET "ED<10>" LOC = "R12" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L52P_M1DQ14
|
||||
NET "ED<11>" LOC = "T13" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L51N_M1DQ13
|
||||
NET "ED<12>" LOC = "T14" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L51P_M1DQ12
|
||||
NET "ED<13>" LOC = "T15" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L50N_M1UDQSN
|
||||
NET "ED<14>" LOC = "R16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L49N_M1DQ11
|
||||
NET "ED<15>" LOC = "R15" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L49P_M1DQ10
|
||||
NET "IOBITS<0>" LOC = "M3" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L1N_VREF
|
||||
NET "IOBITS<1>" LOC = "M4" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L1P
|
||||
NET "IOBITS<24>" LOC = "L1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L36N_M3DQ9
|
||||
NET "IOBITS<25>" LOC = "L3" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L36P_M3DQ8
|
||||
NET "IOBITS<48>" LOC = "K1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L37N_M3DQ1
|
||||
NET "IOBITS<49>" LOC = "K2" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L37P_M3DQ0
|
||||
NET "IOBITS<2>" LOC = "J1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L38N_M3DQ3
|
||||
NET "IOBITS<3>" LOC = "J3" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L38P_M3DQ2
|
||||
NET "IOBITS<26>" LOC = "H1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L39N_M3LDQSN
|
||||
NET "IOBITS<27>" LOC = "H2" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L39P_M3LDQS
|
||||
NET "IOBITS<50>" LOC = "G1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L40N_M3DQ7
|
||||
NET "IOBITS<51>" LOC = "G3" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L40P_M3DQ6
|
||||
NET "IOBITS<4>" LOC = "F1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L41N_C26_M3DQ5
|
||||
NET "IOBITS<5>" LOC = "F2" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L41P_C27_M3DQ4
|
||||
NET "IOBITS<28>" LOC = "E1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L46N_M3CLKN
|
||||
NET "IOBITS<29>" LOC = "E2" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L46P_M3CLK
|
||||
NET "IOBITS<52>" LOC = "D1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L49N_M3A2
|
||||
NET "IOBITS<53>" LOC = "D3" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L49P_M3A7
|
||||
NET "IOBITS<6>" LOC = "B1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L50N_M3BA2
|
||||
NET "IOBITS<7>" LOC = "C1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L50P_M3WE
|
||||
NET "IOBITS<30>" LOC = "C2" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L48N_M3BA1
|
||||
NET "IOBITS<31>" LOC = "C3" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L48P_M3BA0
|
||||
NET "IOBITS<54>" LOC = "A2" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L52N_M3A9
|
||||
NET "IOBITS<55>" LOC = "B2" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L52P_M3A8
|
||||
NET "IOBITS<8>" LOC = "A3" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L83N_VREF
|
||||
NET "IOBITS<9>" LOC = "B3" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L83P
|
||||
NET "IOBITS<32>" LOC = "A5" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L2N
|
||||
NET "IOBITS<33>" LOC = "B5" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L2P
|
||||
NET "IOBITS<56>" LOC = "A6" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L4N
|
||||
NET "IOBITS<57>" LOC = "B6" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L4P
|
||||
NET "IOBITS<10>" LOC = "A7" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L6N
|
||||
NET "IOBITS<11>" LOC = "C7" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L6P
|
||||
NET "IOBITS<34>" LOC = "A8" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L33N
|
||||
NET "IOBITS<35>" LOC = "B8" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L33P
|
||||
NET "IOBITS<58>" LOC = "A9" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L34N_C18
|
||||
NET "IOBITS<59>" LOC = "C9" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L34P_C19
|
||||
NET "IOBITS<12>" LOC = "A10" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L35N_C16
|
||||
NET "IOBITS<13>" LOC = "B10" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L35P_C17
|
||||
NET "IOBITS<36>" LOC = "A11" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L39N
|
||||
NET "IOBITS<37>" LOC = "C11" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L39P
|
||||
NET "IOBITS<60>" LOC = "A12" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L62N_VREF
|
||||
NET "IOBITS<61>" LOC = "B12" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L62P
|
||||
NET "IOBITS<14>" LOC = "A13" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L63N_SCP6
|
||||
NET "IOBITS<15>" LOC = "C13" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L63P_SCP7
|
||||
NET "IOBITS<38>" LOC = "A14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L65N_SCP2
|
||||
NET "IOBITS<39>" LOC = "B14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L65P_SCP3
|
||||
NET "IOBITS<62>" LOC = "B16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L29N_A22_M1A14
|
||||
NET "IOBITS<63>" LOC = "B15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L29P_A23_M1A13
|
||||
NET "IOBITS<16>" LOC = "C16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L33N_A14_M1A4
|
||||
NET "IOBITS<17>" LOC = "C15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L33P_A15_M1A10
|
||||
NET "IOBITS<40>" LOC = "D16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L31N_A18_M1A12
|
||||
NET "IOBITS<41>" LOC = "D14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L31P_A19_M1CKE
|
||||
NET "IOBITS<64>" LOC = "E16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L34N_A12_M1BA2
|
||||
NET "IOBITS<65>" LOC = "E15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L34P_A13_M1WE
|
||||
NET "IOBITS<18>" LOC = "F16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L35N_A10_M1A2
|
||||
NET "IOBITS<19>" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L35P_A11_M1A7
|
||||
NET "IOBITS<42>" LOC = "G16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L36N_A8_M1BA1
|
||||
NET "IOBITS<43>" LOC = "G14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L36P_A9_M1BA0
|
||||
NET "IOBITS<66>" LOC = "H16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L37N_A6_M1A1
|
||||
NET "IOBITS<67>" LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L37P_A7_M1A0
|
||||
NET "IOBITS<20>" LOC = "J16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L43N_C4_M1DQ5
|
||||
NET "IOBITS<21>" LOC = "J14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L43P_C5_M1DQ4
|
||||
NET "IOBITS<44>" LOC = "K16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L44N_A2_M1DQ7
|
||||
NET "IOBITS<45>" LOC = "K15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L44P_A3_M1DQ6
|
||||
NET "IOBITS<68>" LOC = "L16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L47N_LDC_M1DQ1
|
||||
NET "IOBITS<69>" LOC = "L14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L47P_FWE_M1DQ0
|
||||
NET "IOBITS<22>" LOC = "M16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L46N_FOE_M1DQ3
|
||||
NET "IOBITS<23>" LOC = "M15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L46P_FCS_M1DQ2
|
||||
NET "IOBITS<46>" LOC = "M14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L74N_DOUT_BUS 7I80HD only
|
||||
NET "IOBITS<47>" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L74P_AWAKE 7I80HD only
|
||||
NET "IOBITS<70>" LOC = "N16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L45N_A0_M1LDQS 7I80HD only
|
||||
NET "IOBITS<71>" LOC = "N14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank1 L45P_A1_M1LDQS 7I80HD only
|
||||
NET "LEDS<3>" LOC = "R2" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L32P_M3DQ14
|
||||
NET "LEDS<2>" LOC = "R1" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L32N_M3DQ15
|
||||
NET "LEDS<1>" LOC = "P2" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L33P_M3DQ12
|
||||
NET "LEDS<0>" LOC = "P1" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L33N_M3DQ13
|
||||
NET "OPTS<0>" LOC = "N3" ; # Bank3 L34P_M3UDQS
|
||||
NET "OPTS<1>" LOC = "N1" ; # Bank3 L34N_M3UDQSN
|
||||
NET "TP<0>" LOC = "M2" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank3 L35P_M3DQ10
|
||||
NET "TP<1>" LOC = "M1" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank3 L35N_M3DQ11
|
||||
NET "NINIT" LOC = "R3" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L65P_INIT_B
|
||||
|
||||
#NET "M<0>" LOC = "T11" ; # Bank2 L1N_M0_CMPMISO
|
||||
#NET "M<1>" LOC = "N11" ; # Bank2 L13P_M1
|
||||
#NET "HSWAPEN_<3>" LOC = "C4" ; # Bank0 L1P_HSWAPEN
|
||||
#NET "DONE" LOC = "P13" ; # Bank2 DONE
|
||||
#NET "PWRGD" LOC = "T2" ; # Bank2 PROGRAM_B
|
||||
#NET "FPGATCK" LOC = "C14" ; # Bank4 TCK
|
||||
#NET "FPGATDI" LOC = "C12" ; # Bank4 TDI
|
||||
#NET "FPGATDO" LOC = "E14" ; # Bank4 TDO
|
||||
#NET "FPGATMS" LOC = "A15" ; # Bank4 TMS
|
||||
#NET "<1.2V>" LOC = "G7" ; # Bank5 VCCINT
|
||||
#NET "<1.2V>" LOC = "G9" ; # Bank5 VCCINT
|
||||
#NET "<1.2V>" LOC = "H10" ; # Bank5 VCCINT
|
||||
#NET "<1.2V>" LOC = "H8" ; # Bank5 VCCINT
|
||||
#NET "<1.2V>" LOC = "J7" ; # Bank5 VCCINT
|
||||
#NET "<1.2V>" LOC = "J9" ; # Bank5 VCCINT
|
||||
#NET "<1.2V>" LOC = "K10" ; # Bank5 VCCINT
|
||||
#NET "<1.2V>" LOC = "K8" ; # Bank5 VCCINT
|
||||
#NET "<3.3V>" LOC = "B13" ; # Bank0 VCCO
|
||||
#NET "<3.3V>" LOC = "B4" ; # Bank0 VCCO
|
||||
#NET "<3.3V>" LOC = "B9" ; # Bank0 VCCO
|
||||
#NET "<3.3V>" LOC = "D10" ; # Bank0 VCCO
|
||||
#NET "<3.3V>" LOC = "D15" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "D2" ; # Bank3 VCCO
|
||||
#NET "<3.3V>" LOC = "D7" ; # Bank0 VCCO
|
||||
#NET "<3.3V>" LOC = "E5" ; # Bank5 VCCAUX
|
||||
#NET "<3.3V>" LOC = "F11" ; # Bank5 VCCAUX
|
||||
#NET "<3.3V>" LOC = "F8" ; # Bank5 VCCAUX
|
||||
#NET "<3.3V>" LOC = "G10" ; # Bank5 VCCAUX
|
||||
#NET "<3.3V>" LOC = "G13" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "G4" ; # Bank3 VCCO
|
||||
#NET "<3.3V>" LOC = "H6" ; # Bank5 VCCAUX
|
||||
#NET "<3.3V>" LOC = "J10" ; # Bank5 VCCAUX
|
||||
#NET "<3.3V>" LOC = "J15" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "J2" ; # Bank3 VCCO
|
||||
#NET "<3.3V>" LOC = "K13" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "K4" ; # Bank3 VCCO
|
||||
#NET "<3.3V>" LOC = "L11" ; # Bank2 CMPCS_B
|
||||
#NET "<3.3V>" LOC = "L6" ; # Bank5 VCCAUX
|
||||
#NET "<3.3V>" LOC = "L9" ; # Bank5 VCCAUX
|
||||
#NET "<3.3V>" LOC = "N10" ; # Bank2 VCCO
|
||||
#NET "<3.3V>" LOC = "N15" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "N2" ; # Bank3 VCCO
|
||||
#NET "<3.3V>" LOC = "N7" ; # Bank2 VCCO
|
||||
#NET "<3.3V>" LOC = "R13" ; # Bank1 VCCO
|
||||
#NET "<3.3V>" LOC = "R4" ; # Bank2 VCCO
|
||||
#NET "<3.3V>" LOC = "R8" ; # Bank2 VCCO
|
||||
#NET "GND" LOC = "A1" ; # Bank5 GND
|
||||
#NET "GND" LOC = "A16" ; # Bank5 GND
|
||||
#NET "GND" LOC = "B11" ; # Bank5 GND
|
||||
#NET "GND" LOC = "B7" ; # Bank5 GND
|
||||
#NET "GND" LOC = "D13" ; # Bank5 GND
|
||||
#NET "GND" LOC = "D4" ; # Bank5 GND
|
||||
#NET "GND" LOC = "E9" ; # Bank5 GND
|
||||
#NET "GND" LOC = "G15" ; # Bank5 GND
|
||||
#NET "GND" LOC = "G2" ; # Bank5 GND
|
||||
#NET "GND" LOC = "G8" ; # Bank5 GND
|
||||
#NET "GND" LOC = "H12" ; # Bank5 GND
|
||||
#NET "GND" LOC = "H7" ; # Bank5 GND
|
||||
#NET "GND" LOC = "H9" ; # Bank5 GND
|
||||
#NET "GND" LOC = "J5" ; # Bank5 GND
|
||||
#NET "GND" LOC = "J8" ; # Bank5 GND
|
||||
#NET "GND" LOC = "K7" ; # Bank5 GND
|
||||
#NET "GND" LOC = "K9" ; # Bank5 GND
|
||||
#NET "GND" LOC = "L15" ; # Bank5 GND
|
||||
#NET "GND" LOC = "L2" ; # Bank5 GND
|
||||
#NET "GND" LOC = "M8" ; # Bank5 GND
|
||||
#NET "GND" LOC = "N13" ; # Bank5 GND
|
||||
#NET "GND" LOC = "P3" ; # Bank5 GND
|
||||
#NET "GND" LOC = "R10" ; # Bank5 GND
|
||||
#NET "GND" LOC = "R6" ; # Bank5 GND
|
||||
#NET "GND" LOC = "T1" ; # Bank5 GND
|
||||
#NET "GND" LOC = "T16" ; # Bank5 GND
|
||||
#NET "NC" LOC = "A4" ; # Bank0 L1N_VREF
|
||||
#NET "NC" LOC = "C10" ; # Bank0 L37N_C12
|
||||
#NET "NC" LOC = "C5" ; # Bank0 L3N
|
||||
#NET "NC" LOC = "C6" ; # Bank0 L7N
|
||||
#NET "NC" LOC = "C8" ; # Bank0 L38N_VREF
|
||||
#NET "NC" LOC = "D11" ; # Bank0 L66P_SCP1
|
||||
#NET "NC" LOC = "D12" ; # Bank0 L66N_SCP0
|
||||
#NET "NC" LOC = "D5" ; # Bank0 L3P
|
||||
#NET "NC" LOC = "D6" ; # Bank0 L7P
|
||||
#NET "NC" LOC = "D8" ; # Bank0 L38P
|
||||
#NET "NC" LOC = "D9" ; # Bank0 L40N
|
||||
#NET "NC" LOC = "E10" ; # Bank0 L37P_C13
|
||||
#NET "NC" LOC = "E11" ; # Bank0 L64N_SCP4
|
||||
#NET "NC" LOC = "E12" ; # Bank1 L1N_A24_VREF
|
||||
#NET "NC" LOC = "E13" ; # Bank1 L1P_A25
|
||||
#NET "NC" LOC = "E3" ; # Bank3 L54N_M3A11
|
||||
#NET "NC" LOC = "E4" ; # Bank3 L54P_M3RESET
|
||||
#NET "NC" LOC = "E6" ; # Bank0 L5N
|
||||
#NET "NC" LOC = "E7" ; # Bank0 L36P_C15
|
||||
#NET "NC" LOC = "E8" ; # Bank0 L36N_C14
|
||||
#NET "NC" LOC = "F10" ; # Bank0 L64P_SCP5
|
||||
#NET "NC" LOC = "F12" ; # Bank1 L30P_A21_M1RST
|
||||
#NET "NC" LOC = "F13" ; # Bank1 L32P_A17_M1A8
|
||||
#NET "NC" LOC = "F14" ; # Bank1 L32N_A16_M1A9
|
||||
#NET "NC" LOC = "F3" ; # Bank3 L53N_M3A12
|
||||
#NET "NC" LOC = "F4" ; # Bank3 L53P_M3CKE
|
||||
#NET "NC" LOC = "F5" ; # Bank3 L55N_M3A14
|
||||
#NET "NC" LOC = "F6" ; # Bank3 L55P_M3A13
|
||||
#NET "NC" LOC = "F7" ; # Bank0 L5P
|
||||
#NET "NC" LOC = "F9" ; # Bank0 L40P
|
||||
#NET "NC" LOC = "G11" ; # Bank1 L30N_A20_M1A11
|
||||
#NET "NC" LOC = "G12" ; # Bank1 L38P_A5_M1CLK
|
||||
#NET "NC" LOC = "G5" ; # Bank3 L51N_M3A4
|
||||
#NET "NC" LOC = "G6" ; # Bank3 L51P_M3A10
|
||||
#NET "NC" LOC = "H11" ; # Bank1 L38N_A4_M1CLKN
|
||||
#NET "NC" LOC = "H13" ; # Bank1 L39P_M1A3
|
||||
#NET "NC" LOC = "H14" ; # Bank1 L39N_M1ODT
|
||||
#NET "NC" LOC = "H3" ; # Bank3 L44N_C20_M3A6
|
||||
#NET "NC" LOC = "H4" ; # Bank3 L44P_C21_M3A5
|
||||
#NET "NC" LOC = "H5" ; # Bank3 L43N_C22_M3CAS
|
||||
#NET "NC" LOC = "J11" ; # Bank1 L40P_C11_M1A5
|
||||
#NET "NC" LOC = "J12" ; # Bank1 L40N_C10_M1A6
|
||||
#NET "NC" LOC = "J13" ; # Bank1 L41P_C9_M1RAS
|
||||
#NET "NC" LOC = "J4" ; # Bank3 L42N_C24_M3LDM
|
||||
#NET "NC" LOC = "J6" ; # Bank3 L43P_C23_M3RAS
|
||||
#NET "NC" LOC = "K11" ; # Bank1 L42N_C6_M1LDM
|
||||
#NET "NC" LOC = "K12" ; # Bank1 L42P_C7_M1UDM
|
||||
#NET "NC" LOC = "K14" ; # Bank1 L41N_C8_M1CAS
|
||||
#NET "NC" LOC = "K3" ; # Bank3 L42P_C25_M3UDM
|
||||
#NET "NC" LOC = "K5" ; # Bank3 L47P_M3A0
|
||||
#NET "NC" LOC = "K6" ; # Bank3 L47N_M3A1
|
||||
#NET "NC" LOC = "L10" ; # Bank2 L16P
|
||||
#NET "NC" LOC = "L12" ; # Bank1 L53P
|
||||
#NET "NC" LOC = "L13" ; # Bank1 L53N_VREF
|
||||
#NET "NC" LOC = "L4" ; # Bank3 L45P_M3A3
|
||||
#NET "NC" LOC = "L5" ; # Bank3 L45N_M3ODT
|
||||
#NET "NC" LOC = "L7" ; # Bank2 L62N_D6
|
||||
#NET "NC" LOC = "L8" ; # Bank2 L62P_D5
|
||||
#NET "NC" LOC = "M10" ; # Bank2 L16N_VREF
|
||||
#NET "NC" LOC = "M11" ; # Bank2 L2N_CMPMOSI
|
||||
#NET "NC" LOC = "M12" ; # Bank2 L2P_CMPCLK
|
||||
#NET "NC" LOC = "M5" ; # Bank3 L2P
|
||||
#NET "NC" LOC = "M6" ; # Bank2 L64P_D8
|
||||
#NET "NC" LOC = "M7" ; # Bank2 L31N_C30_D15
|
||||
#NET "NC" LOC = "M9" ; # Bank2 L29P_C3
|
||||
#NET "NC" LOC = "N12" ; # Bank2 L12P_D1_MISO2
|
||||
#NET "NC" LOC = "N4" ; # Bank3 L2N
|
||||
#NET "NC" LOC = "N5" ; # Bank2 L49P_D3
|
||||
#NET "NC" LOC = "N6" ; # Bank2 L64N_D9
|
||||
#NET "NC" LOC = "N8" ; # Bank2 L29N_C2
|
||||
#NET "NC" LOC = "N9" ; # Bank2 L14P_D11
|
||||
#NET "NC" LOC = "P11" ; # Bank2 L13N_D10
|
||||
#NET "NC" LOC = "P12" ; # Bank2 L12N_D2_MISO3
|
||||
#NET "NC" LOC = "P14" ; # Bank4 SUSPEND
|
||||
#NET "NC" LOC = "R14" ; # Bank1 L50P_M1UDQS
|
||||
110
5i24/configs/hostmot2/source/7i90.ucf
Executable file
110
5i24/configs/hostmot2/source/7i90.ucf
Executable file
@@ -0,0 +1,110 @@
|
||||
NET "CLK" TNM_NET = "CLK";
|
||||
TIMESPEC "TS_CLK" = PERIOD "CLK" 19.9 ns HIGH 50 %;
|
||||
TIMESPEC "TS_P2P" = FROM "PADS" TO "PADS" 50 ns;
|
||||
NET "EPP_DATABUS<0>" LOC ="P43" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ;
|
||||
NET "EPP_DATABUS<1>" LOC ="P45" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ;
|
||||
NET "EPP_DATABUS<2>" LOC ="P47" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ;
|
||||
NET "EPP_DATABUS<3>" LOC ="P51" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ;
|
||||
NET "EPP_DATABUS<4>" LOC ="P55" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ;
|
||||
NET "EPP_DATABUS<5>" LOC ="P56" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ;
|
||||
NET "EPP_DATABUS<6>" LOC ="P57" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ;
|
||||
NET "EPP_DATABUS<7>" LOC ="P58" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ;
|
||||
NET "EPP_DSTROBE" LOC ="P41" | IOSTANDARD = LVTTL | PULLUP ;
|
||||
NET "EPP_ASTROBE" LOC ="P48" | IOSTANDARD = LVTTL | PULLUP ;
|
||||
NET "EPP_READ" LOC ="P40" | IOSTANDARD = LVTTL | PULLUP ;
|
||||
NET "EPP_WAIT" LOC ="P61" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ;
|
||||
NET "RECONFIG" LOC ="P67" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPICS" LOC ="P38" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPIIN" LOC ="P65" | IOSTANDARD = LVTTL;
|
||||
NET "SPIOUT" LOC ="P64" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPICLK" LOC ="P70" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "NINIT" LOC ="P39" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ;
|
||||
NET "CLK" LOC ="P50" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "LEDS<1>" LOC ="P74" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LEDS<0>" LOC ="P75" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<0>" LOC ="P35" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<1>" LOC ="P34" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<24>" LOC ="P33" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<25>" LOC ="P32" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<48>" LOC ="P30" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<49>" LOC ="P29" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<2>" LOC ="P27" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<3>" LOC ="P26" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<26>" LOC ="P24" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<27>" LOC ="P23" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<50>" LOC ="P22" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<51>" LOC ="P21" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<4>" LOC ="P17" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<5>" LOC ="P16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<28>" LOC ="P15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<29>" LOC ="P14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<52>" LOC ="P12" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<53>" LOC ="P11" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<6>" LOC ="P10" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<7>" LOC ="P9" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<30>" LOC ="P8" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<31>" LOC ="P7" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<54>" LOC ="P6" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<55>" LOC ="P5" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<8>" LOC ="P2" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<9>" LOC ="P1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<32>" LOC ="P142" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<33>" LOC ="P141" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<56>" LOC ="P140" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<57>" LOC ="P139" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<10>" LOC ="P138" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<11>" LOC ="P137" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<34>" LOC ="P134" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<35>" LOC ="P133" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<58>" LOC ="P132" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<59>" LOC ="P131" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<12>" LOC ="P127" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<13>" LOC ="P126" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<36>" LOC ="P124" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<37>" LOC ="P123" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<60>" LOC ="P121" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<61>" LOC ="P120" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<14>" LOC ="P119" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<15>" LOC ="P118" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<38>" LOC ="P117" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<39>" LOC ="P116" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<62>" LOC ="P115" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<63>" LOC ="P114" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<16>" LOC ="P112" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<17>" LOC ="P111" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<40>" LOC ="P105" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<41>" LOC ="P104" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<64>" LOC ="P102" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<65>" LOC ="P101" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<18>" LOC ="P100" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<19>" LOC ="P99" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<42>" LOC ="P98" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<43>" LOC ="P97" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<66>" LOC ="P95" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<67>" LOC ="P94" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<20>" LOC ="P93" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<21>" LOC ="P92" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<44>" LOC ="P88" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<45>" LOC ="P87" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<68>" LOC ="P85" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<69>" LOC ="P84" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<22>" LOC ="P83" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<23>" LOC ="P82" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<46>" LOC ="P81" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<47>" LOC ="P80" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<70>" LOC ="P79" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<71>" LOC ="P78" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
|
||||
NET "LIOBITS<0>" LOC ="P143" | IOSTANDARD = LVTTL ; #MISCCLK (RS-422 RXData in)
|
||||
NET "LIOBITS<1>" LOC ="P144" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; #HSWAPEN (RS-422 TXData out)
|
||||
NET "LIOBITS<2>" LOC ="P60" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; #M1 (RS-422 TXEN)
|
||||
|
||||
#NET "DONE" LOC ="P71" ;
|
||||
#NET "RDWR" LOC ="P47" ;
|
||||
#NET "PROGRAM" LOC ="P37" ;
|
||||
#NET "M0" LOC ="P69" ;
|
||||
#NET "FPGATMS" LOC ="P107" ;
|
||||
#NET "FPGATDI" LOC ="P110" ;
|
||||
#NET "FPGATDO" LOC ="P106" ;
|
||||
#NET "FPGACLK" LOC ="P109" ;
|
||||
#NET "HOST5" LOC ="P59" ;
|
||||
102
5i24/configs/hostmot2/source/7i90serhm2.ucf
Executable file
102
5i24/configs/hostmot2/source/7i90serhm2.ucf
Executable file
@@ -0,0 +1,102 @@
|
||||
NET "CLK" TNM_NET = "CLK";
|
||||
TIMESPEC "TS_CLK" = PERIOD "CLK" 19.9 ns HIGH 50 %;
|
||||
TIMESPEC "TS_P2P" = FROM "PADS" TO "PADS" 50 ns;
|
||||
NET "OPTS<1>" LOC ="P61" | IOSTANDARD = LVTTL ;
|
||||
NET "OPTS<0>" LOC ="P62" | IOSTANDARD = LVTTL ;
|
||||
NET "TP<1>" LOC ="P58" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "TP<0>" LOC ="P59" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "RECONFIG" LOC ="P67" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPICS" LOC ="P38" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPIIN" LOC ="P65" | IOSTANDARD = LVTTL;
|
||||
NET "SPIOUT" LOC ="P64" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPICLK" LOC ="P70" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "NINIT" LOC ="P39" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ;
|
||||
NET "CLK" LOC ="P50" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "LEDS<1>" LOC ="P74" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LEDS<0>" LOC ="P75" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<0>" LOC ="P35" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<1>" LOC ="P34" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<24>" LOC ="P33" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<25>" LOC ="P32" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<48>" LOC ="P30" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<49>" LOC ="P29" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<2>" LOC ="P27" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<3>" LOC ="P26" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<26>" LOC ="P24" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<27>" LOC ="P23" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<50>" LOC ="P22" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<51>" LOC ="P21" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<4>" LOC ="P17" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<5>" LOC ="P16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<28>" LOC ="P15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<29>" LOC ="P14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<52>" LOC ="P12" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<53>" LOC ="P11" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<6>" LOC ="P10" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<7>" LOC ="P9" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<30>" LOC ="P8" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<31>" LOC ="P7" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<54>" LOC ="P6" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<55>" LOC ="P5" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<8>" LOC ="P2" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<9>" LOC ="P1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<32>" LOC ="P142" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<33>" LOC ="P141" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<56>" LOC ="P140" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<57>" LOC ="P139" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<10>" LOC ="P138" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<11>" LOC ="P137" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<34>" LOC ="P134" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<35>" LOC ="P133" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<58>" LOC ="P132" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<59>" LOC ="P131" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<12>" LOC ="P127" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<13>" LOC ="P126" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<36>" LOC ="P124" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<37>" LOC ="P123" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<60>" LOC ="P121" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<61>" LOC ="P120" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<14>" LOC ="P119" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<15>" LOC ="P118" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<38>" LOC ="P117" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<39>" LOC ="P116" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<62>" LOC ="P115" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<63>" LOC ="P114" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<16>" LOC ="P112" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<17>" LOC ="P111" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<40>" LOC ="P105" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<41>" LOC ="P104" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<64>" LOC ="P102" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<65>" LOC ="P101" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<18>" LOC ="P100" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<19>" LOC ="P99" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<42>" LOC ="P98" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<43>" LOC ="P97" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<66>" LOC ="P95" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<67>" LOC ="P94" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<20>" LOC ="P93" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<21>" LOC ="P92" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<44>" LOC ="P88" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<45>" LOC ="P87" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<68>" LOC ="P85" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<69>" LOC ="P84" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<22>" LOC ="P83" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<23>" LOC ="P82" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<46>" LOC ="P81" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<47>" LOC ="P80" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<70>" LOC ="P79" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<71>" LOC ="P78" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
|
||||
NET "RXDATA" LOC ="P143" | IOSTANDARD = LVTTL ; #MISCCLK (RS-422 RXData in)
|
||||
NET "TXDATA" LOC ="P144" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; #HSWAPEN (RS-422 TXData out)
|
||||
NET "TXEN" LOC ="P60" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; #M1 (RS-422 TXEN)
|
||||
|
||||
#NET "DONE" LOC ="P71" ;
|
||||
#NET "RDWR" LOC ="P47" ;
|
||||
#NET "PROGRAM" LOC ="P37" ;
|
||||
#NET "M0" LOC ="P69" ;
|
||||
#NET "FPGATMS" LOC ="P107" ;
|
||||
#NET "FPGATDI" LOC ="P110" ;
|
||||
#NET "FPGATDO" LOC ="P106" ;
|
||||
#NET "FPGACLK" LOC ="P109" ;
|
||||
#NET "HOST5" LOC ="P59" ;
|
||||
110
5i24/configs/hostmot2/source/7i90spi.ucf
Executable file
110
5i24/configs/hostmot2/source/7i90spi.ucf
Executable file
@@ -0,0 +1,110 @@
|
||||
NET "CLK" TNM_NET = "CLK";
|
||||
TIMESPEC "TS_CLK" = PERIOD "CLK" 19.9 ns HIGH 50 %;
|
||||
|
||||
NET "COM_SPICLK" TNM_NET = "COM_SPICLK";
|
||||
TIMESPEC "TS_COM_SPICLK" = PERIOD "COM_SPICLK" 9 ns HIGH 50 %;
|
||||
|
||||
OFFSET = OUT 12 ns AFTER "COM_SPICLK" ;
|
||||
OFFSET = IN 8 ns BEFORE "COM_SPICLK" ;
|
||||
|
||||
NET "COM_SPICLK" LOC ="P55" | IOSTANDARD = LVTTL;
|
||||
NET "COM_SPIIN" LOC ="P56" | IOSTANDARD = LVTTL;
|
||||
NET "COM_SPIOUT" LOC ="P57" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = FAST ;
|
||||
NET "COM_SPICS" LOC ="P58" | IOSTANDARD = LVTTL;
|
||||
|
||||
NET "TEST0" LOC ="P59" | IOSTANDARD = LVTTL;
|
||||
|
||||
NET "RECONFIG" LOC ="P67" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPICS" LOC ="P38" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPIIN" LOC ="P65" | IOSTANDARD = LVTTL;
|
||||
NET "SPIOUT" LOC ="P64" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPICLK" LOC ="P70" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "NINIT" LOC ="P39" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ;
|
||||
NET "CLK" LOC ="P50" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "LEDS<1>" LOC ="P74" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LEDS<0>" LOC ="P75" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<0>" LOC ="P35" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<1>" LOC ="P34" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<24>" LOC ="P33" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<25>" LOC ="P32" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<48>" LOC ="P30" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<49>" LOC ="P29" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<2>" LOC ="P27" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<3>" LOC ="P26" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<26>" LOC ="P24" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<27>" LOC ="P23" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<50>" LOC ="P22" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<51>" LOC ="P21" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<4>" LOC ="P17" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<5>" LOC ="P16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<28>" LOC ="P15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<29>" LOC ="P14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<52>" LOC ="P12" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<53>" LOC ="P11" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<6>" LOC ="P10" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<7>" LOC ="P9" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<30>" LOC ="P8" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<31>" LOC ="P7" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<54>" LOC ="P6" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<55>" LOC ="P5" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<8>" LOC ="P2" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<9>" LOC ="P1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<32>" LOC ="P142" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<33>" LOC ="P141" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<56>" LOC ="P140" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<57>" LOC ="P139" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<10>" LOC ="P138" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<11>" LOC ="P137" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<34>" LOC ="P134" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<35>" LOC ="P133" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<58>" LOC ="P132" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<59>" LOC ="P131" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<12>" LOC ="P127" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<13>" LOC ="P126" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<36>" LOC ="P124" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<37>" LOC ="P123" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<60>" LOC ="P121" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<61>" LOC ="P120" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<14>" LOC ="P119" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<15>" LOC ="P118" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<38>" LOC ="P117" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<39>" LOC ="P116" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<62>" LOC ="P115" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<63>" LOC ="P114" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<16>" LOC ="P112" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<17>" LOC ="P111" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<40>" LOC ="P105" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<41>" LOC ="P104" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<64>" LOC ="P102" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<65>" LOC ="P101" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<18>" LOC ="P100" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<19>" LOC ="P99" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<42>" LOC ="P98" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<43>" LOC ="P97" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<66>" LOC ="P95" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<67>" LOC ="P94" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<20>" LOC ="P93" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<21>" LOC ="P92" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<44>" LOC ="P88" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<45>" LOC ="P87" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<68>" LOC ="P85" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<69>" LOC ="P84" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<22>" LOC ="P83" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<23>" LOC ="P82" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<46>" LOC ="P81" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<47>" LOC ="P80" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<70>" LOC ="P79" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<71>" LOC ="P78" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
|
||||
#NET "DONE" LOC ="P71" ;
|
||||
#NET "RDWR" LOC ="P47" ;
|
||||
#NET "PROGRAM" LOC ="P37" ;
|
||||
#NET "M0" LOC ="P69" ;
|
||||
#NET "M1" LOC ="P60" ;
|
||||
#NET "FPGATMS" LOC ="P107" ;
|
||||
#NET "FPGATDI" LOC ="P110" ;
|
||||
#NET "FPGATDO" LOC ="P106" ;
|
||||
#NET "FPGACLK" LOC ="P109" ;
|
||||
#NET "HSWAPEN" LOC ="P144" ;
|
||||
#NET "MISCCLK" LOC ="P143" ;
|
||||
#NET "HOST5" LOC ="P59" ;
|
||||
102
5i24/configs/hostmot2/source/7i90ssremote.ucf
Executable file
102
5i24/configs/hostmot2/source/7i90ssremote.ucf
Executable file
@@ -0,0 +1,102 @@
|
||||
NET "CLK" TNM_NET = "CLK";
|
||||
TIMESPEC "TS_CLK" = PERIOD "CLK" 19.9 ns HIGH 50 %;
|
||||
TIMESPEC "TS_P2P" = FROM "PADS" TO "PADS" 50 ns;
|
||||
NET "OPTS<1>" LOC ="P61" | IOSTANDARD = LVTTL ;
|
||||
NET "OPTS<0>" LOC ="P62" | IOSTANDARD = LVTTL ;
|
||||
NET "TP<1>" LOC ="P58" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "TP<0>" LOC ="P59" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "RECONFIG" LOC ="P67" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPICS" LOC ="P38" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPIIN" LOC ="P65" | IOSTANDARD = LVTTL;
|
||||
NET "SPIOUT" LOC ="P64" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPICLK" LOC ="P70" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "NINIT" LOC ="P39" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ;
|
||||
NET "CLK" LOC ="P50" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "LEDS<1>" LOC ="P74" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LEDS<0>" LOC ="P75" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<0>" LOC ="P35" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<1>" LOC ="P34" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<24>" LOC ="P33" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<25>" LOC ="P32" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<48>" LOC ="P30" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<49>" LOC ="P29" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<2>" LOC ="P27" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<3>" LOC ="P26" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<26>" LOC ="P24" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<27>" LOC ="P23" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<50>" LOC ="P22" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<51>" LOC ="P21" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<4>" LOC ="P17" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<5>" LOC ="P16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<28>" LOC ="P15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<29>" LOC ="P14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<52>" LOC ="P12" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<53>" LOC ="P11" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<6>" LOC ="P10" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<7>" LOC ="P9" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<30>" LOC ="P8" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<31>" LOC ="P7" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<54>" LOC ="P6" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<55>" LOC ="P5" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<8>" LOC ="P2" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<9>" LOC ="P1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<32>" LOC ="P142" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<33>" LOC ="P141" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<56>" LOC ="P140" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<57>" LOC ="P139" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<10>" LOC ="P138" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<11>" LOC ="P137" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<34>" LOC ="P134" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<35>" LOC ="P133" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<58>" LOC ="P132" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<59>" LOC ="P131" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<12>" LOC ="P127" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<13>" LOC ="P126" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<36>" LOC ="P124" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<37>" LOC ="P123" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<60>" LOC ="P121" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<61>" LOC ="P120" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<14>" LOC ="P119" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<15>" LOC ="P118" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<38>" LOC ="P117" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<39>" LOC ="P116" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<62>" LOC ="P115" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<63>" LOC ="P114" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<16>" LOC ="P112" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<17>" LOC ="P111" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<40>" LOC ="P105" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<41>" LOC ="P104" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<64>" LOC ="P102" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<65>" LOC ="P101" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<18>" LOC ="P100" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<19>" LOC ="P99" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<42>" LOC ="P98" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<43>" LOC ="P97" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<66>" LOC ="P95" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<67>" LOC ="P94" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<20>" LOC ="P93" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<21>" LOC ="P92" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<44>" LOC ="P88" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<45>" LOC ="P87" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<68>" LOC ="P85" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<69>" LOC ="P84" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<22>" LOC ="P83" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<23>" LOC ="P82" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<46>" LOC ="P81" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<47>" LOC ="P80" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<70>" LOC ="P79" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<71>" LOC ="P78" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
|
||||
NET "RXDATA" LOC ="P143" | IOSTANDARD = LVTTL ; #MISCCLK (RS-422 RXData in)
|
||||
NET "TXDATA" LOC ="P144" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; #HSWAPEN (RS-422 TXData out)
|
||||
NET "TXEN" LOC ="P60" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; #M1 (RS-422 TXEN)
|
||||
|
||||
#NET "DONE" LOC ="P71" ;
|
||||
#NET "RDWR" LOC ="P47" ;
|
||||
#NET "PROGRAM" LOC ="P37" ;
|
||||
#NET "M0" LOC ="P69" ;
|
||||
#NET "FPGATMS" LOC ="P107" ;
|
||||
#NET "FPGATDI" LOC ="P110" ;
|
||||
#NET "FPGATDO" LOC ="P106" ;
|
||||
#NET "FPGACLK" LOC ="P109" ;
|
||||
#NET "HOST5" LOC ="P59" ;
|
||||
111
5i24/configs/hostmot2/source/7i91spi.ucf
Executable file
111
5i24/configs/hostmot2/source/7i91spi.ucf
Executable file
@@ -0,0 +1,111 @@
|
||||
NET "CLK" TNM_NET = "CLK";
|
||||
TIMESPEC "TS_CLK" = PERIOD "CLK" 19.9 ns HIGH 50 %;
|
||||
|
||||
NET "COM_SPICLK" TNM_NET = "COM_SPICLK";
|
||||
TIMESPEC "TS_COM_SPICLK" = PERIOD "COM_SPICLK" 9 ns HIGH 50 %;
|
||||
|
||||
OFFSET = OUT 12 ns AFTER "COM_SPICLK" ;
|
||||
OFFSET = IN 8 ns BEFORE "COM_SPICLK" ;
|
||||
|
||||
NET "COM_SPICLK" LOC ="P56" | IOSTANDARD = LVTTL;
|
||||
NET "COM_SPIIN" LOC ="P57" | IOSTANDARD = LVTTL;
|
||||
NET "COM_SPICS" LOC ="P58" | IOSTANDARD = LVTTL;
|
||||
NET "COM_SPIOUT" LOC ="P59" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = FAST ;
|
||||
|
||||
# these next 5 are dunmmies
|
||||
NET "SPICS" LOC ="P38" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPIIN" LOC ="P65" | IOSTANDARD = LVTTL;
|
||||
NET "SPIOUT" LOC ="P64" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPICLK" LOC ="P70" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "TEST0" LOC ="P55" | IOSTANDARD = LVTTL;
|
||||
|
||||
NET "RECONFIG" LOC ="P67" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "NINIT" LOC ="P39" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ;
|
||||
NET "CLK" LOC ="P50" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "LEDS<1>" LOC ="P74" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LEDS<0>" LOC ="P75" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<0>" LOC ="P41" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<1>" LOC ="P40" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<24>" LOC ="P35" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<25>" LOC ="P34" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<48>" LOC ="P33" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<49>" LOC ="P32" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<2>" LOC ="P30" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<3>" LOC ="P29" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<26>" LOC ="P27" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<27>" LOC ="P26" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<50>" LOC ="P22" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<51>" LOC ="P21" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<4>" LOC ="P17" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<5>" LOC ="P16" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<28>" LOC ="P15" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<29>" LOC ="P14" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<52>" LOC ="P12" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<53>" LOC ="P11" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<6>" LOC ="P10" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<7>" LOC ="P9" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<30>" LOC ="P8" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<31>" LOC ="P7" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<54>" LOC ="P6" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<55>" LOC ="P5" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<8>" LOC ="P2" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<9>" LOC ="P1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<32>" LOC ="P142" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<33>" LOC ="P141" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<56>" LOC ="P140" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<57>" LOC ="P139" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<10>" LOC ="P138" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<11>" LOC ="P137" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<34>" LOC ="P134" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<35>" LOC ="P133" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<58>" LOC ="P132" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<59>" LOC ="P131" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<12>" LOC ="P127" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<13>" LOC ="P126" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<36>" LOC ="P124" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<37>" LOC ="P123" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<60>" LOC ="P121" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<61>" LOC ="P120" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<14>" LOC ="P119" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<15>" LOC ="P118" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<38>" LOC ="P117" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<39>" LOC ="P116" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<62>" LOC ="P115" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<63>" LOC ="P114" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<16>" LOC ="P112" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<17>" LOC ="P111" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<40>" LOC ="P105" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<41>" LOC ="P104" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<64>" LOC ="P102" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<65>" LOC ="P101" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<18>" LOC ="P100" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<19>" LOC ="P99" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<42>" LOC ="P98" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<43>" LOC ="P97" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<66>" LOC ="P95" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<67>" LOC ="P94" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<20>" LOC ="P93" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<21>" LOC ="P92" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<44>" LOC ="P88" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<45>" LOC ="P87" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<68>" LOC ="P85" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<69>" LOC ="P84" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<22>" LOC ="P83" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<23>" LOC ="P82" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<46>" LOC ="P81" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<47>" LOC ="P80" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<70>" LOC ="P79" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<71>" LOC ="P78" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
|
||||
#NET "DONE" LOC ="P71" ;
|
||||
#NET "RDWR" LOC ="P47" ;
|
||||
#NET "PROGRAM" LOC ="P37" ;
|
||||
#NET "M0" LOC ="P69" ;
|
||||
#NET "M1" LOC ="P60" ;
|
||||
#NET "FPGATMS" LOC ="P107" ;
|
||||
#NET "FPGATDI" LOC ="P110" ;
|
||||
#NET "FPGATDO" LOC ="P106" ;
|
||||
#NET "FPGACLK" LOC ="P109" ;
|
||||
#NET "HSWAPEN" LOC ="P144" ;
|
||||
#NET "MISCCLK" LOC ="P143" ;
|
||||
|
||||
74
5i24/configs/hostmot2/source/7i92.ucf
Executable file
74
5i24/configs/hostmot2/source/7i92.ucf
Executable file
@@ -0,0 +1,74 @@
|
||||
NET "CLK" TNM_NET = "CLK";
|
||||
TIMESPEC "TS_CLK" = PERIOD "CLK" 19.9 ns HIGH 50 %;
|
||||
NET "SPICLK" LOC = "P70" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L1P_CCLK
|
||||
NET "SPICS" LOC = "P38" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L65N_CSO_B
|
||||
NET "SPIIN" LOC = "P65" | IOSTANDARD = LVTTL; # Bank2 L3P_D0_MISO1
|
||||
NET "SPIOUT" LOC = "P64" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L3N_CSI_MISO0
|
||||
NET "ECLK" LOC = "P41" | IOSTANDARD = LVTTL | DRIVE = 4 ; # Bank1 L48N_M1DQ9
|
||||
NET "NECS" LOC = "P32" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L63N
|
||||
NET "ECMD" LOC = "P30" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L63P
|
||||
NET "NEREAD" LOC = "P34" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L48N_RDWR_VREF
|
||||
NET "NEWRITE" LOC = "P33" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L49N_D4
|
||||
NET "NERST" LOC = "P40" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L48P_HDC_M1DQ8
|
||||
NET "EINT" LOC = "P35" | IOSTANDARD = LVTTL | PULLUP; # Bank2 L48P_D7
|
||||
NET "CLK" LOC = "P50" | IOSTANDARD = LVTTL; # Bank2 L31P_C31_D14
|
||||
NET "ED<0>" LOC = "P7" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L47N
|
||||
NET "ED<1>" LOC = "P8" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L47P
|
||||
NET "ED<2>" LOC = "P9" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L32N_C28
|
||||
NET "ED<3>" LOC = "P10" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L32P_C29
|
||||
NET "ED<4>" LOC = "P11" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L30N_C0_USRCC
|
||||
NET "ED<5>" LOC = "P12" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L30P_C1_D13
|
||||
NET "ED<6>" LOC = "P14" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L14N_D12
|
||||
NET "ED<7>" LOC = "P15" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L23N
|
||||
NET "ED<8>" LOC = "P17" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L23P
|
||||
NET "ED<9>" LOC = "P21" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L52N_M1DQ15
|
||||
NET "ED<10>" LOC = "P22" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L52P_M1DQ14
|
||||
NET "ED<11>" LOC = "P23" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L51N_M1DQ13
|
||||
NET "ED<12>" LOC = "P24" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L51P_M1DQ12
|
||||
NET "ED<13>" LOC = "P26" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L50N_M1UDQSN
|
||||
NET "ED<14>" LOC = "P27" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L49N_M1DQ11
|
||||
NET "ED<15>" LOC = "P29" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L49P_M1DQ10
|
||||
NET "IOBITS<0>" LOC = "P142" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L1N_VREF
|
||||
NET "IOBITS<1>" LOC = "P140" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L1P
|
||||
NET "IOBITS<2>" LOC = "P138" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L36N_M3DQ9
|
||||
NET "IOBITS<3>" LOC = "P134" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L36P_M3DQ8
|
||||
NET "IOBITS<4>" LOC = "P132" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L37N_M3DQ1
|
||||
NET "IOBITS<5>" LOC = "P127" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L37P_M3DQ0
|
||||
NET "IOBITS<6>" LOC = "P124" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L38N_M3DQ3
|
||||
NET "IOBITS<7>" LOC = "P121" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L38P_M3DQ2
|
||||
NET "IOBITS<8>" LOC = "P119" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L39N_M3LDQSN
|
||||
NET "IOBITS<9>" LOC = "P117" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L39P_M3LDQS
|
||||
NET "IOBITS<10>" LOC = "P115" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L40N_M3DQ7
|
||||
NET "IOBITS<11>" LOC = "P112" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L40P_M3DQ6
|
||||
NET "IOBITS<12>" LOC = "P105" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L41N_C26_M3DQ5
|
||||
NET "IOBITS<13>" LOC = "P102" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L41P_C27_M3DQ4
|
||||
NET "IOBITS<14>" LOC = "P100" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L46N_M3CLKN
|
||||
NET "IOBITS<15>" LOC = "P98" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L46P_M3CLK
|
||||
NET "IOBITS<16>" LOC = "P95" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L49N_M3A2
|
||||
NET "IOBITS<17>" LOC = "P141" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L49P_M3A7
|
||||
NET "IOBITS<18>" LOC = "P139" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L50N_M3BA2
|
||||
NET "IOBITS<19>" LOC = "P137" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L50P_M3WE
|
||||
NET "IOBITS<20>" LOC = "P133" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L48N_M3BA1
|
||||
NET "IOBITS<21>" LOC = "P131" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L48P_M3BA0
|
||||
NET "IOBITS<22>" LOC = "P126" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L52N_M3A9
|
||||
NET "IOBITS<23>" LOC = "P123" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L52P_M3A8
|
||||
NET "IOBITS<24>" LOC = "P120" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L83N_VREF
|
||||
NET "IOBITS<25>" LOC = "P118" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L83P
|
||||
NET "IOBITS<26>" LOC = "P116" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L2N
|
||||
NET "IOBITS<27>" LOC = "P114" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L2P
|
||||
NET "IOBITS<28>" LOC = "P111" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L4N
|
||||
NET "IOBITS<29>" LOC = "P104" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L4P
|
||||
NET "IOBITS<30>" LOC = "P101" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L6N
|
||||
NET "IOBITS<31>" LOC = "P99" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L6P
|
||||
NET "IOBITS<32>" LOC = "P97" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L33N
|
||||
NET "IOBITS<33>" LOC = "P94" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L33P
|
||||
NET "LEDS<0>" LOC = "P1" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L32P_M3DQ14
|
||||
NET "LEDS<1>" LOC = "P2" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L32N_M3DQ15
|
||||
NET "LEDS<2>" LOC = "P5" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L33P_M3DQ12
|
||||
NET "LEDS<3>" LOC = "P6" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L33N_M3DQ13
|
||||
NET "OPTS<0>" LOC = "P79" | IOSTANDARD = LVTTL | PULLUP;
|
||||
NET "OPTS<1>" LOC = "P78" | IOSTANDARD = LVTTL | PULLUP;
|
||||
NET "TP<0>" LOC = "P81" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank3 L35P_M3DQ10
|
||||
NET "TP<1>" LOC = "P80" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank3 L35N_M3DQ11
|
||||
NET "NINIT" LOC = "P39" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L65P_INIT_B
|
||||
|
||||
88
5i24/configs/hostmot2/source/7i93.ucf
Executable file
88
5i24/configs/hostmot2/source/7i93.ucf
Executable file
@@ -0,0 +1,88 @@
|
||||
NET "CLK" TNM_NET = "CLK";
|
||||
TIMESPEC "TS_CLK" = PERIOD "CLK" 19.9 ns HIGH 50 %;
|
||||
NET "SPICLK" LOC = "P70" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L1P_CCLK
|
||||
NET "SPICS" LOC = "P38" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L65N_CSO_B
|
||||
NET "SPIIN" LOC = "P65" | IOSTANDARD = LVTTL; # Bank2 L3P_D0_MISO1
|
||||
NET "SPIOUT" LOC = "P64" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L3N_CSI_MISO0
|
||||
NET "ECLK" LOC = "P47" | IOSTANDARD = LVTTL | DRIVE = 4 ; # Bank1 L48N_M1DQ9
|
||||
NET "NECS" LOC = "P41" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L63N
|
||||
NET "ECMD" LOC = "P40" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L63P
|
||||
NET "NEREAD" LOC = "P44" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L48N_RDWR_VREF
|
||||
NET "NEWRITE" LOC = "P43" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L49N_D4
|
||||
NET "NERST" LOC = "P46" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L48P_HDC_M1DQ8
|
||||
NET "EINT" LOC = "P45" | IOSTANDARD = LVTTL | PULLUP; # Bank2 L48P_D7
|
||||
NET "CLK" LOC = "P50" | IOSTANDARD = LVTTL; # Bank2 L31P_C31_D14
|
||||
NET "ED<0>" LOC = "P14" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L47N
|
||||
NET "ED<1>" LOC = "P15" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L47P
|
||||
NET "ED<2>" LOC = "P16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L32N_C28
|
||||
NET "ED<3>" LOC = "P17" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L32P_C29
|
||||
NET "ED<4>" LOC = "P21" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L30N_C0_USRCC
|
||||
NET "ED<5>" LOC = "P22" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L30P_C1_D13
|
||||
NET "ED<6>" LOC = "P23" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L14N_D12
|
||||
NET "ED<7>" LOC = "P24" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L23N
|
||||
NET "ED<8>" LOC = "P26" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L23P
|
||||
NET "ED<9>" LOC = "P27" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L52N_M1DQ15
|
||||
NET "ED<10>" LOC = "P29" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L52P_M1DQ14
|
||||
NET "ED<11>" LOC = "P30" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L51N_M1DQ13
|
||||
NET "ED<12>" LOC = "P32" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L51P_M1DQ12
|
||||
NET "ED<13>" LOC = "P33" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L50N_M1UDQSN
|
||||
NET "ED<14>" LOC = "P34" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L49N_M1DQ11
|
||||
NET "ED<15>" LOC = "P35" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L49P_M1DQ10
|
||||
NET "IOBITS<0>" LOC = "P8" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L1N_VREF
|
||||
NET "IOBITS<1>" LOC = "P7" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L1P
|
||||
NET "IOBITS<2>" LOC = "P2" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L36N_M3DQ9
|
||||
NET "IOBITS<3>" LOC = "P1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L36P_M3DQ8
|
||||
NET "IOBITS<4>" LOC = "P140" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L37N_M3DQ1
|
||||
NET "IOBITS<5>" LOC = "P139" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L37P_M3DQ0
|
||||
NET "IOBITS<6>" LOC = "P134" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L38N_M3DQ3
|
||||
NET "IOBITS<7>" LOC = "P133" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L38P_M3DQ2
|
||||
NET "IOBITS<8>" LOC = "P127" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L39N_M3LDQSN
|
||||
NET "IOBITS<9>" LOC = "P126" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L39P_M3LDQS
|
||||
NET "IOBITS<10>" LOC = "P121" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L40N_M3DQ7
|
||||
NET "IOBITS<11>" LOC = "P120" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L40P_M3DQ6
|
||||
NET "IOBITS<12>" LOC = "P117" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L41N_C26_M3DQ5
|
||||
NET "IOBITS<13>" LOC = "P116" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L41P_C27_M3DQ4
|
||||
NET "IOBITS<14>" LOC = "P112" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L46N_M3CLKN
|
||||
NET "IOBITS<15>" LOC = "P111" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L46P_M3CLK
|
||||
NET "IOBITS<16>" LOC = "P102" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L49N_M3A2
|
||||
NET "IOBITS<17>" LOC = "P101" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L49P_M3A7
|
||||
NET "IOBITS<18>" LOC = "P98" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L50N_M3BA2
|
||||
NET "IOBITS<19>" LOC = "P97" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L50P_M3WE
|
||||
NET "IOBITS<20>" LOC = "P93" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L48N_M3BA1
|
||||
NET "IOBITS<21>" LOC = "P92" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L48P_M3BA0
|
||||
NET "IOBITS<22>" LOC = "P85" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L52N_M3A9
|
||||
NET "IOBITS<23>" LOC = "P84" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L52P_M3A8
|
||||
NET "IOBITS<24>" LOC = "P6" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L83N_VREF
|
||||
NET "IOBITS<25>" LOC = "P5" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank3 L83P
|
||||
NET "IOBITS<26>" LOC = "P142" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L2N
|
||||
NET "IOBITS<27>" LOC = "P141" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L2P
|
||||
NET "IOBITS<28>" LOC = "P138" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L4N
|
||||
NET "IOBITS<29>" LOC = "P137" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L4P
|
||||
NET "IOBITS<30>" LOC = "P132" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L6N
|
||||
NET "IOBITS<31>" LOC = "P131" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L6P
|
||||
NET "IOBITS<32>" LOC = "P124" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L33N
|
||||
NET "IOBITS<33>" LOC = "P123" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L33P
|
||||
NET "IOBITS<34>" LOC = "P119" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L33P
|
||||
NET "IOBITS<35>" LOC = "P118" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L33P
|
||||
NET "IOBITS<36>" LOC = "P115" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L33P
|
||||
NET "IOBITS<37>" LOC = "P114" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L33P
|
||||
NET "IOBITS<38>" LOC = "P105" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L33P
|
||||
NET "IOBITS<39>" LOC = "P104" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L33P
|
||||
NET "IOBITS<40>" LOC = "P100" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L33P
|
||||
NET "IOBITS<41>" LOC = "P99" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L33P
|
||||
NET "IOBITS<42>" LOC = "P95" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L33P
|
||||
NET "IOBITS<43>" LOC = "P94" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L33P
|
||||
NET "IOBITS<44>" LOC = "P88" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L33P
|
||||
NET "IOBITS<45>" LOC = "P87" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L33P
|
||||
NET "IOBITS<46>" LOC = "P83" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L33P
|
||||
NET "IOBITS<47>" LOC = "P82" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ; # Bank0 L33P
|
||||
NET "LEDS<0>" LOC = "P9" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L33N_M3DQ13
|
||||
NET "LEDS<1>" LOC = "P10" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L33P_M3DQ12
|
||||
NET "LEDS<2>" LOC = "P11" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L32N_M3DQ15
|
||||
NET "LEDS<3>" LOC = "P12" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L32P_M3DQ14
|
||||
NET "OPTS<0>" LOC = "P78" | IOSTANDARD = LVTTL | PULLUP;
|
||||
NET "OPTS<1>" LOC = "P75" | IOSTANDARD = LVTTL | PULLUP;
|
||||
NET "TP<0>" LOC = "P61" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank3 L35P_M3DQ10
|
||||
NET "TP<1>" LOC = "P62" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank3 L35N_M3DQ11
|
||||
NET "NINIT" LOC = "P39" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L65P_INIT_B
|
||||
|
||||
86
5i24/configs/hostmot2/source/7i94.ucf
Executable file
86
5i24/configs/hostmot2/source/7i94.ucf
Executable file
@@ -0,0 +1,86 @@
|
||||
NET "CLK" TNM_NET = "CLK";
|
||||
TIMESPEC "TS_CLK" = PERIOD "CLK" 19.9 ns HIGH 50 %;
|
||||
NET "SPICLK" LOC = "P70" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L1P_CCLK
|
||||
NET "SPICS" LOC = "P38" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L65N_CSO_B
|
||||
NET "SPIIN" LOC = "P65" | IOSTANDARD = LVTTL; # Bank2 L3P_D0_MISO1
|
||||
NET "SPIOUT" LOC = "P64" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L3N_CSI_MISO0
|
||||
NET "ECLK" LOC = "P35" | IOSTANDARD = LVTTL | DRIVE = 4 ; # Bank1 L48N_M1DQ9
|
||||
NET "NECS" LOC = "P7" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L63N
|
||||
NET "ECMD" LOC = "P6" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L63P
|
||||
NET "NEREAD" LOC = "P9" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L48N_RDWR_VREF
|
||||
NET "NEWRITE" LOC = "P8" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L49N_D4
|
||||
NET "NERST" LOC = "P34" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L48P_HDC_M1DQ8
|
||||
NET "EINT" LOC = "P33" | IOSTANDARD = LVTTL | PULLUP; # Bank2 L48P_D7
|
||||
NET "CLK" LOC = "P50" | IOSTANDARD = LVTTL; # Bank2 L31P_C31_D14
|
||||
NET "ED<0>" LOC = "P10" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L47N
|
||||
NET "ED<1>" LOC = "P11" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L47P
|
||||
NET "ED<2>" LOC = "P12" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L32N_C28
|
||||
NET "ED<3>" LOC = "P14" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L32P_C29
|
||||
NET "ED<4>" LOC = "P15" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L30N_C0_USRCC
|
||||
NET "ED<5>" LOC = "P16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L30P_C1_D13
|
||||
NET "ED<6>" LOC = "P17" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L14N_D12
|
||||
NET "ED<7>" LOC = "P21" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L23N
|
||||
NET "ED<8>" LOC = "P22" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L23P
|
||||
NET "ED<9>" LOC = "P23" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L52N_M1DQ15
|
||||
NET "ED<10>" LOC = "P24" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L52P_M1DQ14
|
||||
NET "ED<11>" LOC = "P26" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L51N_M1DQ13
|
||||
NET "ED<12>" LOC = "P27" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L51P_M1DQ12
|
||||
NET "ED<13>" LOC = "P29" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L50N_M1UDQSN
|
||||
NET "ED<14>" LOC = "P30" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L49N_M1DQ11
|
||||
NET "ED<15>" LOC = "P32" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L49P_M1DQ10
|
||||
|
||||
NET "IOBITS<0>" LOC = "P100" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<1>" LOC = "P99" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<2>" LOC = "P98" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<3>" LOC = "P97" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<4>" LOC = "P95" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<5>" LOC = "P94" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<6>" LOC = "P93" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<7>" LOC = "P92" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<8>" LOC = "P88" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<9>" LOC = "P87" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<10>" LOC = "P85" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<11>" LOC = "P84" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<12>" LOC = "P83" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<13>" LOC = "P82" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<14>" LOC = "P81" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<15>" LOC = "P80" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<16>" LOC = "P79" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<17>" LOC = "P44" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<18>" LOC = "P45" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<19>" LOC = "P46" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<20>" LOC = "P47" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
|
||||
NET "IOBITS<21>" LOC = "P48" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<22>" LOC = "P51" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<23>" LOC = "P55" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<24>" LOC = "P56" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<25>" LOC = "P57" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<26>" LOC = "P58" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<27>" LOC = "P59" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<28>" LOC = "P61" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<29>" LOC = "P111" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<30>" LOC = "P112" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<31>" LOC = "P114" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<32>" LOC = "P115" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<33>" LOC = "P116" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP;
|
||||
NET "IOBITS<34>" LOC = "P117" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<35>" LOC = "P123" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<36>" LOC = "P124" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<37>" LOC = "P126" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<38>" LOC = "P127" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<39>" LOC = "P131" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<40>" LOC = "P132" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<41>" LOC = "P101" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
|
||||
NET "LEDS<0>" LOC = "P118" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L33N_M3DQ13
|
||||
NET "LEDS<1>" LOC = "P119" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L33P_M3DQ12
|
||||
NET "LEDS<2>" LOC = "P120" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L32N_M3DQ15
|
||||
NET "LEDS<3>" LOC = "P121" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L32P_M3DQ14
|
||||
|
||||
NET "OPTS<0>" LOC = "P40" | IOSTANDARD = LVTTL | PULLUP;
|
||||
NET "OPTS<1>" LOC = "P41" | IOSTANDARD = LVTTL | PULLUP;
|
||||
NET "TP<0>" LOC = "P78" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank3 L35P_M3DQ10
|
||||
NET "TP<1>" LOC = "P75" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank3 L35N_M3DQ11
|
||||
NET "NINIT" LOC = "P39" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L65P_INIT_B
|
||||
|
||||
99
5i24/configs/hostmot2/source/7i95.ucf
Executable file
99
5i24/configs/hostmot2/source/7i95.ucf
Executable file
@@ -0,0 +1,99 @@
|
||||
NET "CLK" TNM_NET = "CLK";
|
||||
TIMESPEC "TS_CLK" = PERIOD "CLK" 19.9 ns HIGH 50 %;
|
||||
NET "SPICLK" LOC = "P70" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L1P_CCLK
|
||||
NET "SPICS" LOC = "P38" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L65N_CSO_B
|
||||
NET "SPIIN" LOC = "P65" | IOSTANDARD = LVTTL; # Bank2 L3P_D0_MISO1
|
||||
NET "SPIOUT" LOC = "P64" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L3N_CSI_MISO0
|
||||
NET "ECLK" LOC = "P47" | IOSTANDARD = LVTTL | DRIVE = 4 ; # Bank1 L48N_M1DQ9
|
||||
NET "NECS" LOC = "P41" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L63N
|
||||
NET "ECMD" LOC = "P40" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L63P
|
||||
NET "NEREAD" LOC = "P44" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L48N_RDWR_VREF
|
||||
NET "NEWRITE" LOC = "P43" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L49N_D4
|
||||
NET "NERST" LOC = "P46" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L48P_HDC_M1DQ8
|
||||
NET "EINT" LOC = "P45" | IOSTANDARD = LVTTL | PULLUP; # Bank2 L48P_D7
|
||||
NET "CLK" LOC = "P50" | IOSTANDARD = LVTTL; # Bank2 L31P_C31_D14
|
||||
NET "ED<0>" LOC = "P14" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L47N
|
||||
NET "ED<1>" LOC = "P15" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L47P
|
||||
NET "ED<2>" LOC = "P16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L32N_C28
|
||||
NET "ED<3>" LOC = "P17" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L32P_C29
|
||||
NET "ED<4>" LOC = "P21" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L30N_C0_USRCC
|
||||
NET "ED<5>" LOC = "P22" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L30P_C1_D13
|
||||
NET "ED<6>" LOC = "P23" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L14N_D12
|
||||
NET "ED<7>" LOC = "P24" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L23N
|
||||
NET "ED<8>" LOC = "P26" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L23P
|
||||
NET "ED<9>" LOC = "P27" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L52N_M1DQ15
|
||||
NET "ED<10>" LOC = "P29" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L52P_M1DQ14
|
||||
NET "ED<11>" LOC = "P30" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L51N_M1DQ13
|
||||
NET "ED<12>" LOC = "P32" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L51P_M1DQ12
|
||||
NET "ED<13>" LOC = "P33" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L50N_M1UDQSN
|
||||
NET "ED<14>" LOC = "P34" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L49N_M1DQ11
|
||||
NET "ED<15>" LOC = "P35" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L49P_M1DQ10
|
||||
NET "IOBITS<0>" LOC = "P116" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<1>" LOC = "P117" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<2>" LOC = "P118" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<3>" LOC = "P119" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<4>" LOC = "P124" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<5>" LOC = "P126" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<6>" LOC = "P127" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<7>" LOC = "P131" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<8>" LOC = "P62" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<9>" LOC = "P61" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<10>" LOC = "P132" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<11>" LOC = "P133" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<12>" LOC = "P134" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<13>" LOC = "P137" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<14>" LOC = "P138" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<15>" LOC = "P139" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<16>" LOC = "P140" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<17>" LOC = "P141" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<18>" LOC = "P142" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<19>" LOC = "P1" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<20>" LOC = "P2" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<21>" LOC = "P5" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<22>" LOC = "P6" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<23>" LOC = "P7" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<24>" LOC = "P8" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<25>" LOC = "P120" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<26>" LOC = "P121" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<27>" LOC = "P123" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<28>" LOC = "P57" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
|
||||
NET "IOBITS<29>" LOC = "P58" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<30>" LOC = "P59" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<31>" LOC = "P56" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<32>" LOC = "P55" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<33>" LOC = "P51" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<34>" LOC = "P115" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<35>" LOC = "P114" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<36>" LOC = "P112" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<37>" LOC = "P111" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<38>" LOC = "P105" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<39>" LOC = "P104" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<40>" LOC = "P102" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<41>" LOC = "P101" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<42>" LOC = "P100" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<43>" LOC = "P99" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<44>" LOC = "P98" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<45>" LOC = "P97" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<46>" LOC = "P95" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<47>" LOC = "P94" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<48>" LOC = "P93" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<49>" LOC = "P92" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<50>" LOC = "P88" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<51>" LOC = "P48" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<52>" LOC = "P87" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<53>" LOC = "P85" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<54>" LOC = "P84" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<55>" LOC = "P83" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<56>" LOC = "P82" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<57>" LOC = "P81" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LEDS<0>" LOC = "P9" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L33N_M3DQ13
|
||||
NET "LEDS<1>" LOC = "P10" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L33P_M3DQ12
|
||||
NET "LEDS<2>" LOC = "P11" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L32N_M3DQ15
|
||||
NET "LEDS<3>" LOC = "P12" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L32P_M3DQ14
|
||||
NET "OPTS<0>" LOC = "P78" | IOSTANDARD = LVTTL | PULLUP;
|
||||
NET "OPTS<1>" LOC = "P75" | IOSTANDARD = LVTTL | PULLUP;
|
||||
NET "TP<0>" LOC = "P80" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank3 L35P_M3DQ10
|
||||
NET "TP<1>" LOC = "P79" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank3 L35N_M3DQ11
|
||||
NET "NINIT" LOC = "P39" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L65P_INIT_B
|
||||
|
||||
93
5i24/configs/hostmot2/source/7i96.ucf
Executable file
93
5i24/configs/hostmot2/source/7i96.ucf
Executable file
@@ -0,0 +1,93 @@
|
||||
NET "CLK" TNM_NET = "CLK";
|
||||
TIMESPEC "TS_CLK" = PERIOD "CLK" 19.9 ns HIGH 50 %;
|
||||
NET "SPICLK" LOC = "P70" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L1P_CCLK
|
||||
NET "SPICS" LOC = "P38" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L65N_CSO_B
|
||||
NET "SPIIN" LOC = "P65" | IOSTANDARD = LVTTL; # Bank2 L3P_D0_MISO1
|
||||
NET "SPIOUT" LOC = "P64" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L3N_CSI_MISO0
|
||||
NET "ECLK" LOC = "P47" | IOSTANDARD = LVTTL | DRIVE = 4 ; # Bank1 L48N_M1DQ9
|
||||
NET "NECS" LOC = "P41" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L63N
|
||||
NET "ECMD" LOC = "P40" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L63P
|
||||
NET "NEREAD" LOC = "P44" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L48N_RDWR_VREF
|
||||
NET "NEWRITE" LOC = "P43" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L49N_D4
|
||||
NET "NERST" LOC = "P46" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L48P_HDC_M1DQ8
|
||||
NET "EINT" LOC = "P45" | IOSTANDARD = LVTTL | PULLUP; # Bank2 L48P_D7
|
||||
NET "CLK" LOC = "P50" | IOSTANDARD = LVTTL; # Bank2 L31P_C31_D14
|
||||
NET "ED<0>" LOC = "P14" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L47N
|
||||
NET "ED<1>" LOC = "P15" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L47P
|
||||
NET "ED<2>" LOC = "P16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L32N_C28
|
||||
NET "ED<3>" LOC = "P17" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L32P_C29
|
||||
NET "ED<4>" LOC = "P21" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L30N_C0_USRCC
|
||||
NET "ED<5>" LOC = "P22" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L30P_C1_D13
|
||||
NET "ED<6>" LOC = "P23" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L14N_D12
|
||||
NET "ED<7>" LOC = "P24" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L23N
|
||||
NET "ED<8>" LOC = "P26" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L23P
|
||||
NET "ED<9>" LOC = "P27" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L52N_M1DQ15
|
||||
NET "ED<10>" LOC = "P29" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L52P_M1DQ14
|
||||
NET "ED<11>" LOC = "P30" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L51N_M1DQ13
|
||||
NET "ED<12>" LOC = "P32" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L51P_M1DQ12
|
||||
NET "ED<13>" LOC = "P33" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L50N_M1UDQSN
|
||||
NET "ED<14>" LOC = "P34" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L49N_M1DQ11
|
||||
NET "ED<15>" LOC = "P35" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L49P_M1DQ10
|
||||
NET "IOBITS<0>" LOC = "P101" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<1>" LOC = "P102" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<2>" LOC = "P104" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<3>" LOC = "P105" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<4>" LOC = "P114" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<5>" LOC = "P115" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<6>" LOC = "P116" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<7>" LOC = "P117" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<8>" LOC = "P118" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<9>" LOC = "P119" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<10>" LOC = "P120" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<11>" LOC = "P126" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<12>" LOC = "P127" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<13>" LOC = "P131" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<14>" LOC = "P138" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<15>" LOC = "P139" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<16>" LOC = "P140" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
|
||||
NET "IOBITS<17>" LOC = "P141" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<18>" LOC = "P142" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<19>" LOC = "P1" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<20>" LOC = "P2" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<21>" LOC = "P5" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<22>" LOC = "P6" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<23>" LOC = "P7" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<24>" LOC = "P8" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<25>" LOC = "P111" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<26>" LOC = "P112" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<27>" LOC = "P121" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<28>" LOC = "P123" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<29>" LOC = "P124" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<30>" LOC = "P132" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<31>" LOC = "P133" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<32>" LOC = "P134" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<33>" LOC = "P137" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW | PULLUP;
|
||||
|
||||
NET "IOBITS<34>" LOC = "P100" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<35>" LOC = "P99" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<36>" LOC = "P98" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<37>" LOC = "P97" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<38>" LOC = "P95" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<39>" LOC = "P94" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<40>" LOC = "P93" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<41>" LOC = "P92" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<42>" LOC = "P88" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<43>" LOC = "P87" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<44>" LOC = "P85" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<45>" LOC = "P84" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<46>" LOC = "P83" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<47>" LOC = "P82" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<48>" LOC = "P81" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<49>" LOC = "P80" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<50>" LOC = "P79" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LEDS<0>" LOC = "P9" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L33N_M3DQ13
|
||||
NET "LEDS<1>" LOC = "P10" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L33P_M3DQ12
|
||||
NET "LEDS<2>" LOC = "P11" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L32N_M3DQ15
|
||||
NET "LEDS<3>" LOC = "P12" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L32P_M3DQ14
|
||||
NET "OPTS<0>" LOC = "P78" | IOSTANDARD = LVTTL | PULLUP;
|
||||
NET "OPTS<1>" LOC = "P75" | IOSTANDARD = LVTTL | PULLUP;
|
||||
NET "TP<0>" LOC = "P61" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank3 L35P_M3DQ10
|
||||
NET "TP<1>" LOC = "P62" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank3 L35N_M3DQ11
|
||||
NET "NINIT" LOC = "P39" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L65P_INIT_B
|
||||
|
||||
95
5i24/configs/hostmot2/source/7i97.ucf
Executable file
95
5i24/configs/hostmot2/source/7i97.ucf
Executable file
@@ -0,0 +1,95 @@
|
||||
NET "CLK" TNM_NET = "CLK";
|
||||
TIMESPEC "TS_CLK" = PERIOD "CLK" 19.9 ns HIGH 50 %;
|
||||
NET "SPICLK" LOC = "P70" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L1P_CCLK
|
||||
NET "SPICS" LOC = "P38" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L65N_CSO_B
|
||||
NET "SPIIN" LOC = "P65" | IOSTANDARD = LVTTL; # Bank2 L3P_D0_MISO1
|
||||
NET "SPIOUT" LOC = "P64" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L3N_CSI_MISO0
|
||||
NET "ECLK" LOC = "P47" | IOSTANDARD = LVTTL | DRIVE = 4 ; # Bank1 L48N_M1DQ9
|
||||
NET "NECS" LOC = "P41" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L63N
|
||||
NET "ECMD" LOC = "P40" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L63P
|
||||
NET "NEREAD" LOC = "P44" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L48N_RDWR_VREF
|
||||
NET "NEWRITE" LOC = "P43" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L49N_D4
|
||||
NET "NERST" LOC = "P46" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L48P_HDC_M1DQ8
|
||||
NET "EINT" LOC = "P45" | IOSTANDARD = LVTTL | PULLUP; # Bank2 L48P_D7
|
||||
NET "CLK" LOC = "P50" | IOSTANDARD = LVTTL; # Bank2 L31P_C31_D14
|
||||
NET "ED<0>" LOC = "P14" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L47N
|
||||
NET "ED<1>" LOC = "P15" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L47P
|
||||
NET "ED<2>" LOC = "P16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L32N_C28
|
||||
NET "ED<3>" LOC = "P17" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L32P_C29
|
||||
NET "ED<4>" LOC = "P21" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L30N_C0_USRCC
|
||||
NET "ED<5>" LOC = "P22" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L30P_C1_D13
|
||||
NET "ED<6>" LOC = "P23" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L14N_D12
|
||||
NET "ED<7>" LOC = "P24" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L23N
|
||||
NET "ED<8>" LOC = "P26" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L23P
|
||||
NET "ED<9>" LOC = "P27" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L52N_M1DQ15
|
||||
NET "ED<10>" LOC = "P29" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L52P_M1DQ14
|
||||
NET "ED<11>" LOC = "P30" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L51N_M1DQ13
|
||||
NET "ED<12>" LOC = "P32" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L51P_M1DQ12
|
||||
NET "ED<13>" LOC = "P33" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L50N_M1UDQSN
|
||||
NET "ED<14>" LOC = "P34" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L49N_M1DQ11
|
||||
NET "ED<15>" LOC = "P35" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L49P_M1DQ10
|
||||
NET "IOBITS<0>" LOC = "P101" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<1>" LOC = "P102" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<2>" LOC = "P104" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<3>" LOC = "P105" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<4>" LOC = "P114" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<5>" LOC = "P115" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<6>" LOC = "P116" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<7>" LOC = "P117" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<8>" LOC = "P118" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<9>" LOC = "P119" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<10>" LOC = "P120" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<11>" LOC = "P126" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<12>" LOC = "P127" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<13>" LOC = "P131" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<14>" LOC = "P138" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<15>" LOC = "P139" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<16>" LOC = "P140" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
|
||||
NET "IOBITS<17>" LOC = "P141" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<18>" LOC = "P142" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<19>" LOC = "P1" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<20>" LOC = "P2" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<21>" LOC = "P5" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<22>" LOC = "P6" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<23>" LOC = "P7" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<24>" LOC = "P8" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<25>" LOC = "P111" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<26>" LOC = "P112" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<27>" LOC = "P121" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<28>" LOC = "P123" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<29>" LOC = "P124" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<30>" LOC = "P132" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<31>" LOC = "P133" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<32>" LOC = "P134" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<33>" LOC = "P137" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW | PULLUP;
|
||||
|
||||
NET "IOBITS<34>" LOC = "P100" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<35>" LOC = "P99" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<36>" LOC = "P98" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<37>" LOC = "P97" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<38>" LOC = "P95" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<39>" LOC = "P94" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<40>" LOC = "P93" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<41>" LOC = "P92" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<42>" LOC = "P88" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<43>" LOC = "P87" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<44>" LOC = "P85" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<45>" LOC = "P84" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<46>" LOC = "P83" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<47>" LOC = "P82" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<48>" LOC = "P81" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<49>" LOC = "P80" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<50>" LOC = "P79" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LEDS<0>" LOC = "P9" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L33N_M3DQ13
|
||||
NET "LEDS<1>" LOC = "P10" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L33P_M3DQ12
|
||||
NET "LEDS<2>" LOC = "P11" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L32N_M3DQ15
|
||||
NET "LEDS<3>" LOC = "P12" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L32P_M3DQ14
|
||||
NET "OPTS<0>" LOC = "P78" | IOSTANDARD = LVTTL | PULLUP;
|
||||
NET "OPTS<1>" LOC = "P75" | IOSTANDARD = LVTTL | PULLUP;
|
||||
NET "TP<0>" LOC = "P61" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank3 L35P_M3DQ10
|
||||
NET "TP<1>" LOC = "P62" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank3 L35N_M3DQ11
|
||||
NET "NINIT" LOC = "P39" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L65P_INIT_B
|
||||
NET "LIOBITS<0>" LOC = "P55" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank2 L65P_INIT_B
|
||||
NET "LIOBITS<1>" LOC = "P56" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank2 L65P_INIT_B
|
||||
|
||||
93
5i24/configs/hostmot2/source/7i98.ucf
Executable file
93
5i24/configs/hostmot2/source/7i98.ucf
Executable file
@@ -0,0 +1,93 @@
|
||||
NET "CLK" TNM_NET = "CLK";
|
||||
TIMESPEC "TS_CLK" = PERIOD "CLK" 19.9 ns HIGH 50 %;
|
||||
NET "SPICLK" LOC = "P70" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L1P_CCLK
|
||||
NET "SPICS" LOC = "P38" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L65N_CSO_B
|
||||
NET "SPIIN" LOC = "P65" | IOSTANDARD = LVTTL; # Bank2 L3P_D0_MISO1
|
||||
NET "SPIOUT" LOC = "P64" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L3N_CSI_MISO0
|
||||
NET "ECLK" LOC = "P47" | IOSTANDARD = LVTTL | DRIVE = 4 ; # Bank1 L48N_M1DQ9
|
||||
NET "NECS" LOC = "P41" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L63N
|
||||
NET "ECMD" LOC = "P40" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L63P
|
||||
NET "NEREAD" LOC = "P44" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L48N_RDWR_VREF
|
||||
NET "NEWRITE" LOC = "P43" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L49N_D4
|
||||
NET "NERST" LOC = "P46" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L48P_HDC_M1DQ8
|
||||
NET "EINT" LOC = "P45" | IOSTANDARD = LVTTL | PULLUP; # Bank2 L48P_D7
|
||||
NET "CLK" LOC = "P50" | IOSTANDARD = LVTTL; # Bank2 L31P_C31_D14
|
||||
NET "ED<0>" LOC = "P14" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L47N
|
||||
NET "ED<1>" LOC = "P15" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L47P
|
||||
NET "ED<2>" LOC = "P16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L32N_C28
|
||||
NET "ED<3>" LOC = "P17" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L32P_C29
|
||||
NET "ED<4>" LOC = "P21" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L30N_C0_USRCC
|
||||
NET "ED<5>" LOC = "P22" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L30P_C1_D13
|
||||
NET "ED<6>" LOC = "P23" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L14N_D12
|
||||
NET "ED<7>" LOC = "P24" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L23N
|
||||
NET "ED<8>" LOC = "P26" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L23P
|
||||
NET "ED<9>" LOC = "P27" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L52N_M1DQ15
|
||||
NET "ED<10>" LOC = "P29" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L52P_M1DQ14
|
||||
NET "ED<11>" LOC = "P30" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L51N_M1DQ13
|
||||
NET "ED<12>" LOC = "P32" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L51P_M1DQ12
|
||||
NET "ED<13>" LOC = "P33" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L50N_M1UDQSN
|
||||
NET "ED<14>" LOC = "P34" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L49N_M1DQ11
|
||||
NET "ED<15>" LOC = "P35" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank1 L49P_M1DQ10
|
||||
NET "IOBITS<0>" LOC = "P8" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<1>" LOC = "P7" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<2>" LOC = "P6" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<3>" LOC = "P5" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<4>" LOC = "P2" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<5>" LOC = "P1" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<6>" LOC = "P142" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<7>" LOC = "P141" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<8>" LOC = "P140" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<9>" LOC = "P139" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<10>" LOC = "P138" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<11>" LOC = "P137" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<12>" LOC = "P134" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<13>" LOC = "P133" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<14>" LOC = "P132" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<15>" LOC = "P131" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<16>" LOC = "P127" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
|
||||
NET "IOBITS<17>" LOC = "P126" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<18>" LOC = "P124" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<19>" LOC = "P123" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<20>" LOC = "P121" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<21>" LOC = "P120" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<22>" LOC = "P119" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<23>" LOC = "P118" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<24>" LOC = "P117" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<25>" LOC = "P116" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<26>" LOC = "P115" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW | PULLUP ;
|
||||
NET "IOBITS<27>" LOC = "P114" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<28>" LOC = "P112" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<29>" LOC = "P111" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<30>" LOC = "P105" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<31>" LOC = "P104" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<32>" LOC = "P102" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<33>" LOC = "P101" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW | PULLUP;
|
||||
|
||||
NET "IOBITS<34>" LOC = "P100" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<35>" LOC = "P99" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<36>" LOC = "P98" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<37>" LOC = "P97" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<38>" LOC = "P95" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<39>" LOC = "P94" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<40>" LOC = "P93" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<41>" LOC = "P92" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<42>" LOC = "P88" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<43>" LOC = "P87" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<44>" LOC = "P85" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<45>" LOC = "P84" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<46>" LOC = "P83" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<47>" LOC = "P82" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<48>" LOC = "P81" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<49>" LOC = "P80" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "IOBITS<50>" LOC = "P79" | IOSTANDARD = LVTTL | DRIVE = 24 | SLEW = SLOW ;
|
||||
NET "LEDS<0>" LOC = "P9" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L33N_M3DQ13
|
||||
NET "LEDS<1>" LOC = "P10" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L33P_M3DQ12
|
||||
NET "LEDS<2>" LOC = "P11" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L32N_M3DQ15
|
||||
NET "LEDS<3>" LOC = "P12" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; # Bank3 L32P_M3DQ14
|
||||
NET "OPTS<0>" LOC = "P78" | IOSTANDARD = LVTTL | PULLUP;
|
||||
NET "OPTS<1>" LOC = "P75" | IOSTANDARD = LVTTL | PULLUP;
|
||||
NET "TP<0>" LOC = "P61" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank3 L35P_M3DQ10
|
||||
NET "TP<1>" LOC = "P62" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank3 L35N_M3DQ11
|
||||
NET "NINIT" LOC = "P39" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; # Bank2 L65P_INIT_B
|
||||
|
||||
84
5i24/configs/hostmot2/source/7ia0ssremote.ucf
Executable file
84
5i24/configs/hostmot2/source/7ia0ssremote.ucf
Executable file
@@ -0,0 +1,84 @@
|
||||
NET "CLK" TNM_NET = "CLK";
|
||||
TIMESPEC "TS_CLK" = PERIOD "CLK" 19.9 ns HIGH 50 %;
|
||||
TIMESPEC "TS_P2P" = FROM "PADS" TO "PADS" 50 ns;
|
||||
NET "OPTS<1>" LOC ="P127" | IOSTANDARD = LVTTL ;
|
||||
NET "OPTS<0>" LOC ="P131" | IOSTANDARD = LVTTL ;
|
||||
NET "TP<1>" LOC ="P105" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; #DUMMY
|
||||
NET "TP<0>" LOC ="P111" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ; #DUMMY
|
||||
NET "RECONFIG" LOC ="P112" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; #DUMMY
|
||||
NET "SPICS" LOC ="P38" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPIIN" LOC ="P65" | IOSTANDARD = LVTTL;
|
||||
NET "SPIOUT" LOC ="P64" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "SPICLK" LOC ="P70" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "NINIT" LOC ="P39" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ;
|
||||
NET "CLK" LOC ="P134" | IOSTANDARD = LVTTL ;
|
||||
NET "LEDS<3>" LOC ="P140" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LEDS<2>" LOC ="P141" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LEDS<1>" LOC ="P142" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "LEDS<0>" LOC ="P143" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<0>" LOC ="P1" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<1>" LOC ="P2" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<2>" LOC ="P5" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<3>" LOC ="P6" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<4>" LOC ="P7" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<5>" LOC ="P8" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<6>" LOC ="P9" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<7>" LOC ="P10" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<8>" LOC ="P11" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<9>" LOC ="P12" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<10>" LOC ="P14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<11>" LOC ="P15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<12>" LOC ="P16" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<13>" LOC ="P17" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<14>" LOC ="P21" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<15>" LOC ="P22" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<16>" LOC ="P23" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<17>" LOC ="P24" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<18>" LOC ="P26" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<19>" LOC ="P27" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<20>" LOC ="P29" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<21>" LOC ="P30" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<22>" LOC ="P32" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<23>" LOC ="P33" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
|
||||
NET "IOBITS<24>" LOC ="P34" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
|
||||
NET "IOBITS<25>" LOC ="P92" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<26>" LOC ="P88" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<27>" LOC ="P87" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<28>" LOC ="P93" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<29>" LOC ="P94" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<30>" LOC ="P95" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<31>" LOC ="P99" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<32>" LOC ="P98" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<33>" LOC ="P97" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<34>" LOC ="P100" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<35>" LOC ="P101" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<36>" LOC ="P102" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
NET "IOBITS<37>" LOC ="P104" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
|
||||
|
||||
NET "LIOBITS<0>" LOC ="P40" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ;
|
||||
NET "LIOBITS<1>" LOC ="P41" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ;
|
||||
NET "LIOBITS<2>" LOC ="P43" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ;
|
||||
NET "LIOBITS<3>" LOC ="P44" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ;
|
||||
NET "LIOBITS<4>" LOC ="P47" | IOSTANDARD = "LVDS_33" | DIFF_TERM = FALSE ;
|
||||
NET "LIOBITS<5>" LOC ="P48" | IOSTANDARD = "LVDS_33" | DIFF_TERM = FALSE ;
|
||||
NET "LIOBITS<6>" LOC ="P50" | IOSTANDARD = "LVDS_33" | DIFF_TERM = FALSE ;
|
||||
NET "LIOBITS<7>" LOC ="P51" | IOSTANDARD = "LVDS_33" | DIFF_TERM = FALSE ;
|
||||
NET "LIOBITS<8>" LOC ="P55" | IOSTANDARD = "LVDS_33" | DIFF_TERM = FALSE ;
|
||||
NET "LIOBITS<9>" LOC ="P56" | IOSTANDARD = "LVDS_33" | DIFF_TERM = FALSE ;
|
||||
NET "LIOBITS<10>" LOC ="P57" | IOSTANDARD = "LVDS_33" | DIFF_TERM = FALSE ;
|
||||
NET "LIOBITS<11>" LOC ="P58" | IOSTANDARD = "LVDS_33" | DIFF_TERM = FALSE ;
|
||||
NET "LIOBITS<12>" LOC ="P59" | IOSTANDARD = LVTTL | DRIVE = 12 | SLEW = SLOW ;
|
||||
|
||||
NET "RXDATA" LOC ="P123" | IOSTANDARD = LVTTL ; #MISCCLK (RS-422 RXData in)
|
||||
NET "TXDATA" LOC ="P121" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; #HSWAPEN (RS-422 TXData out)
|
||||
NET "TXEN" LOC ="P120" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ; #M1 (RS-422 TXEN)
|
||||
|
||||
#NET "DONE" LOC ="P71" ;
|
||||
#NET "RDWR" LOC ="P47" ;
|
||||
#NET "PROGRAM" LOC ="P37" ;
|
||||
#NET "M0" LOC ="P69" ;
|
||||
#NET "FPGATMS" LOC ="P107" ;
|
||||
#NET "FPGATDI" LOC ="P110" ;
|
||||
#NET "FPGATDO" LOC ="P106" ;
|
||||
#NET "FPGACLK" LOC ="P109" ;
|
||||
#NET "HOST5" LOC ="P59" ;
|
||||
90
5i24/configs/hostmot2/source/CountPinsInRange.vhd
Executable file
90
5i24/configs/hostmot2/source/CountPinsInRange.vhd
Executable file
@@ -0,0 +1,90 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
package CountPinsInRange is
|
||||
function CountPinsInRange(PD : PinDescType; Tag : std_logic_vector(7 downto 0); low : std_logic_vector(7 downto 0); high:std_logic_vector(7 downto 0)) return integer;
|
||||
end CountPinsInRange;
|
||||
|
||||
package body CountPinsInRange is
|
||||
|
||||
function CountPinsInRange(PD : PinDescType; Tag : std_logic_vector(7 downto 0); low : std_logic_vector(7 downto 0); high:std_logic_vector(7 downto 0)) return integer is
|
||||
variable result: integer;
|
||||
begin
|
||||
result := 0;
|
||||
for i in 0 to MaxPins-1 loop
|
||||
if (Tag = PD(i)(15 downto 8)) and (PD(i)(23 downto 16) = x"00") then -- if GTag matches and first instance
|
||||
if (PD(i)(7 downto 0) >= conv_integer(low)) and (PD(i)(7 downto 0) <= conv_integer(high)) then -- in range
|
||||
result := result+1; -- count pins that match GTag and in range
|
||||
end if;
|
||||
end if;
|
||||
end loop;
|
||||
return result;
|
||||
end;
|
||||
end CountPinsInRange;
|
||||
88
5i24/configs/hostmot2/source/GetModuleHint.vhd
Executable file
88
5i24/configs/hostmot2/source/GetModuleHint.vhd
Executable file
@@ -0,0 +1,88 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
package GetModuleHint is
|
||||
function GetModuleHint(MID : ModuleIDType; Tag : std_logic_vector(7 downto 0)) return integer;
|
||||
end GetModuleHint;
|
||||
|
||||
package body GetModuleHint is
|
||||
|
||||
function GetModuleHint(MID : ModuleIDType; Tag : std_logic_vector(7 downto 0)) return integer is
|
||||
variable result: integer;
|
||||
begin
|
||||
result := 0;
|
||||
for i in 0 to MaxModules-1 loop
|
||||
if Tag = MID(i).GTag then
|
||||
result := conv_integer(MID(i).MultRegs); -- hide hints in the multreg register for now
|
||||
end if;
|
||||
end loop;
|
||||
return result;
|
||||
end;
|
||||
end GetModuleHint;
|
||||
1267
5i24/configs/hostmot2/source/IDROMConst.vhd
Executable file
1267
5i24/configs/hostmot2/source/IDROMConst.vhd
Executable file
File diff suppressed because it is too large
Load Diff
1189
5i24/configs/hostmot2/source/IDROMConst_str.vhd
Executable file
1189
5i24/configs/hostmot2/source/IDROMConst_str.vhd
Executable file
File diff suppressed because it is too large
Load Diff
94
5i24/configs/hostmot2/source/InputPinsPerModule.vhd
Executable file
94
5i24/configs/hostmot2/source/InputPinsPerModule.vhd
Executable file
@@ -0,0 +1,94 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
package InputPinsPerModule is
|
||||
function InputPinsPerModule(PD : PinDescType; Tag : std_logic_vector(7 downto 0); Instance : integer) return integer;
|
||||
end InputPinsPerModule;
|
||||
|
||||
package body InputPinsPerModule is
|
||||
|
||||
function InputPinsPerModule(PD : PinDescType; Tag : std_logic_vector(7 downto 0); Instance : integer) return integer is
|
||||
variable result: integer;
|
||||
begin
|
||||
result := 0;
|
||||
for i in 0 to MaxPins-1 loop
|
||||
if Instance = PD(i)(23 downto 16) then -- if instance matches
|
||||
if PD(i)(7) = '0' then -- and its an input
|
||||
if Tag = PD(i)(15 downto 8) then -- if GTag matches
|
||||
if PD(i)(5 downto 0) > result then -- drop MSB and NMSB to allow 2 input types
|
||||
result := conv_integer(PD(i)(5 downto 0)); -- find max (63 max)
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end loop;
|
||||
return result;
|
||||
end;
|
||||
end InputPinsPerModule;
|
||||
92
5i24/configs/hostmot2/source/MaxIOPinsPerModule.vhd
Executable file
92
5i24/configs/hostmot2/source/MaxIOPinsPerModule.vhd
Executable file
@@ -0,0 +1,92 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
package MaxIOPinsPerModule is
|
||||
function MaxIOPinsPerModule(PD : PinDescType; Tag : std_logic_vector(7 downto 0)) return integer;
|
||||
end MaxIOPinsPerModule;
|
||||
|
||||
package body MaxIOPinsPerModule is
|
||||
|
||||
function MaxIOPinsPerModule(PD : PinDescType; Tag : std_logic_vector(7 downto 0)) return integer is
|
||||
variable result: integer;
|
||||
begin
|
||||
result := 0;
|
||||
for i in 0 to MaxPins-1 loop
|
||||
if Tag = PD(i)(15 downto 8) then -- if GTag matches
|
||||
if PD(i)(7 downto 6) = "11" then -- and its an IO
|
||||
if PD(i)(5 downto 0) > result then -- drop MSB and NMSB to allow 2 IO types
|
||||
result := conv_integer(PD(i)(5 downto 0)); -- find max (63 max)
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end loop;
|
||||
return result;
|
||||
end;
|
||||
end MaxIOPinsPerModule;
|
||||
92
5i24/configs/hostmot2/source/MaxInputPinsPerModule.vhd
Executable file
92
5i24/configs/hostmot2/source/MaxInputPinsPerModule.vhd
Executable file
@@ -0,0 +1,92 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
package MaxInputPinsPerModule is
|
||||
function MaxInputPinsPerModule(PD : PinDescType; Tag : std_logic_vector(7 downto 0)) return integer;
|
||||
end MaxInputPinsPerModule;
|
||||
|
||||
package body MaxInputPinsPerModule is
|
||||
|
||||
function MaxInputPinsPerModule(PD : PinDescType; Tag : std_logic_vector(7 downto 0)) return integer is
|
||||
variable result: integer;
|
||||
begin
|
||||
result := 0;
|
||||
for i in 0 to MaxPins-1 loop
|
||||
if Tag = PD(i)(15 downto 8) then -- if GTag matches
|
||||
if PD(i)(7) = '0' then -- and its an input
|
||||
if PD(i)(5 downto 0) > result then -- drop MSB and NMSB to allow 2 input types
|
||||
result := conv_integer(PD(i)(5 downto 0)); -- find max (63 max)
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end loop;
|
||||
return result;
|
||||
end;
|
||||
end MaxInputPinsPerModule;
|
||||
92
5i24/configs/hostmot2/source/MaxOutputPinsPerModule.vhd
Executable file
92
5i24/configs/hostmot2/source/MaxOutputPinsPerModule.vhd
Executable file
@@ -0,0 +1,92 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
package MaxOutputPinsPerModule is
|
||||
function MaxOutputPinsPerModule(PD : PinDescType; Tag : std_logic_vector(7 downto 0)) return integer;
|
||||
end MaxOutputPinsPerModule;
|
||||
|
||||
package body MaxOutputPinsPerModule is
|
||||
|
||||
function MaxOutputPinsPerModule(PD : PinDescType; Tag : std_logic_vector(7 downto 0)) return integer is
|
||||
variable result: integer;
|
||||
begin
|
||||
result := 0;
|
||||
for i in 0 to MaxPins-1 loop
|
||||
if Tag = PD(i)(15 downto 8) then -- if GTag matches
|
||||
if PD(i)(7) = '1' then -- and its an Output
|
||||
if PD(i)(5 downto 0) > result then -- drop MSB and NMSB to allow 2 Output types
|
||||
result := conv_integer(PD(i)(5 downto 0)); -- find max (63 max)
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end loop;
|
||||
return result;
|
||||
end;
|
||||
end MaxOutputPinsPerModule;
|
||||
90
5i24/configs/hostmot2/source/MaxPinsPerModule.vhd
Executable file
90
5i24/configs/hostmot2/source/MaxPinsPerModule.vhd
Executable file
@@ -0,0 +1,90 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
package MaxPinsPerModule is
|
||||
function MaxPinsPerModule(PD : PinDescType; Tag : std_logic_vector(7 downto 0)) return integer;
|
||||
end MaxPinsPerModule;
|
||||
|
||||
package body MaxPinsPerModule is
|
||||
|
||||
function MaxPinsPerModule(PD : PinDescType; Tag : std_logic_vector(7 downto 0)) return integer is
|
||||
variable result: integer;
|
||||
begin
|
||||
result := 0;
|
||||
for i in 0 to MaxPins-1 loop
|
||||
if Tag = PD(i)(15 downto 8) then -- if GTag matches
|
||||
if PD(i)(6 downto 0) > result then -- drop MSB output flag
|
||||
result := conv_integer(PD(i)(6 downto 0)); -- find max
|
||||
end if;
|
||||
end if;
|
||||
end loop;
|
||||
return result;
|
||||
end;
|
||||
end MaxPinsPerModule;
|
||||
88
5i24/configs/hostmot2/source/ModuleExists.vhd
Executable file
88
5i24/configs/hostmot2/source/ModuleExists.vhd
Executable file
@@ -0,0 +1,88 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
package ModuleExists is
|
||||
function ModuleExists(MID : ModuleIDType; Tag : std_logic_vector(7 downto 0)) return boolean;
|
||||
end ModuleExists;
|
||||
|
||||
package body ModuleExists is
|
||||
|
||||
function ModuleExists(MID : ModuleIDType; Tag : std_logic_vector(7 downto 0)) return boolean is
|
||||
variable result: boolean;
|
||||
begin
|
||||
result := false;
|
||||
for i in 0 to MaxModules-1 loop
|
||||
if Tag = MID(i).GTag then -- if GTag matches
|
||||
result := true;
|
||||
end if;
|
||||
end loop;
|
||||
return result;
|
||||
end;
|
||||
end ModuleExists;
|
||||
88
5i24/configs/hostmot2/source/ModuleVersion.vhd
Executable file
88
5i24/configs/hostmot2/source/ModuleVersion.vhd
Executable file
@@ -0,0 +1,88 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
package ModuleVersion is
|
||||
function ModuleVersion(MID : ModuleIDType; Tag : std_logic_vector(7 downto 0)) return integer;
|
||||
end ModuleVersion;
|
||||
|
||||
package body ModuleVersion is
|
||||
|
||||
function ModuleVersion(MID : ModuleIDType; Tag : std_logic_vector(7 downto 0)) return integer is
|
||||
variable result: integer;
|
||||
begin
|
||||
result := 0;
|
||||
for i in 0 to MaxModules-1 loop
|
||||
if Tag = MID(i).GTag then
|
||||
result := conv_integer(MID(i).Version);
|
||||
end if;
|
||||
end loop;
|
||||
return result;
|
||||
end;
|
||||
end ModuleVersion;
|
||||
88
5i24/configs/hostmot2/source/NumberOfModules.vhd
Executable file
88
5i24/configs/hostmot2/source/NumberOfModules.vhd
Executable file
@@ -0,0 +1,88 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
package NumberOfModules is
|
||||
function NumberOfModules(MID : ModuleIDType; Tag : std_logic_vector(7 downto 0)) return integer;
|
||||
end NumberOfModules;
|
||||
|
||||
package body NumberOfModules is
|
||||
|
||||
function NumberOfModules(MID : ModuleIDType; Tag : std_logic_vector(7 downto 0)) return integer is
|
||||
variable result: integer;
|
||||
begin
|
||||
result := 0;
|
||||
for i in 0 to MaxModules-1 loop
|
||||
if Tag = MID(i).GTag then
|
||||
result := conv_integer(MID(i).NumInstances);
|
||||
end if;
|
||||
end loop;
|
||||
return result;
|
||||
end;
|
||||
end NumberOfModules;
|
||||
209
5i24/configs/hostmot2/source/OutputInteg.vhd
Executable file
209
5i24/configs/hostmot2/source/OutputInteg.vhd
Executable file
@@ -0,0 +1,209 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.std_logic_arith.all;
|
||||
use ieee.std_logic_unsigned.all;
|
||||
--
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
use work.log2.all;
|
||||
|
||||
entity OutputInteg is -- 8 channel integrator/accumulator with accumlators readable by host
|
||||
port ( dspdin : in std_logic_vector (31 downto 0);
|
||||
dspdout : out std_logic_vector (31 downto 0);
|
||||
hostdout : out std_logic_vector (31 downto 0);
|
||||
dspraddr : in std_logic_vector (2 downto 0);
|
||||
dspwaddr : in std_logic_vector (2 downto 0);
|
||||
hostaddr : in std_logic_vector (2 downto 0);
|
||||
loadvel : in std_logic;
|
||||
loadrate : in std_logic;
|
||||
dspread : in std_logic;
|
||||
hostread : in std_logic;
|
||||
testout : out std_logic;
|
||||
clk : in std_logic);
|
||||
end OutputInteg;
|
||||
|
||||
architecture Behavioral of OutputInteg is
|
||||
constant divwidth :integer := 16;
|
||||
constant channels : integer := 8;
|
||||
constant offset : integer := 8; -- accumulator runs 256 times faster than host sample rate so sr by 8
|
||||
constant csize : integer := log2(channels);
|
||||
constant width : integer := 32;
|
||||
|
||||
signal acca: std_logic_vector(width-1 downto 0);
|
||||
signal accb: std_logic_vector(width-1 downto 0);
|
||||
signal accsum: std_logic_vector(width-1 downto 0);
|
||||
signal rawhostdout: std_logic_vector(width-1 downto 0);
|
||||
signal rawdspdout: std_logic_vector(width-1 downto 0);
|
||||
signal offsetdin: std_logic_vector(width-1 downto 0);
|
||||
signal smaddr: std_logic_vector(log2(channels)-1 downto 0);
|
||||
signal smwrite: std_logic;
|
||||
signal run: std_logic;
|
||||
signal ratereg: std_logic_vector(divwidth-1 downto 0);
|
||||
signal ratediv: std_logic_vector(divwidth-1 downto 0);
|
||||
alias ratedivmsb: std_logic is ratediv(divwidth-1);
|
||||
signal oldratedivmsb: std_logic;
|
||||
|
||||
begin
|
||||
|
||||
inputdpram: entity work.dpram
|
||||
generic map (
|
||||
width => width,
|
||||
depth => channels
|
||||
)
|
||||
port map(
|
||||
addra => dspwaddr,
|
||||
addrb => smaddr,
|
||||
clk => clk,
|
||||
dina => offsetdin,
|
||||
-- douta =>
|
||||
doutb => acca,
|
||||
wea => loadvel
|
||||
);
|
||||
|
||||
feedbackdpram: entity work.dpram
|
||||
generic map (
|
||||
width => width,
|
||||
depth => channels
|
||||
)
|
||||
port map(
|
||||
addra => smaddr,
|
||||
addrb => dspraddr,
|
||||
clk => clk,
|
||||
dina => accsum,
|
||||
douta => accb,
|
||||
doutb => rawdspdout,
|
||||
wea => smwrite
|
||||
);
|
||||
|
||||
outputdpram: entity work.dpram
|
||||
generic map (
|
||||
width => width,
|
||||
depth => channels
|
||||
)
|
||||
port map(
|
||||
addra => smaddr,
|
||||
addrb => hostaddr,
|
||||
clk => clk,
|
||||
dina => accsum,
|
||||
-- douta => snugglebunnies,
|
||||
doutb => rawhostdout,
|
||||
wea => smwrite
|
||||
);
|
||||
|
||||
|
||||
accumulator: process(clk,acca,accb, dspdin, hostread,
|
||||
rawhostdout, dspread, rawdspdout, smwrite) -- multi channel accumulator
|
||||
begin
|
||||
if rising_edge(clk) then
|
||||
ratediv <= ratediv + ratereg;
|
||||
if ratedivmsb /= oldratedivmsb then
|
||||
smaddr <= conv_std_logic_vector(0,csize);
|
||||
smwrite <= '0'; -- start channel processing at channel 0 read
|
||||
run <= '1';
|
||||
end if;
|
||||
|
||||
if run = '1' then
|
||||
if smwrite = '1' then -- if write asserted, increment channel
|
||||
if smaddr = conv_std_logic_vector(channels -1,csize) then
|
||||
run <= '0'; -- if last channel stop till next rate req
|
||||
else
|
||||
smaddr <= smaddr +1;
|
||||
end if;
|
||||
end if;
|
||||
smwrite <= not smwrite; -- alternate read/write per channel
|
||||
end if;
|
||||
|
||||
oldratedivmsb <= ratedivmsb;
|
||||
|
||||
if loadrate = '1' then
|
||||
ratereg <= dspdin(divwidth-1 downto 0);
|
||||
end if;
|
||||
|
||||
end if; -- clk
|
||||
|
||||
accsum <= acca + accb;
|
||||
|
||||
offsetdin(width-offset-1 downto 0) <= dspdin(width-1 downto offset);
|
||||
if dspdin(width -1) = '1' then -- sign extend
|
||||
offsetdin(width-1 downto width-offset) <= (others => '1');
|
||||
else
|
||||
offsetdin(width-1 downto width-offset) <= (others => '0');
|
||||
end if;
|
||||
|
||||
|
||||
hostdout <= (others => 'Z');
|
||||
if hostread = '1' then
|
||||
hostdout <= rawhostdout;
|
||||
end if;
|
||||
|
||||
dspdout <= (others => 'Z');
|
||||
if dspread = '1' then
|
||||
dspdout <= rawdspdout;
|
||||
end if;
|
||||
|
||||
testout <= smwrite;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
94
5i24/configs/hostmot2/source/OutputPinsPerModule.vhd
Executable file
94
5i24/configs/hostmot2/source/OutputPinsPerModule.vhd
Executable file
@@ -0,0 +1,94 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
package OutputPinsPerModule is
|
||||
function OutputPinsPerModule(PD : PinDescType; Tag : std_logic_vector(7 downto 0); Instance : integer) return integer;
|
||||
end OutputPinsPerModule;
|
||||
|
||||
package body OutputPinsPerModule is
|
||||
|
||||
function OutputPinsPerModule(PD : PinDescType; Tag : std_logic_vector(7 downto 0); Instance : integer) return integer is
|
||||
variable result: integer;
|
||||
begin
|
||||
result := 0;
|
||||
for i in 0 to MaxPins-1 loop
|
||||
if Instance = PD(i)(23 downto 16) then -- if instance matches
|
||||
if PD(i)(7) = '1' then -- and its an Output
|
||||
if Tag = PD(i)(15 downto 8) then -- if GTag matches
|
||||
if PD(i)(5 downto 0) > result then -- drop MSB and NMSB to allow 2 Output types
|
||||
result := conv_integer(PD(i)(5 downto 0)); -- find max (63 max)
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end loop;
|
||||
return result;
|
||||
end;
|
||||
end OutputPinsPerModule;
|
||||
197
5i24/configs/hostmot2/source/PIN_24XQCTRONLY_72.vhd
Executable file
197
5i24/configs/hostmot2/source/PIN_24XQCTRONLY_72.vhd
Executable file
@@ -0,0 +1,197 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_24XQCTRONLY_72 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"18", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin
|
||||
IOPortTag & x"00" & QCountTag & x"01", -- I/O 00
|
||||
IOPortTag & x"00" & QCountTag & x"02", -- I/O 01
|
||||
IOPortTag & x"00" & QCountTag & x"03", -- I/O 02
|
||||
IOPortTag & x"01" & QCountTag & x"01", -- I/O 03
|
||||
IOPortTag & x"01" & QCountTag & x"02", -- I/O 04
|
||||
IOPortTag & x"01" & QCountTag & x"03", -- I/O 05
|
||||
IOPortTag & x"02" & QCountTag & x"01", -- I/O 06
|
||||
IOPortTag & x"02" & QCountTag & x"02", -- I/O 07
|
||||
IOPortTag & x"02" & QCountTag & x"03", -- I/O 08
|
||||
IOPortTag & x"03" & QCountTag & x"01", -- I/O 09
|
||||
IOPortTag & x"03" & QCountTag & x"02", -- I/O 10
|
||||
IOPortTag & x"03" & QCountTag & x"03", -- I/O 11
|
||||
IOPortTag & x"04" & QCountTag & x"01", -- I/O 12
|
||||
IOPortTag & x"04" & QCountTag & x"02", -- I/O 13
|
||||
IOPortTag & x"04" & QCountTag & x"03", -- I/O 14
|
||||
IOPortTag & x"05" & QCountTag & x"01", -- I/O 15
|
||||
IOPortTag & x"05" & QCountTag & x"02", -- I/O 16
|
||||
IOPortTag & x"05" & QCountTag & x"03", -- I/O 17
|
||||
IOPortTag & x"06" & QCountTag & x"01", -- I/O 18
|
||||
IOPortTag & x"06" & QCountTag & x"02", -- I/O 19
|
||||
IOPortTag & x"06" & QCountTag & x"03", -- I/O 20
|
||||
IOPortTag & x"07" & QCountTag & x"01", -- I/O 21
|
||||
IOPortTag & x"07" & QCountTag & x"02", -- I/O 22
|
||||
IOPortTag & x"07" & QCountTag & x"03", -- I/O 23
|
||||
|
||||
IOPortTag & x"08" & QCountTag & x"01", -- I/O 24
|
||||
IOPortTag & x"08" & QCountTag & x"02", -- I/O 25
|
||||
IOPortTag & x"08" & QCountTag & x"03", -- I/O 26
|
||||
IOPortTag & x"09" & QCountTag & x"01", -- I/O 27
|
||||
IOPortTag & x"09" & QCountTag & x"02", -- I/O 28
|
||||
IOPortTag & x"09" & QCountTag & x"03", -- I/O 29
|
||||
IOPortTag & x"0A" & QCountTag & x"01", -- I/O 30
|
||||
IOPortTag & x"0A" & QCountTag & x"02", -- I/O 31
|
||||
IOPortTag & x"0A" & QCountTag & x"03", -- I/O 32
|
||||
IOPortTag & x"0B" & QCountTag & x"01", -- I/O 33
|
||||
IOPortTag & x"0B" & QCountTag & x"02", -- I/O 34
|
||||
IOPortTag & x"0B" & QCountTag & x"03", -- I/O 35
|
||||
IOPortTag & x"0C" & QCountTag & x"01", -- I/O 36
|
||||
IOPortTag & x"0C" & QCountTag & x"02", -- I/O 37
|
||||
IOPortTag & x"0C" & QCountTag & x"03", -- I/O 38
|
||||
IOPortTag & x"0D" & QCountTag & x"01", -- I/O 39
|
||||
IOPortTag & x"0D" & QCountTag & x"02", -- I/O 40
|
||||
IOPortTag & x"0D" & QCountTag & x"03", -- I/O 41
|
||||
IOPortTag & x"0E" & QCountTag & x"01", -- I/O 42
|
||||
IOPortTag & x"0E" & QCountTag & x"02", -- I/O 43
|
||||
IOPortTag & x"0E" & QCountTag & x"03", -- I/O 44
|
||||
IOPortTag & x"0F" & QCountTag & x"01", -- I/O 45
|
||||
IOPortTag & x"0F" & QCountTag & x"02", -- I/O 46
|
||||
IOPortTag & x"0F" & QCountTag & x"03", -- I/O 47
|
||||
|
||||
IOPortTag & x"10" & QCountTag & x"01", -- I/O 48
|
||||
IOPortTag & x"10" & QCountTag & x"02", -- I/O 49
|
||||
IOPortTag & x"10" & QCountTag & x"03", -- I/O 50
|
||||
IOPortTag & x"11" & QCountTag & x"01", -- I/O 51
|
||||
IOPortTag & x"11" & QCountTag & x"02", -- I/O 52
|
||||
IOPortTag & x"11" & QCountTag & x"03", -- I/O 53
|
||||
IOPortTag & x"12" & QCountTag & x"01", -- I/O 54
|
||||
IOPortTag & x"12" & QCountTag & x"02", -- I/O 55
|
||||
IOPortTag & x"12" & QCountTag & x"03", -- I/O 56
|
||||
IOPortTag & x"13" & QCountTag & x"01", -- I/O 57
|
||||
IOPortTag & x"13" & QCountTag & x"02", -- I/O 58
|
||||
IOPortTag & x"13" & QCountTag & x"03", -- I/O 59
|
||||
IOPortTag & x"14" & QCountTag & x"01", -- I/O 60
|
||||
IOPortTag & x"14" & QCountTag & x"02", -- I/O 61
|
||||
IOPortTag & x"14" & QCountTag & x"03", -- I/O 62
|
||||
IOPortTag & x"15" & QCountTag & x"01", -- I/O 63
|
||||
IOPortTag & x"15" & QCountTag & x"02", -- I/O 64
|
||||
IOPortTag & x"15" & QCountTag & x"03", -- I/O 65
|
||||
IOPortTag & x"16" & QCountTag & x"01", -- I/O 66
|
||||
IOPortTag & x"16" & QCountTag & x"02", -- I/O 67
|
||||
IOPortTag & x"16" & QCountTag & x"03", -- I/O 68
|
||||
IOPortTag & x"17" & QCountTag & x"01", -- I/O 69
|
||||
IOPortTag & x"17" & QCountTag & x"02", -- I/O 70
|
||||
IOPortTag & x"17" & QCountTag & x"03", -- I/O 71
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_24XQCTRONLY_72;
|
||||
197
5i24/configs/hostmot2/source/PIN_2X7I65_72.vhd
Executable file
197
5i24/configs/hostmot2/source/PIN_2X7I65_72.vhd
Executable file
@@ -0,0 +1,197 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_2X7I65_72 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(MuxedQcountTag, MQCRev, ClockLowTag, x"10", MuxedQcounterAddr&PadT, MuxedQCounterNumRegs, x"00", MuxedQCounterMPBitMask),
|
||||
(MuxedQCountSelTag, x"00", ClockLowTag, x"01", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(BSPITag, x"00", ClockLowTag, x"02", BSPIDataAddr&PadT, BSPINumRegs, x"11", BSPIMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 00
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 01
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 02
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 03
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 04
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 05
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 06
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 07
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 08
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 09
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 10
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 11
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 12
|
||||
IOPortTag & x"00" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 37
|
||||
IOPortTag & x"00" & BSPITag & BSPIFramePin, -- I/O 14
|
||||
IOPortTag & x"00" & BSPITag & BSPIOutPin, -- I/O 15
|
||||
IOPortTag & x"00" & BSPITag & BSPIClkPin, -- I/O 16
|
||||
IOPortTag & x"00" & BSPITag & BSPIInPin, -- I/O 17
|
||||
IOPortTag & x"00" & BSPITag & BSPICS2Pin, -- I/O 18
|
||||
IOPortTag & x"00" & BSPITag & BSPICS1Pin, -- I/O 19
|
||||
IOPortTag & x"00" & BSPITag & BSPICS0Pin, -- I/O 20
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 21
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 22
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 23
|
||||
|
||||
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 24
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 25
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 26
|
||||
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 27
|
||||
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 28
|
||||
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 29
|
||||
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 30
|
||||
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 31
|
||||
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 32
|
||||
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 33
|
||||
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 34
|
||||
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 35
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 36
|
||||
IOPortTag & x"08" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 37
|
||||
IOPortTag & x"01" & BSPITag & BSPIFramePin, -- I/O 38
|
||||
IOPortTag & x"01" & BSPITag & BSPIOutPin, -- I/O 39
|
||||
IOPortTag & x"01" & BSPITag & BSPIClkPin, -- I/O 40
|
||||
IOPortTag & x"01" & BSPITag & BSPIInPin, -- I/O 41
|
||||
IOPortTag & x"01" & BSPITag & BSPICS2Pin, -- I/O 42
|
||||
IOPortTag & x"01" & BSPITag & BSPICS1Pin, -- I/O 43
|
||||
IOPortTag & x"01" & BSPITag & BSPICS0Pin, -- I/O 44
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 45
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 46
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 47
|
||||
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 48
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 49
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 50
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 51
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 52
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 53
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 54
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 55
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 56
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 57
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 58
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 59
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 60
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 61
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 62
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 63
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 64
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 65
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 66
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 67
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 68
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 69
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 70
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 71
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_2X7I65_72;
|
||||
197
5i24/configs/hostmot2/source/PIN_2X7I65_7I44_72.vhd
Executable file
197
5i24/configs/hostmot2/source/PIN_2X7I65_7I44_72.vhd
Executable file
@@ -0,0 +1,197 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_2X7I65_7I44_72 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(MuxedQcountTag, MQCRev, ClockLowTag, x"10", MuxedQcounterAddr&PadT, MuxedQCounterNumRegs, x"00", MuxedQCounterMPBitMask),
|
||||
(MuxedQCountSelTag, x"00", ClockLowTag, x"01", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(BSPITag, x"00", ClockLowTag, x"02", BSPIDataAddr&PadT, BSPINumRegs, x"11", BSPIMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 00
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 01
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 02
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 03
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 04
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 05
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 06
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 07
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 08
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 09
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 10
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 11
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 12
|
||||
IOPortTag & x"00" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 37
|
||||
IOPortTag & x"00" & BSPITag & BSPIFramePin, -- I/O 14
|
||||
IOPortTag & x"00" & BSPITag & BSPIOutPin, -- I/O 15
|
||||
IOPortTag & x"00" & BSPITag & BSPIClkPin, -- I/O 16
|
||||
IOPortTag & x"00" & BSPITag & BSPIInPin, -- I/O 17
|
||||
IOPortTag & x"00" & BSPITag & BSPICS2Pin, -- I/O 18
|
||||
IOPortTag & x"00" & BSPITag & BSPICS1Pin, -- I/O 19
|
||||
IOPortTag & x"00" & BSPITag & BSPICS0Pin, -- I/O 20
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 21
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 22
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 23
|
||||
|
||||
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 24
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 25
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 26
|
||||
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 27
|
||||
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 28
|
||||
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 29
|
||||
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 30
|
||||
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 31
|
||||
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 32
|
||||
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 33
|
||||
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 34
|
||||
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 35
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 36
|
||||
IOPortTag & x"08" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 37
|
||||
IOPortTag & x"01" & BSPITag & BSPIFramePin, -- I/O 38
|
||||
IOPortTag & x"01" & BSPITag & BSPIOutPin, -- I/O 39
|
||||
IOPortTag & x"01" & BSPITag & BSPIClkPin, -- I/O 40
|
||||
IOPortTag & x"01" & BSPITag & BSPIInPin, -- I/O 41
|
||||
IOPortTag & x"01" & BSPITag & BSPICS2Pin, -- I/O 42
|
||||
IOPortTag & x"01" & BSPITag & BSPICS1Pin, -- I/O 43
|
||||
IOPortTag & x"01" & BSPITag & BSPICS0Pin, -- I/O 44
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 45
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 46
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 47
|
||||
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 48
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 49
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, -- I/O 50
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX3Pin, -- I/O 51
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 52
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn0Pin, -- I/O 53
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 54
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn1Pin, -- I/O 55
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, -- I/O 56
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn2Pin, -- I/O 57
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX3Pin, -- I/O 58
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn3Pin, -- I/O 59
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX4Pin, -- I/O 60
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX5Pin, -- I/O 61
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX6Pin, -- I/O 62
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX7Pin, -- I/O 63
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX4Pin, -- I/O 64
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn4Pin, -- I/O 65
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX5Pin, -- I/O 66
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn5Pin, -- I/O 67
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX6Pin, -- I/O 68
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn6Pin, -- I/O 69
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX7Pin, -- I/O 70
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn7Pin, -- I/O 71
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_2X7I65_7I44_72;
|
||||
197
5i24/configs/hostmot2/source/PIN_2X7I65_SS8_72.vhd
Executable file
197
5i24/configs/hostmot2/source/PIN_2X7I65_SS8_72.vhd
Executable file
@@ -0,0 +1,197 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_2X7I65_SS8_72 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(MuxedQcountTag, MQCRev, ClockLowTag, x"10", MuxedQcounterAddr&PadT, MuxedQCounterNumRegs, x"00", MuxedQCounterMPBitMask),
|
||||
(MuxedQCountSelTag, x"00", ClockLowTag, x"01", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(BSPITag, x"00", ClockLowTag, x"02", BSPIDataAddr&PadT, BSPINumRegs, x"11", BSPIMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 00
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 01
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 02
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 03
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 04
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 05
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 06
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 07
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 08
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 09
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 10
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 11
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 12
|
||||
IOPortTag & x"00" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 37
|
||||
IOPortTag & x"00" & BSPITag & BSPIFramePin, -- I/O 14
|
||||
IOPortTag & x"00" & BSPITag & BSPIOutPin, -- I/O 15
|
||||
IOPortTag & x"00" & BSPITag & BSPIClkPin, -- I/O 16
|
||||
IOPortTag & x"00" & BSPITag & BSPIInPin, -- I/O 17
|
||||
IOPortTag & x"00" & BSPITag & BSPICS2Pin, -- I/O 18
|
||||
IOPortTag & x"00" & BSPITag & BSPICS1Pin, -- I/O 19
|
||||
IOPortTag & x"00" & BSPITag & BSPICS0Pin, -- I/O 20
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 21
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 22
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 23
|
||||
|
||||
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 24
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 25
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 26
|
||||
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 27
|
||||
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 28
|
||||
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 29
|
||||
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 30
|
||||
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 31
|
||||
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 32
|
||||
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 33
|
||||
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 34
|
||||
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 35
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 36
|
||||
IOPortTag & x"08" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 37
|
||||
IOPortTag & x"01" & BSPITag & BSPIFramePin, -- I/O 38
|
||||
IOPortTag & x"01" & BSPITag & BSPIOutPin, -- I/O 39
|
||||
IOPortTag & x"01" & BSPITag & BSPIClkPin, -- I/O 40
|
||||
IOPortTag & x"01" & BSPITag & BSPIInPin, -- I/O 41
|
||||
IOPortTag & x"01" & BSPITag & BSPICS2Pin, -- I/O 42
|
||||
IOPortTag & x"01" & BSPITag & BSPICS1Pin, -- I/O 43
|
||||
IOPortTag & x"01" & BSPITag & BSPICS0Pin, -- I/O 44
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 45
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 46
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 47
|
||||
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 48
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 49
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, -- I/O 50
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX3Pin, -- I/O 51
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 52
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn0Pin, -- I/O 53
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 54
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn1Pin, -- I/O 55
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, -- I/O 56
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn2Pin, -- I/O 57
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX3Pin, -- I/O 58
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn3Pin, -- I/O 59
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX4Pin, -- I/O 60
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX5Pin, -- I/O 61
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX6Pin, -- I/O 62
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX7Pin, -- I/O 63
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX4Pin, -- I/O 64
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn4Pin, -- I/O 65
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX5Pin, -- I/O 66
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn5Pin, -- I/O 67
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX6Pin, -- I/O 68
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn6Pin, -- I/O 69
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX7Pin, -- I/O 70
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn7Pin, -- I/O 71
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_2X7I65_SS8_72;
|
||||
219
5i24/configs/hostmot2/source/PIN_3x7I65_1x7I44_96.vhd
Executable file
219
5i24/configs/hostmot2/source/PIN_3x7I65_1x7I44_96.vhd
Executable file
@@ -0,0 +1,219 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_3x7I65_1x7I44_96 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"04", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(MuxedQcountTag, MQCRev, ClockLowTag, x"18", MuxedQcounterAddr&PadT, MuxedQCounterNumRegs, x"00", MuxedQCounterMPBitMask),
|
||||
(MuxedQCountSelTag, x"00", ClockLowTag, x"01", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(BSPITag, x"00", ClockLowTag, x"03", BSPIDataAddr&PadT, BSPINumRegs, x"11", BSPIMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 00
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 01
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 02
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 03
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 04
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 05
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 06
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 07
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 08
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 09
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 10
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 11
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 12
|
||||
IOPortTag & x"00" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 37
|
||||
IOPortTag & x"00" & BSPITag & BSPIFramePin, -- I/O 14
|
||||
IOPortTag & x"00" & BSPITag & BSPIOutPin, -- I/O 15
|
||||
IOPortTag & x"00" & BSPITag & BSPIClkPin, -- I/O 16
|
||||
IOPortTag & x"00" & BSPITag & BSPIInPin, -- I/O 17
|
||||
IOPortTag & x"00" & BSPITag & BSPICS2Pin, -- I/O 18
|
||||
IOPortTag & x"00" & BSPITag & BSPICS1Pin, -- I/O 19
|
||||
IOPortTag & x"00" & BSPITag & BSPICS0Pin, -- I/O 20
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 21
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 22
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 23
|
||||
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 24
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 25
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 26
|
||||
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 27
|
||||
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 28
|
||||
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 29
|
||||
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 30
|
||||
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 31
|
||||
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 32
|
||||
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 33
|
||||
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 34
|
||||
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 35
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 36
|
||||
IOPortTag & x"08" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 37
|
||||
IOPortTag & x"01" & BSPITag & BSPIFramePin, -- I/O 38
|
||||
IOPortTag & x"01" & BSPITag & BSPIOutPin, -- I/O 39
|
||||
IOPortTag & x"01" & BSPITag & BSPIClkPin, -- I/O 40
|
||||
IOPortTag & x"01" & BSPITag & BSPIInPin, -- I/O 41
|
||||
IOPortTag & x"01" & BSPITag & BSPICS2Pin, -- I/O 42
|
||||
IOPortTag & x"01" & BSPITag & BSPICS1Pin, -- I/O 43
|
||||
IOPortTag & x"01" & BSPITag & BSPICS0Pin, -- I/O 44
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 45
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 46
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 47
|
||||
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 48
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 49
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 50
|
||||
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 51
|
||||
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 52
|
||||
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 53
|
||||
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 54
|
||||
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 55
|
||||
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 56
|
||||
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 57
|
||||
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 58
|
||||
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 59
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 60
|
||||
IOPortTag & x"10" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 61
|
||||
IOPortTag & x"02" & BSPITag & BSPIFramePin, -- I/O 62
|
||||
IOPortTag & x"02" & BSPITag & BSPIOutPin, -- I/O 63
|
||||
IOPortTag & x"02" & BSPITag & BSPIClkPin, -- I/O 64
|
||||
IOPortTag & x"02" & BSPITag & BSPIInPin, -- I/O 65
|
||||
IOPortTag & x"02" & BSPITag & BSPICS2Pin, -- I/O 66
|
||||
IOPortTag & x"02" & BSPITag & BSPICS1Pin, -- I/O 67
|
||||
IOPortTag & x"02" & BSPITag & BSPICS0Pin, -- I/O 68
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 69
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 70
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 71
|
||||
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 72
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 73
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, -- I/O 74
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX3Pin, -- I/O 75
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 76
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn0Pin, -- I/O 77
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 78
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn1Pin, -- I/O 79
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, -- I/O 80
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn2Pin, -- I/O 81
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX3Pin, -- I/O 82
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn3Pin, -- I/O 83
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX4Pin, -- I/O 84
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX5Pin, -- I/O 85
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX6Pin, -- I/O 86
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX7Pin, -- I/O 87
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX4Pin, -- I/O 88
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn4Pin, -- I/O 89
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX5Pin, -- I/O 90
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn5Pin, -- I/O 91
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX6Pin, -- I/O 92
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn6Pin, -- I/O 93
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX7Pin, -- I/O 94
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn7Pin, -- I/O 95
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_3x7I65_1x7I44_96;
|
||||
219
5i24/configs/hostmot2/source/PIN_4x7I65_96.vhd
Executable file
219
5i24/configs/hostmot2/source/PIN_4x7I65_96.vhd
Executable file
@@ -0,0 +1,219 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_4x7I65_96 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"04", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(MuxedQcountTag, MQCRev, ClockLowTag, x"20", MuxedQcounterAddr&PadT, MuxedQCounterNumRegs, x"00", MuxedQCounterMPBitMask),
|
||||
(MuxedQCountSelTag, x"00", ClockLowTag, x"01", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(BSPITag, x"00", ClockLowTag, x"04", BSPIDataAddr&PadT, BSPINumRegs, x"11", BSPIMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 00
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 01
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 02
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 03
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 04
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 05
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 06
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 07
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 08
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 09
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 10
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 11
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 12
|
||||
IOPortTag & x"00" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 37
|
||||
IOPortTag & x"00" & BSPITag & BSPIFramePin, -- I/O 14
|
||||
IOPortTag & x"00" & BSPITag & BSPIOutPin, -- I/O 15
|
||||
IOPortTag & x"00" & BSPITag & BSPIClkPin, -- I/O 16
|
||||
IOPortTag & x"00" & BSPITag & BSPIInPin, -- I/O 17
|
||||
IOPortTag & x"00" & BSPITag & BSPICS2Pin, -- I/O 18
|
||||
IOPortTag & x"00" & BSPITag & BSPICS1Pin, -- I/O 19
|
||||
IOPortTag & x"00" & BSPITag & BSPICS0Pin, -- I/O 20
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 21
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 22
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 23
|
||||
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 24
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 25
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 26
|
||||
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 27
|
||||
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 28
|
||||
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 29
|
||||
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 30
|
||||
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 31
|
||||
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 32
|
||||
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 33
|
||||
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 34
|
||||
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 35
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 36
|
||||
IOPortTag & x"08" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 37
|
||||
IOPortTag & x"01" & BSPITag & BSPIFramePin, -- I/O 38
|
||||
IOPortTag & x"01" & BSPITag & BSPIOutPin, -- I/O 39
|
||||
IOPortTag & x"01" & BSPITag & BSPIClkPin, -- I/O 40
|
||||
IOPortTag & x"01" & BSPITag & BSPIInPin, -- I/O 41
|
||||
IOPortTag & x"01" & BSPITag & BSPICS2Pin, -- I/O 42
|
||||
IOPortTag & x"01" & BSPITag & BSPICS1Pin, -- I/O 43
|
||||
IOPortTag & x"01" & BSPITag & BSPICS0Pin, -- I/O 44
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 45
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 46
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 47
|
||||
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 48
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 49
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 50
|
||||
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 51
|
||||
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 52
|
||||
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 53
|
||||
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 54
|
||||
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 55
|
||||
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 56
|
||||
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 57
|
||||
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 58
|
||||
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 59
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 60
|
||||
IOPortTag & x"10" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 61
|
||||
IOPortTag & x"02" & BSPITag & BSPIFramePin, -- I/O 62
|
||||
IOPortTag & x"02" & BSPITag & BSPIOutPin, -- I/O 63
|
||||
IOPortTag & x"02" & BSPITag & BSPIClkPin, -- I/O 64
|
||||
IOPortTag & x"02" & BSPITag & BSPIInPin, -- I/O 65
|
||||
IOPortTag & x"02" & BSPITag & BSPICS2Pin, -- I/O 66
|
||||
IOPortTag & x"02" & BSPITag & BSPICS1Pin, -- I/O 67
|
||||
IOPortTag & x"02" & BSPITag & BSPICS0Pin, -- I/O 68
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 69
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 70
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 71
|
||||
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 72
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 73
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 74
|
||||
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 75
|
||||
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 76
|
||||
IOPortTag & x"05" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 77
|
||||
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 78
|
||||
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 79
|
||||
IOPortTag & x"06" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 80
|
||||
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 81
|
||||
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 82
|
||||
IOPortTag & x"07" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 83
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 84
|
||||
IOPortTag & x"18" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 85
|
||||
IOPortTag & x"03" & BSPITag & BSPIFramePin, -- I/O 86
|
||||
IOPortTag & x"03" & BSPITag & BSPIOutPin, -- I/O 87
|
||||
IOPortTag & x"03" & BSPITag & BSPIClkPin, -- I/O 88
|
||||
IOPortTag & x"03" & BSPITag & BSPIInPin, -- I/O 89
|
||||
IOPortTag & x"03" & BSPITag & BSPICS2Pin, -- I/O 90
|
||||
IOPortTag & x"03" & BSPITag & BSPICS1Pin, -- I/O 91
|
||||
IOPortTag & x"03" & BSPITag & BSPICS0Pin, -- I/O 92
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 93
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 94
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 95
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_4x7I65_96;
|
||||
167
5i24/configs/hostmot2/source/PIN_5ABOB_EncD_34.vhd
Executable file
167
5i24/configs/hostmot2/source/PIN_5ABOB_EncD_34.vhd
Executable file
@@ -0,0 +1,167 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_5ABOB_EncD_34 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"06", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"05", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(PWMTag, x"00", ClockHighTag, x"01", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin -- external DB25 or IDC26
|
||||
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 00 PIN 1 Spindle DAC PWM
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 01 PIN 14 just GPIO
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 02 PIN 2 X Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 03 PIN 15 just GPIO
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 04 PIN 3 X Dir
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 05 PIN 16 B Step
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 06 PIN 4 Y Step
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 07 PIN 17 B Dir
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 08 PIN 5 Y Dir
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 09 PIN 6 Z Step
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 10 PIN 7 Z Dir
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 11 PIN 8 A Step
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 12 PIN 9 A Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 13 PIN 10 Input 1 just GPIO
|
||||
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 14 PIN 11 Input 2 (Quad A)
|
||||
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 15 PIN 12 Input 3 (Quad B)
|
||||
IOPortTag & x"00" & QCountTag & QCountIdxPin, -- I/O 16 PIN 13 Input 4 (Quad Idx)
|
||||
|
||||
-- 26 HDR -- IDC DB25
|
||||
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 17 PIN 1 PIN 1
|
||||
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 18 PIN 2 PIN 14
|
||||
IOPortTag & x"01" & QCountTag & QCountIdxPin, -- I/O 19 PIN 3 PIN 2
|
||||
IOPortTag & x"02" & QCountTag & QCountQAPin, -- I/O 20 PIN 4 PIN 15
|
||||
IOPortTag & x"02" & QCountTag & QCountQBPin, -- I/O 21 PIN 5 PIN 3
|
||||
IOPortTag & x"02" & QCountTag & QCountIdxPin, -- I/O 22 PIN 6 PIN 16
|
||||
IOPortTag & x"03" & QCountTag & QCountQAPin, -- I/O 23 PIN 7 PIN 4
|
||||
IOPortTag & x"03" & QCountTag & QCountQBPin, -- I/O 24 PIN 8 PIN 17
|
||||
IOPortTag & x"03" & QCountTag & QCountIdxPin, -- I/O 25 PIN 9 PIN 5
|
||||
IOPortTag & x"04" & QCountTag & QCountQAPin, -- I/O 26 PIN 11 PIN 6
|
||||
IOPortTag & x"04" & QCountTag & QCountQBPin, -- I/O 27 PIN 13 PIN 7
|
||||
IOPortTag & x"04" & QCountTag & QCountIdxPin, -- I/O 28 PIN 15 PIN 8
|
||||
IOPortTag & x"05" & QCountTag & QCountQAPin, -- I/O 29 PIN 17 PIN 9
|
||||
IOPortTag & x"05" & QCountTag & QCountQBPin, -- I/O 30 PIN 19 PIN 10
|
||||
IOPortTag & x"05" & QCountTag & QCountIdxPin, -- I/O 31 PIN 21 PIN 11
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 32 PIN 23 PIN 12
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 33 PIN 25 PIN 13
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_5ABOB_EncD_34;
|
||||
167
5i24/configs/hostmot2/source/PIN_5ABOB_XYDPD_34.vhd
Executable file
167
5i24/configs/hostmot2/source/PIN_5ABOB_XYDPD_34.vhd
Executable file
@@ -0,0 +1,167 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_5ABOB_XYDPD_34 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(DPainterTag, x"00", ClockLowTag, x"01", DPainterRateAddr&PadT, DPainterNumRegs, x"00", DPainterMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"01", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"05", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(PWMTag, x"00", ClockHighTag, x"01", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
|
||||
(XY2ModTag, x"00", ClockLowTag, x"01", XY2ModAccelXAddr&PadT, XY2ModNumRegs, x"00", XY2ModMPBitMask ),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin -- external DB25
|
||||
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 00 PIN 1 Spindle DAC PWM
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 01 PIN 14 just GPIO
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 02 PIN 2 X Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 03 PIN 15 just GPIO
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 04 PIN 3 X Dir
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 05 PIN 16 B Step
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 06 PIN 4 Y Step
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 07 PIN 17 B Dir
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 08 PIN 5 Y Dir
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 09 PIN 6 Z Step
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 10 PIN 7 Z Dir
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 11 PIN 8 A Step
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 12 PIN 9 A Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 13 PIN 10 Input 1 just GPIO
|
||||
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 14 PIN 11 Input 2 (Quad A)
|
||||
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 15 PIN 12 Input 3 (Quad B)
|
||||
IOPortTag & x"00" & QCountTag & QCountIdxPin, -- I/O 16 PIN 13 Input 4 (Quad Idx)
|
||||
|
||||
-- 26 HDR -- IDC DB25
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 17 PIN 1 PIN 1 just GPIO
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 18 PIN 2 PIN 14 just GPIO
|
||||
IOPortTag & x"00" & XY2ModTag & XY2ModDataXPin, -- I/O 19 PIN 3 PIN 2 XY100 X Data
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 20 PIN 4 PIN 15 just GPIO
|
||||
IOPortTag & x"00" & XY2ModTag & XY2ModDataYPin, -- I/O 21 PIN 5 PIN 3 XY 100Y Data
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 22 PIN 6 PIN 16 just GPIO
|
||||
IOPortTag & x"00" & XY2ModTag & XY2ModDataClkPin, -- I/O 23 PIN 7 PIN 4 XY100 Clk
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 24 PIN 8 PIN 17 just GPIO
|
||||
IOPortTag & x"00" & XY2ModTag & XY2ModSyncPin, -- I/O 25 PIN 9 PIN 5 XY100 Sync
|
||||
IOPortTag & x"00" & DPainterTag & DPainterDataPin, -- I/O 26 PIN 11 PIN 6 DPainter Data
|
||||
IOPortTag & x"00" & DPainterTag & DPainterClkPin, -- I/O 27 PIN 13 PIN 7 Dpainter clk
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 28 PIN 15 PIN 8 just GPIO
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 29 PIN 17 PIN 9 just GPIO
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 30 PIN 19 PIN 10 XY100 Status
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 31 PIN 21 PIN 11 just GPIO
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 32 PIN 23 PIN 12 just GPIO
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 33 PIN 25 PIN 13 just GPIO
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_5ABOB_XYDPD_34;
|
||||
167
5i24/configs/hostmot2/source/PIN_5ABOBx2D_34.vhd
Executable file
167
5i24/configs/hostmot2/source/PIN_5ABOBx2D_34.vhd
Executable file
@@ -0,0 +1,167 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_5ABOBx2D_34 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"02", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"0A", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(PWMTag, x"00", ClockHighTag, x"02", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin -- external DB25
|
||||
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 00 PIN 1 Spindle DAC PWM
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 01 PIN 14 just GPIO
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 02 PIN 2 X Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 03 PIN 15 just GPIO
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 04 PIN 3 X Dir
|
||||
IOPortTag & x"08" & StepGenTag & StepGenStepPin, -- I/O 05 PIN 16 B Step
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 06 PIN 4 Y Step
|
||||
IOPortTag & x"08" & StepGenTag & StepGenDirPin, -- I/O 07 PIN 17 B Dir
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 08 PIN 5 Y Dir
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 09 PIN 6 Z Step
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 10 PIN 7 Z Dir
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 11 PIN 8 A Step
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 12 PIN 9 A Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 13 PIN 10 Input 1 just GPIO
|
||||
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 14 PIN 11 Input 2 (Quad A)
|
||||
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 15 PIN 12 Input 3 (Quad B)
|
||||
IOPortTag & x"00" & QCountTag & QCountIdxPin, -- I/O 16 PIN 13 Input 4 (Quad Idx)
|
||||
|
||||
-- 26 HDR -- IDC DB25
|
||||
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 17 PIN 1 PIN 1 Spindle DAC PWM
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 18 PIN 2 PIN 14 just GPIO
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 19 PIN 3 PIN 2 X2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 20 PIN 4 PIN 15 just GPIO
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 21 PIN 5 PIN 3 X2 Step
|
||||
IOPortTag & x"09" & StepGenTag & StepGenStepPin, -- I/O 22 PIN 6 PIN 16 just GPIO
|
||||
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 23 PIN 7 PIN 4 Y2 Dir
|
||||
IOPortTag & x"09" & StepGenTag & StepGenDirPin, -- I/O 24 PIN 8 PIN 17 just GPIO
|
||||
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 25 PIN 9 PIN 5 Y2 Step
|
||||
IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 26 PIN 11 PIN 6 Z2 Dir
|
||||
IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 27 PIN 13 PIN 7 Z2 Step
|
||||
IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 28 PIN 15 PIN 8 A2 Dir
|
||||
IOPortTag & x"07" & StepGenTag & StepGenDIrPin, -- I/O 29 PIN 17 PIN 9 A2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 30 PIN 19 PIN 10 just GPIO
|
||||
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 31 PIN 21 PIN 11 Input 2 (Quad A)
|
||||
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 32 PIN 23 PIN 12 Input 3 (Quad B))
|
||||
IOPortTag & x"01" & QCountTag & QCountIdxPin, -- I/O 33 PIN 25 PIN 13 Input 4 (Quad Idx)
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_5ABOBx2D_34;
|
||||
191
5i24/configs/hostmot2/source/PIN_5ABOBx2D_56.vhd
Executable file
191
5i24/configs/hostmot2/source/PIN_5ABOBx2D_56.vhd
Executable file
@@ -0,0 +1,191 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_5ABOBx2D_56 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"02", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"08", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(PWMTag, x"00", ClockHighTag, x"03", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin -- external DB25
|
||||
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 00 PIN 1 Spindle DAC PWM
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 01 PIN 14 just GPIO
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 02 PIN 2 X Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 03 PIN 15 just GPIO
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 04 PIN 3 X Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 05 PIN 16 B Step
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 06 PIN 4 Y Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 07 PIN 17 B Dir
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 08 PIN 5 Y Dir
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 09 PIN 6 Z Step
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 10 PIN 7 Z Dir
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 11 PIN 8 A Step
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 12 PIN 9 A Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 13 PIN 10 Input 1 just GPIO
|
||||
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 14 PIN 11 Input 2 (Quad A)
|
||||
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 15 PIN 12 Input 3 (Quad B)
|
||||
IOPortTag & x"00" & QCountTag & QCountIdxPin, -- I/O 16 PIN 13 Input 4 (Quad Idx)
|
||||
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 17
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 18
|
||||
|
||||
-- 26 HDR -- IDC DB25
|
||||
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 19 PIN 1 PIN 1 Spindle DAC PWM
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 20 PIN 2 PIN 14 just GPIO
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 21 PIN 3 PIN 2 X2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 22 PIN 4 PIN 15 just GPIO
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 23 PIN 5 PIN 3 X2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 24 PIN 6 PIN 16 just GPIO
|
||||
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 25 PIN 7 PIN 4 Y2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 26 PIN 8 PIN 17 just GPIO
|
||||
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 27 PIN 9 PIN 5 Y2 Step
|
||||
IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 28 PIN 11 PIN 6 Z2 Dir
|
||||
IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 29 PIN 13 PIN 7 Z2 Step
|
||||
IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 30 PIN 15 PIN 8 A2 Dir
|
||||
IOPortTag & x"07" & StepGenTag & StepGenDIrPin, -- I/O 31 PIN 17 PIN 9 A2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 32 PIN 19 PIN 10 just GPIO
|
||||
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 33 PIN 21 PIN 11 Input 2 (Quad A)
|
||||
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 34 PIN 23 PIN 12 Input 3 (Quad B))
|
||||
IOPortTag & x"01" & QCountTag & QCountIdxPin, -- I/O 35 PIN 25 PIN 13 Input 4 (Quad Idx)
|
||||
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEN0Pin, -- I/O 36
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEN1Pin, -- I/O 37
|
||||
|
||||
-- 26 HDR -- IDC DB25
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 34 PIN 1
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 35 PIN 14
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 36 PIN 2
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 37 PIN 15
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 38 PIN 3
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 39 PIN 16
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 40 PIN 4
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 41 PIN 17
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 42 PIN 5
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 43 PIN 6
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 44 PIN 7
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 45 PIN 8
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 46 PIN 9
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 47 PIN 10
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 48 PIN 11
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 49 PIN 12
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 50 PIN 13
|
||||
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 55
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 56
|
||||
|
||||
|
||||
-- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_5ABOBx2D_56;
|
||||
191
5i24/configs/hostmot2/source/PIN_5ABOBx2D_57.vhd
Executable file
191
5i24/configs/hostmot2/source/PIN_5ABOBx2D_57.vhd
Executable file
@@ -0,0 +1,191 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_5ABOBx2D_57 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"02", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"08", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(PWMTag, x"00", ClockHighTag, x"02", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin -- external DB25
|
||||
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 00 PIN 1 Spindle DAC PWM
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 01 PIN 14 just GPIO
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 02 PIN 2 X Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 03 PIN 15 just GPIO
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 04 PIN 3 X Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 05 PIN 16 B Step
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 06 PIN 4 Y Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 07 PIN 17 B Dir
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 08 PIN 5 Y Dir
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 09 PIN 6 Z Step
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 10 PIN 7 Z Dir
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 11 PIN 8 A Step
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 12 PIN 9 A Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 13 PIN 10 Input 1 just GPIO
|
||||
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 14 PIN 11 Input 2 (Quad A)
|
||||
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 15 PIN 12 Input 3 (Quad B)
|
||||
IOPortTag & x"00" & QCountTag & QCountIdxPin, -- I/O 16 PIN 13 Input 4 (Quad Idx)
|
||||
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 17
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 18
|
||||
|
||||
-- 26 HDR -- IDC DB25
|
||||
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 19 PIN 1 PIN 1 Spindle DAC PWM
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 20 PIN 2 PIN 14 just GPIO
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 21 PIN 3 PIN 2 X2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 22 PIN 4 PIN 15 just GPIO
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 23 PIN 5 PIN 3 X2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 24 PIN 6 PIN 16 just GPIO
|
||||
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 25 PIN 7 PIN 4 Y2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 26 PIN 8 PIN 17 just GPIO
|
||||
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 27 PIN 9 PIN 5 Y2 Step
|
||||
IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 28 PIN 11 PIN 6 Z2 Dir
|
||||
IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 29 PIN 13 PIN 7 Z2 Step
|
||||
IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 30 PIN 15 PIN 8 A2 Dir
|
||||
IOPortTag & x"07" & StepGenTag & StepGenDIrPin, -- I/O 31 PIN 17 PIN 9 A2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 32 PIN 19 PIN 10 just GPIO
|
||||
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 33 PIN 21 PIN 11 Input 2 (Quad A)
|
||||
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 34 PIN 23 PIN 12 Input 3 (Quad B))
|
||||
IOPortTag & x"01" & QCountTag & QCountIdxPin, -- I/O 35 PIN 25 PIN 13 Input 4 (Quad Idx)
|
||||
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEN0Pin, -- I/O 36
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEN1Pin, -- I/O 37
|
||||
|
||||
-- 26 HDR -- IDC DB25
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 38 PIN 1
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 39 PIN 14
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 40 PIN 2
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 41 PIN 15
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 42 PIN 3
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 43 PIN 16
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 44 PIN 4
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 45 PIN 17
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 46 PIN 5
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 47 PIN 6
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 48 PIN 7
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 49 PIN 8
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 50 PIN 9
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 51 PIN 10
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 52 PIN 11
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 53 PIN 12
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 54 PIN 13
|
||||
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 55
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 56
|
||||
|
||||
|
||||
-- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_5ABOBx2D_57;
|
||||
167
5i24/configs/hostmot2/source/PIN_5ABOBx2_34.vhd
Executable file
167
5i24/configs/hostmot2/source/PIN_5ABOBx2_34.vhd
Executable file
@@ -0,0 +1,167 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_5ABOBx2_34 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"02", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"0A", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(PWMTag, x"00", ClockHighTag, x"02", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin -- external DB25
|
||||
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 00 PIN 1 Spindle DAC PWM
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 01 PIN 14 just GPIO
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 02 PIN 2 X Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 03 PIN 15 just GPIO
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 04 PIN 3 X Dir
|
||||
IOPortTag & x"08" & StepGenTag & StepGenStepPin, -- I/O 05 PIN 16 B Step
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 06 PIN 4 Y Step
|
||||
IOPortTag & x"08" & StepGenTag & StepGenDirPin, -- I/O 07 PIN 17 B Dir
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 08 PIN 5 Y Dir
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 09 PIN 6 Z Step
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 10 PIN 7 Z Dir
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 11 PIN 8 A Step
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 12 PIN 9 A Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 13 PIN 10 Input 1 just GPIO
|
||||
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 14 PIN 11 Input 2 (Quad A)
|
||||
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 15 PIN 12 Input 3 (Quad B)
|
||||
IOPortTag & x"00" & QCountTag & QCountIdxPin, -- I/O 16 PIN 13 Input 4 (Quad Idx)
|
||||
|
||||
-- 26 HDR -- IDC DB25
|
||||
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 17 PIN 1 PIN 1 Spindle DAC PWM
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 18 PIN 2 PIN 14 just GPIO
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 19 PIN 3 PIN 2 X2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 20 PIN 4 PIN 15 just GPIO
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 21 PIN 5 PIN 3 X2 Step
|
||||
IOPortTag & x"09" & StepGenTag & StepGenStepPin, -- I/O 22 PIN 6 PIN 16 just GPIO
|
||||
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 23 PIN 7 PIN 4 Y2 Dir
|
||||
IOPortTag & x"09" & StepGenTag & StepGenDirPin, -- I/O 24 PIN 8 PIN 17 just GPIO
|
||||
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 25 PIN 9 PIN 5 Y2 Step
|
||||
IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 26 PIN 11 PIN 6 Z2 Dir
|
||||
IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 27 PIN 13 PIN 7 Z2 Step
|
||||
IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 28 PIN 15 PIN 8 A2 Dir
|
||||
IOPortTag & x"07" & StepGenTag & StepGenDIrPin, -- I/O 29 PIN 17 PIN 9 A2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 30 PIN 19 PIN 10 just GPIO
|
||||
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 31 PIN 21 PIN 11 Input 2 (Quad A)
|
||||
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 32 PIN 23 PIN 12 Input 3 (Quad B))
|
||||
IOPortTag & x"01" & QCountTag & QCountIdxPin, -- I/O 33 PIN 25 PIN 13 Input 4 (Quad Idx)
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_5ABOBx2_34;
|
||||
191
5i24/configs/hostmot2/source/PIN_5ABOBx3DSS_57.vhd
Executable file
191
5i24/configs/hostmot2/source/PIN_5ABOBx3DSS_57.vhd
Executable file
@@ -0,0 +1,191 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_5ABOBx3DSS_57 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"01", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"0A", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(PWMTag, x"00", ClockHighTag, x"03", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin -- external DB25
|
||||
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 00 PIN 1 Spindle DAC PWM
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 01 PIN 14 just GPIO
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 02 PIN 2 X Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 03 PIN 15 just GPIO
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 04 PIN 3 X Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 05 PIN 16 B Step
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 06 PIN 4 Y Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 07 PIN 17 B Dir
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 08 PIN 5 Y Dir
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 09 PIN 6 Z Step
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 10 PIN 7 Z Dir
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 11 PIN 8 A Step
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 12 PIN 9 A Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 13 PIN 10 Input 1 just GPIO
|
||||
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 14 PIN 11 Input 2 (Quad A)
|
||||
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 15 PIN 12 Input 3 (Quad B)
|
||||
IOPortTag & x"00" & QCountTag & QCountIdxPin, -- I/O 16 PIN 13 Input 4 (Quad Idx)
|
||||
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 17
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 18
|
||||
|
||||
-- 26 HDR -- IDC DB25
|
||||
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 19 PIN 1 PIN 1 Spindle DAC PWM
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 20 PIN 2 PIN 14 just GPIO
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 21 PIN 3 PIN 2 X2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 22 PIN 4 PIN 15 just GPIO
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 23 PIN 5 PIN 3 X2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 24 PIN 6 PIN 16 just GPIO
|
||||
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 25 PIN 7 PIN 4 Y2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 26 PIN 8 PIN 17 just GPIO
|
||||
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 27 PIN 9 PIN 5 Y2 Step
|
||||
IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 28 PIN 11 PIN 6 Z2 Dir
|
||||
IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 29 PIN 13 PIN 7 Z2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 30 PIN 15 PIN 8 A2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 31 PIN 17 PIN 9 A2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 32 PIN 19 PIN 10 just GPIO
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 33 PIN 21 PIN 11 Input 2 (Quad A)
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 34 PIN 23 PIN 12 Input 3 (Quad B))
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 35 PIN 25 PIN 13 Input 4 (Quad Idx)
|
||||
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEN0Pin, -- I/O 36
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEN1Pin, -- I/O 37
|
||||
|
||||
-- 26 HDR -- IDC DB25
|
||||
IOPortTag & x"02" & PWMTag & PWMAOutPin, -- I/O 38 PIN 1 PIN 1 Spindle DAC PWM
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 39 PIN 2 PIN 14 just GPIO
|
||||
IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 40 PIN 3 PIN 2 X2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 41 PIN 4 PIN 15 just GPIO
|
||||
IOPortTag & x"07" & StepGenTag & StepGenDirPin, -- I/O 42 PIN 5 PIN 3 X2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 43 PIN 6 PIN 16 just GPIO
|
||||
IOPortTag & x"08" & StepGenTag & StepGenStepPin, -- I/O 44 PIN 7 PIN 4 Y2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 45 PIN 8 PIN 17 just GPIO
|
||||
IOPortTag & x"08" & StepGenTag & StepGenDirPin, -- I/O 46 PIN 9 PIN 5 Y2 Step
|
||||
IOPortTag & x"09" & StepGenTag & StepGenStepPin, -- I/O 47 PIN 11 PIN 6 Z2 Dir
|
||||
IOPortTag & x"09" & StepGenTag & StepGenDirPin, -- I/O 48 PIN 13 PIN 7 Z2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 49 PIN 15 PIN 8 A2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 50 PIN 17 PIN 9 A2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 51 PIN 19 PIN 10 just GPIO
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 52 PIN 21 PIN 11 Input 2 (Quad A)
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 53 PIN 23 PIN 12 Input 3 (Quad B))
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 54 PIN 25 PIN 13 Input 4 (Quad Idx)
|
||||
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 55
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 56
|
||||
|
||||
|
||||
-- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_5ABOBx3DSS_57;
|
||||
182
5i24/configs/hostmot2/source/PIN_5ABOBx3D_51.vhd
Executable file
182
5i24/configs/hostmot2/source/PIN_5ABOBx3D_51.vhd
Executable file
@@ -0,0 +1,182 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_5ABOBx3D_51 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"03", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"0C", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(PWMTag, x"00", ClockHighTag, x"03", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin -- external DB25
|
||||
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 00 PIN 1 Spindle DAC PWM
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 01 PIN 14 just GPIO
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 02 PIN 2 X Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 03 PIN 15 just GPIO
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 04 PIN 3 X Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 05 PIN 16 B Step
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 06 PIN 4 Y Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 07 PIN 17 B Dir
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 08 PIN 5 Y Dir
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 09 PIN 6 Z Step
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 10 PIN 7 Z Dir
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 11 PIN 8 A Step
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 12 PIN 9 A Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 13 PIN 10 Input 1 just GPIO
|
||||
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 14 PIN 11 Input 2 (Quad A)
|
||||
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 15 PIN 12 Input 3 (Quad B)
|
||||
IOPortTag & x"00" & QCountTag & QCountIdxPin, -- I/O 16 PIN 13 Input 4 (Quad Idx)
|
||||
|
||||
-- 26 HDR -- IDC DB25
|
||||
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 17 PIN 1 PIN 1 Spindle DAC PWM
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 18 PIN 2 PIN 14 just GPIO
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 19 PIN 3 PIN 2 X2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 20 PIN 4 PIN 15 just GPIO
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 21 PIN 5 PIN 3 X2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 22 PIN 6 PIN 16 just GPIO
|
||||
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 23 PIN 7 PIN 4 Y2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 24 PIN 8 PIN 17 just GPIO
|
||||
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 25 PIN 9 PIN 5 Y2 Step
|
||||
IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 26 PIN 11 PIN 6 Z2 Dir
|
||||
IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 27 PIN 13 PIN 7 Z2 Step
|
||||
IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 28 PIN 15 PIN 8 A2 Dir
|
||||
IOPortTag & x"07" & StepGenTag & StepGenDIrPin, -- I/O 29 PIN 17 PIN 9 A2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 30 PIN 19 PIN 10 just GPIO
|
||||
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 31 PIN 21 PIN 11 Input 2 (Quad A)
|
||||
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 32 PIN 23 PIN 12 Input 3 (Quad B))
|
||||
IOPortTag & x"01" & QCountTag & QCountIdxPin, -- I/O 33 PIN 25 PIN 13 Input 4 (Quad Idx)
|
||||
|
||||
-- 26 HDR -- IDC DB25
|
||||
IOPortTag & x"02" & PWMTag & PWMAOutPin, -- I/O 17 PIN 1 PIN 1 Spindle DAC PWM
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 18 PIN 2 PIN 14 just GPIO
|
||||
IOPortTag & x"08" & StepGenTag & StepGenStepPin, -- I/O 19 PIN 3 PIN 2 X2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 20 PIN 4 PIN 15 just GPIO
|
||||
IOPortTag & x"08" & StepGenTag & StepGenDirPin, -- I/O 21 PIN 5 PIN 3 X2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 22 PIN 6 PIN 16 just GPIO
|
||||
IOPortTag & x"09" & StepGenTag & StepGenStepPin, -- I/O 23 PIN 7 PIN 4 Y2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 24 PIN 8 PIN 17 just GPIO
|
||||
IOPortTag & x"09" & StepGenTag & StepGenDirPin, -- I/O 25 PIN 9 PIN 5 Y2 Step
|
||||
IOPortTag & x"0A" & StepGenTag & StepGenStepPin, -- I/O 26 PIN 11 PIN 6 Z2 Dir
|
||||
IOPortTag & x"0A" & StepGenTag & StepGenDirPin, -- I/O 27 PIN 13 PIN 7 Z2 Step
|
||||
IOPortTag & x"0B" & StepGenTag & StepGenStepPin, -- I/O 28 PIN 15 PIN 8 A2 Dir
|
||||
IOPortTag & x"0B" & StepGenTag & StepGenDIrPin, -- I/O 29 PIN 17 PIN 9 A2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 30 PIN 19 PIN 10 just GPIO
|
||||
IOPortTag & x"02" & QCountTag & QCountQAPin, -- I/O 31 PIN 21 PIN 11 Input 2 (Quad A)
|
||||
IOPortTag & x"02" & QCountTag & QCountQBPin, -- I/O 32 PIN 23 PIN 12 Input 3 (Quad B))
|
||||
IOPortTag & x"02" & QCountTag & QCountIdxPin, -- I/O 33 PIN 25 PIN 13 Input 4 (Quad Idx)
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_5ABOBx3D_51;
|
||||
191
5i24/configs/hostmot2/source/PIN_5ABOBx3D_56.vhd
Executable file
191
5i24/configs/hostmot2/source/PIN_5ABOBx3D_56.vhd
Executable file
@@ -0,0 +1,191 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_5ABOBx3D_56 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"03", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"0C", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(PWMTag, x"00", ClockHighTag, x"03", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin -- external DB25
|
||||
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 00 PIN 1 Spindle DAC PWM
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 01 PIN 14 just GPIO
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 02 PIN 2 X Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 03 PIN 15 just GPIO
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 04 PIN 3 X Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 05 PIN 16 B Step
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 06 PIN 4 Y Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 07 PIN 17 B Dir
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 08 PIN 5 Y Dir
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 09 PIN 6 Z Step
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 10 PIN 7 Z Dir
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 11 PIN 8 A Step
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 12 PIN 9 A Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 13 PIN 10 Input 1 just GPIO
|
||||
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 14 PIN 11 Input 2 (Quad A)
|
||||
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 15 PIN 12 Input 3 (Quad B)
|
||||
IOPortTag & x"00" & QCountTag & QCountIdxPin, -- I/O 16 PIN 13 Input 4 (Quad Idx)
|
||||
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 17
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 18
|
||||
|
||||
-- 26 HDR -- IDC DB25
|
||||
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 19 PIN 1 PIN 1 Spindle DAC PWM
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 20 PIN 2 PIN 14 just GPIO
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 21 PIN 3 PIN 2 X2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 22 PIN 4 PIN 15 just GPIO
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 23 PIN 5 PIN 3 X2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 24 PIN 6 PIN 16 just GPIO
|
||||
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 25 PIN 7 PIN 4 Y2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 26 PIN 8 PIN 17 just GPIO
|
||||
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 27 PIN 9 PIN 5 Y2 Step
|
||||
IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 28 PIN 11 PIN 6 Z2 Dir
|
||||
IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 29 PIN 13 PIN 7 Z2 Step
|
||||
IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 30 PIN 15 PIN 8 A2 Dir
|
||||
IOPortTag & x"07" & StepGenTag & StepGenDIrPin, -- I/O 31 PIN 17 PIN 9 A2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 32 PIN 19 PIN 10 just GPIO
|
||||
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 33 PIN 21 PIN 11 Input 2 (Quad A)
|
||||
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 34 PIN 23 PIN 12 Input 3 (Quad B))
|
||||
IOPortTag & x"01" & QCountTag & QCountIdxPin, -- I/O 35 PIN 25 PIN 13 Input 4 (Quad Idx)
|
||||
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEN0Pin, -- I/O 36
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEN1Pin, -- I/O 37
|
||||
|
||||
-- 26 HDR -- IDC DB25
|
||||
IOPortTag & x"02" & PWMTag & PWMAOutPin, -- I/O 38 PIN 1 PIN 1 Spindle DAC PWM
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 39 PIN 2 PIN 14 just GPIO
|
||||
IOPortTag & x"08" & StepGenTag & StepGenStepPin, -- I/O 40 PIN 3 PIN 2 X2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 41 PIN 4 PIN 15 just GPIO
|
||||
IOPortTag & x"08" & StepGenTag & StepGenDirPin, -- I/O 42 PIN 5 PIN 3 X2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 43 PIN 6 PIN 16 just GPIO
|
||||
IOPortTag & x"09" & StepGenTag & StepGenStepPin, -- I/O 44 PIN 7 PIN 4 Y2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 45 PIN 8 PIN 17 just GPIO
|
||||
IOPortTag & x"09" & StepGenTag & StepGenDirPin, -- I/O 46 PIN 9 PIN 5 Y2 Step
|
||||
IOPortTag & x"0A" & StepGenTag & StepGenStepPin, -- I/O 47 PIN 11 PIN 6 Z2 Dir
|
||||
IOPortTag & x"0A" & StepGenTag & StepGenDirPin, -- I/O 48 PIN 13 PIN 7 Z2 Step
|
||||
IOPortTag & x"0B" & StepGenTag & StepGenStepPin, -- I/O 49 PIN 15 PIN 8 A2 Dir
|
||||
IOPortTag & x"0B" & StepGenTag & StepGenDIrPin, -- I/O 50 PIN 17 PIN 9 A2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 51 PIN 19 PIN 10 just GPIO
|
||||
IOPortTag & x"02" & QCountTag & QCountQAPin, -- I/O 52 PIN 21 PIN 11 Input 2 (Quad A)
|
||||
IOPortTag & x"02" & QCountTag & QCountQBPin, -- I/O 53 PIN 23 PIN 12 Input 3 (Quad B))
|
||||
IOPortTag & x"02" & QCountTag & QCountIdxPin, -- I/O 54 PIN 25 PIN 13 Input 4 (Quad Idx)
|
||||
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 55
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 56
|
||||
|
||||
|
||||
-- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_5ABOBx3D_56;
|
||||
191
5i24/configs/hostmot2/source/PIN_5ABOBx3D_57.vhd
Executable file
191
5i24/configs/hostmot2/source/PIN_5ABOBx3D_57.vhd
Executable file
@@ -0,0 +1,191 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_5ABOBx3D_57 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"03", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"0C", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(PWMTag, x"00", ClockHighTag, x"03", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin -- external DB25
|
||||
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 00 PIN 1 Spindle DAC PWM
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 01 PIN 14 just GPIO
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 02 PIN 2 X Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 03 PIN 15 just GPIO
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 04 PIN 3 X Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 05 PIN 16 B Step
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 06 PIN 4 Y Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 07 PIN 17 B Dir
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 08 PIN 5 Y Dir
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 09 PIN 6 Z Step
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 10 PIN 7 Z Dir
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 11 PIN 8 A Step
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 12 PIN 9 A Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 13 PIN 10 Input 1 just GPIO
|
||||
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 14 PIN 11 Input 2 (Quad A)
|
||||
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 15 PIN 12 Input 3 (Quad B)
|
||||
IOPortTag & x"00" & QCountTag & QCountIdxPin, -- I/O 16 PIN 13 Input 4 (Quad Idx)
|
||||
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 17
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 18
|
||||
|
||||
-- 26 HDR -- IDC DB25
|
||||
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 19 PIN 1 PIN 1 Spindle DAC PWM
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 20 PIN 2 PIN 14 just GPIO
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 21 PIN 3 PIN 2 X2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 22 PIN 4 PIN 15 just GPIO
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 23 PIN 5 PIN 3 X2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 24 PIN 6 PIN 16 just GPIO
|
||||
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 25 PIN 7 PIN 4 Y2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 26 PIN 8 PIN 17 just GPIO
|
||||
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 27 PIN 9 PIN 5 Y2 Step
|
||||
IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 28 PIN 11 PIN 6 Z2 Dir
|
||||
IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 29 PIN 13 PIN 7 Z2 Step
|
||||
IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 30 PIN 15 PIN 8 A2 Dir
|
||||
IOPortTag & x"07" & StepGenTag & StepGenDirPin, -- I/O 31 PIN 17 PIN 9 A2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 32 PIN 19 PIN 10 just GPIO
|
||||
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 33 PIN 21 PIN 11 Input 2 (Quad A)
|
||||
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 34 PIN 23 PIN 12 Input 3 (Quad B))
|
||||
IOPortTag & x"01" & QCountTag & QCountIdxPin, -- I/O 35 PIN 25 PIN 13 Input 4 (Quad Idx)
|
||||
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 36
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 37
|
||||
|
||||
-- 26 HDR -- IDC DB25
|
||||
IOPortTag & x"02" & PWMTag & PWMAOutPin, -- I/O 38 PIN 1 PIN 1 Spindle DAC PWM
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 39 PIN 2 PIN 14 just GPIO
|
||||
IOPortTag & x"08" & StepGenTag & StepGenStepPin, -- I/O 40 PIN 3 PIN 2 X2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 41 PIN 4 PIN 15 just GPIO
|
||||
IOPortTag & x"08" & StepGenTag & StepGenDirPin, -- I/O 42 PIN 5 PIN 3 X2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 43 PIN 6 PIN 16 just GPIO
|
||||
IOPortTag & x"09" & StepGenTag & StepGenStepPin, -- I/O 44 PIN 7 PIN 4 Y2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 45 PIN 8 PIN 17 just GPIO
|
||||
IOPortTag & x"09" & StepGenTag & StepGenDirPin, -- I/O 46 PIN 9 PIN 5 Y2 Step
|
||||
IOPortTag & x"0A" & StepGenTag & StepGenStepPin, -- I/O 47 PIN 11 PIN 6 Z2 Dir
|
||||
IOPortTag & x"0A" & StepGenTag & StepGenDirPin, -- I/O 48 PIN 13 PIN 7 Z2 Step
|
||||
IOPortTag & x"0B" & StepGenTag & StepGenStepPin, -- I/O 49 PIN 15 PIN 8 A2 Dir
|
||||
IOPortTag & x"0B" & StepGenTag & StepGenDirPin, -- I/O 50 PIN 17 PIN 9 A2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 51 PIN 19 PIN 10 just GPIO
|
||||
IOPortTag & x"02" & QCountTag & QCountQAPin, -- I/O 52 PIN 21 PIN 11 Input 2 (Quad A)
|
||||
IOPortTag & x"02" & QCountTag & QCountQBPin, -- I/O 53 PIN 23 PIN 12 Input 3 (Quad B))
|
||||
IOPortTag & x"02" & QCountTag & QCountIdxPin, -- I/O 54 PIN 25 PIN 13 Input 4 (Quad Idx)
|
||||
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 55
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 56
|
||||
|
||||
|
||||
-- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_5ABOBx3D_57;
|
||||
194
5i24/configs/hostmot2/source/PIN_7C801P_5ABOBD_54.vhd
Executable file
194
5i24/configs/hostmot2/source/PIN_7C801P_5ABOBD_54.vhd
Executable file
@@ -0,0 +1,194 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
|
||||
package PIN_7C801P_5ABOBD_54 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"02", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"08", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(PWMTag, x"00", ClockHighTag, x"03", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
|
||||
(XFrmrOutTag, x"00", ClockLowTag, x"01", XFrmrDataAddr&PadT, XFrmrNumRegs, x"00", XFrmrMPBitMask ),
|
||||
(InMuxTag, x"00", ClockLowTag, x"01", InMuxControlAddr&PadT, InMuxNumRegs, x"00", InmuxMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(InMuxWidth0Tag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000018") -- hide this tag here until we find a better way
|
||||
);
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
|
||||
-- Base func sec unit sec func sec pin
|
||||
|
||||
--
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 00 embedded 7C80 Stepgen
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 01
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 02
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 03
|
||||
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 04
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 05
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 06
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 07
|
||||
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 08
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 09
|
||||
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 10
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 11
|
||||
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 12 embedded sserial expansion
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 13
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn0Pin, -- I/O 14
|
||||
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 15 embedded 7C80 encoder
|
||||
|
||||
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 16
|
||||
IOPortTag & x"00" & QCountTag & QCountIDXPin, -- I/O 17
|
||||
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 18 Spindle PWM
|
||||
IOPortTag & x"00" & PWMTag & PWMCEnaPin, -- I/O 19 Analog ENA
|
||||
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 20 ENA/FWD
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 21 DIR/REV
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr0Pin, -- I/O 22 muxadd0
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr1Pin, -- I/O 23 muxadd1
|
||||
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr2Pin, -- I/O 24 muxadd2
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr3Pin, -- I/O 25 muxadd3
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr4Pin, -- I/O 26 muxadd4
|
||||
|
||||
|
||||
IOPortTag & x"00" & InMuxTag & InMuxDataPin, -- I/O 27 muxindata
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut0Pin, -- I/O 28
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut1Pin, -- I/O 29
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut2Pin, -- I/O 30 muxindata
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut3Pin, -- I/O 31
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut4Pin, -- I/O 32
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut5Pin, -- I/O 33
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut6Pin, -- I/O 34
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut7Pin, -- I/O 35
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrRefPin, -- I/O 36
|
||||
IOPortTag & x"02" & PWMTag & PWMAOutPin, -- I/O 37 PIN 1 PIN 1 Spindle DAC PWM
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 48 PIN 2 PIN 14 just GPIO
|
||||
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 59 PIN 3 PIN 2 X2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 40 PIN 4 PIN 15 just GPIO
|
||||
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 41 PIN 5 PIN 3 X2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 42 PIN 6 PIN 16 just GPIO
|
||||
IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 43 PIN 7 PIN 4 Y2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 44 PIN 8 PIN 17 just GPIO
|
||||
IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 45 PIN 9 PIN 5 Y2 Step
|
||||
IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 46 PIN 11 PIN 6 Z2 Dir
|
||||
IOPortTag & x"07" & StepGenTag & StepGenDirPin, -- I/O 47 PIN 13 PIN 7 Z2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 48 PIN 15 PIN 8 just GPIO
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 49 PIN 17 PIN 9 just GPIO
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 50 PIN 19 PIN 10 just GPIO
|
||||
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 51 PIN 21 PIN 11 Input 2 (Quad A)
|
||||
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 52 PIN 23 PIN 12 Input 3 (Quad B))
|
||||
IOPortTag & x"01" & QCountTag & QCountIdxPin, -- I/O 53 PIN 25 PIN 13 Input 4 (Quad Idx)
|
||||
|
||||
|
||||
emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
|
||||
end package PIN_7C801P_5ABOBD_54;
|
||||
194
5i24/configs/hostmot2/source/PIN_7C80D_54.vhd
Executable file
194
5i24/configs/hostmot2/source/PIN_7C80D_54.vhd
Executable file
@@ -0,0 +1,194 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
|
||||
package PIN_7C80D_54 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"01", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"06", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(PWMTag, x"00", ClockHighTag, x"01", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
|
||||
(XFrmrOutTag, x"00", ClockLowTag, x"01", XFrmrDataAddr&PadT, XFrmrNumRegs, x"00", XFrmrMPBitMask ),
|
||||
(InMuxTag, x"00", ClockLowTag, x"01", InMuxControlAddr&PadT, InMuxNumRegs, x"00", InmuxMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(InMuxWidth0Tag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000018") -- hide this tag here until we find a better way
|
||||
);
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
|
||||
-- Base func sec unit sec func sec pin
|
||||
|
||||
--
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 00 embedded 7C80 Stepgen
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 01
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 02
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 03
|
||||
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 04
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 05
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 06
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 07
|
||||
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 08
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 09
|
||||
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 10
|
||||
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 11
|
||||
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 12 embedded sserial expansion
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 13
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn0Pin, -- I/O 14
|
||||
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 15 embedded 7C80 encoder
|
||||
|
||||
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 16
|
||||
IOPortTag & x"00" & QCountTag & QCountIDXPin, -- I/O 17
|
||||
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 18 Spindle PWM
|
||||
IOPortTag & x"00" & PWMTag & PWMCEnaPin, -- I/O 19 Analog ENA
|
||||
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 20 ENA/FWD
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 21 DIR/REV
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr0Pin, -- I/O 22 muxadd0
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr1Pin, -- I/O 23 muxadd1
|
||||
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr2Pin, -- I/O 24 muxadd2
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr3Pin, -- I/O 25 muxadd3
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr4Pin, -- I/O 26 muxadd4
|
||||
|
||||
|
||||
IOPortTag & x"00" & InMuxTag & InMuxDataPin, -- I/O 27 muxindata
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut0Pin, -- I/O 28
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut1Pin, -- I/O 29
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut2Pin, -- I/O 30 muxindata
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut3Pin, -- I/O 31
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut4Pin, -- I/O 32
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut5Pin, -- I/O 33
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut6Pin, -- I/O 34
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut7Pin, -- I/O 35
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrRefPin, -- I/O 36
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 37 10 PIN 1 -- Expansion port
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 38 11 PIN 14
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 39 12 PIN 2
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 40 13 PIN 15
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 41 14 PIN 3
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 42 15 PIN 16
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 43 16 PIN 4
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 44 17 PIN 17
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 45 18 PIN 5
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 46 19 PIN 6
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 47 20 PIN 7
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 48 21 PIN 8
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 49 22 PIN 9
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 50 23 PIN 10
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 51 24 PIN 11
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 52 25 PIN 12
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 53 26 PIN 13
|
||||
|
||||
|
||||
emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
|
||||
end package PIN_7C80D_54;
|
||||
194
5i24/configs/hostmot2/source/PIN_7C80FALL_54.vhd
Executable file
194
5i24/configs/hostmot2/source/PIN_7C80FALL_54.vhd
Executable file
@@ -0,0 +1,194 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
|
||||
package PIN_7C80FALL_54 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
|
||||
-- Base func sec unit sec func sec pin
|
||||
|
||||
--
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 00 embedded 7C80 Stepgen
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 01
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 02
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 03
|
||||
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 04
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 05
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 06
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 07
|
||||
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 08
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 09
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 10
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 11
|
||||
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 12 embedded sserial expansion
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 13
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 14
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 15 embedded 7C80 encoder
|
||||
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 16
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 17
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 18 Spindle PWM
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 19 Analog ENA
|
||||
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 20 ENA/FWD
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 21 DIR/REV
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 22 muxadd0
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 23 muxadd1
|
||||
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 24 muxadd2
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 25 muxadd3
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 26 muxadd4
|
||||
|
||||
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 27 muxindata
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 28
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 29
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 30 muxindata
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 31
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 32
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 33
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 34
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 35
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 36
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 37 10 PIN 1 -- Expansion port
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 38 11 PIN 14
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 39 12 PIN 2
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 40 13 PIN 15
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 41 14 PIN 3
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 42 15 PIN 16
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 43 16 PIN 4
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 44 17 PIN 17
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 45 18 PIN 5
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 46 19 PIN 6
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 47 20 PIN 7
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 48 21 PIN 8
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 49 22 PIN 9
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 50 23 PIN 10
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 51 24 PIN 11
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 52 25 PIN 12
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 53 26 PIN 13
|
||||
|
||||
|
||||
emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
|
||||
end package PIN_7C80FALL_54;
|
||||
194
5i24/configs/hostmot2/source/PIN_7C80PKTD_54.vhd
Executable file
194
5i24/configs/hostmot2/source/PIN_7C80PKTD_54.vhd
Executable file
@@ -0,0 +1,194 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
|
||||
package PIN_7C80PKTD_54 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"01", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"06", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(PktUARTTTag, x"02", ClockLowTag, x"01", PktUARTTDataAddr&PadT, PktUARTTNumRegs, x"00", PktUARTTMPBitMask),
|
||||
(PktUARTRTag, x"02", ClockLowTag, x"01", PktUARTRDataAddr&PadT, PktUARTRNumRegs, x"00", PktUARTRMPBitMask),
|
||||
(PWMTag, x"00", ClockHighTag, x"01", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
|
||||
(XFrmrOutTag, x"00", ClockLowTag, x"01", XFrmrDataAddr&PadT, XFrmrNumRegs, x"00", XFrmrMPBitMask ),
|
||||
(InMuxTag, x"00", ClockLowTag, x"01", InMuxControlAddr&PadT, InMuxNumRegs, x"00", InmuxMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(InMuxWidth0Tag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000018") -- hide this tag here until we find a better way
|
||||
);
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
|
||||
-- Base func sec unit sec func sec pin
|
||||
|
||||
--
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 00 embedded 7C80 Stepgen
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 01
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 02
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 03
|
||||
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 04
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 05
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 06
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 07
|
||||
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 08
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 09
|
||||
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 10
|
||||
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 11
|
||||
|
||||
IOPortTag & x"00" & PktUARTRTag & PktURDataPin, -- I/O 12 PktUART channel
|
||||
IOPortTag & x"00" & PktUARTTTag & PktUTDataPin, -- I/O 13
|
||||
IOPortTag & x"00" & PktUARTTTag & PktUTDrvEnPin, -- I/O 14
|
||||
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 15 embedded 7C80 encoder
|
||||
|
||||
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 16
|
||||
IOPortTag & x"00" & QCountTag & QCountIDXPin, -- I/O 17
|
||||
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 18 Spindle PWM
|
||||
IOPortTag & x"00" & PWMTag & PWMCEnaPin, -- I/O 19 Analog ENA
|
||||
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 20 ENA/FWD
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 21 DIR/REV
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr0Pin, -- I/O 22 muxadd0
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr1Pin, -- I/O 23 muxadd1
|
||||
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr2Pin, -- I/O 24 muxadd2
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr3Pin, -- I/O 25 muxadd3
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr4Pin, -- I/O 26 muxadd4
|
||||
|
||||
|
||||
IOPortTag & x"00" & InMuxTag & InMuxDataPin, -- I/O 27 muxindata
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut0Pin, -- I/O 28
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut1Pin, -- I/O 29
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut2Pin, -- I/O 30 muxindata
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut3Pin, -- I/O 31
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut4Pin, -- I/O 32
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut5Pin, -- I/O 33
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut6Pin, -- I/O 34
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut7Pin, -- I/O 35
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrRefPin, -- I/O 36
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 37 10 PIN 1 -- Expansion port
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 38 11 PIN 14
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 39 12 PIN 2
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 40 13 PIN 15
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 41 14 PIN 3
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 42 15 PIN 16
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 43 16 PIN 4
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 44 17 PIN 17
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 45 18 PIN 5
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 46 19 PIN 6
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 47 20 PIN 7
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 48 21 PIN 8
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 49 22 PIN 9
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 50 23 PIN 10
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 51 24 PIN 11
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 52 25 PIN 12
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 53 26 PIN 13
|
||||
|
||||
|
||||
emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
|
||||
end package PIN_7C80PKTD_54;
|
||||
194
5i24/configs/hostmot2/source/PIN_7C80_5ABOBD_54.vhd
Executable file
194
5i24/configs/hostmot2/source/PIN_7C80_5ABOBD_54.vhd
Executable file
@@ -0,0 +1,194 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
|
||||
package PIN_7C80_5ABOBD_54 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"02", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"09", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(PWMTag, x"00", ClockHighTag, x"02", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
|
||||
(XFrmrOutTag, x"00", ClockLowTag, x"01", XFrmrDataAddr&PadT, XFrmrNumRegs, x"00", XFrmrMPBitMask ),
|
||||
(InMuxTag, x"00", ClockLowTag, x"01", InMuxControlAddr&PadT, InMuxNumRegs, x"00", InmuxMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(InMuxWidth0Tag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000018") -- hide this tag here until we find a better way
|
||||
);
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
|
||||
-- Base func sec unit sec func sec pin
|
||||
|
||||
--
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 00 embedded 7C80 Stepgen
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 01
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 02
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 03
|
||||
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 04
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 05
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 06
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 07
|
||||
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 08
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 09
|
||||
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 10
|
||||
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 11
|
||||
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 12 embedded sserial expansion
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 13
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn0Pin, -- I/O 14
|
||||
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 15 embedded 7C80 encoder
|
||||
|
||||
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 16
|
||||
IOPortTag & x"00" & QCountTag & QCountIDXPin, -- I/O 17
|
||||
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 18 Spindle PWM
|
||||
IOPortTag & x"00" & PWMTag & PWMCEnaPin, -- I/O 19 Analog ENA
|
||||
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 20 ENA/FWD
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 21 DIR/REV
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr0Pin, -- I/O 22 muxadd0
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr1Pin, -- I/O 23 muxadd1
|
||||
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr2Pin, -- I/O 24 muxadd2
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr3Pin, -- I/O 25 muxadd3
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr4Pin, -- I/O 26 muxadd4
|
||||
|
||||
|
||||
IOPortTag & x"00" & InMuxTag & InMuxDataPin, -- I/O 27 muxindata
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut0Pin, -- I/O 28
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut1Pin, -- I/O 29
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut2Pin, -- I/O 30 muxindata
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut3Pin, -- I/O 31
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut4Pin, -- I/O 32
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut5Pin, -- I/O 33
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut6Pin, -- I/O 34
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut7Pin, -- I/O 35
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrRefPin, -- I/O 36
|
||||
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 37 PIN 1 PIN 1 Spindle DAC PWM
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 48 PIN 2 PIN 14 just GPIO
|
||||
IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 59 PIN 3 PIN 2 X2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 40 PIN 4 PIN 15 just GPIO
|
||||
IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 41 PIN 5 PIN 3 X2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 42 PIN 6 PIN 16 just GPIO
|
||||
IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 43 PIN 7 PIN 4 Y2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 44 PIN 8 PIN 17 just GPIO
|
||||
IOPortTag & x"07" & StepGenTag & StepGenDirPin, -- I/O 45 PIN 9 PIN 5 Y2 Step
|
||||
IOPortTag & x"08" & StepGenTag & StepGenStepPin, -- I/O 46 PIN 11 PIN 6 Z2 Dir
|
||||
IOPortTag & x"08" & StepGenTag & StepGenDirPin, -- I/O 47 PIN 13 PIN 7 Z2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 48 PIN 15 PIN 8 just GPIO
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 49 PIN 17 PIN 9 just GPIO
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 50 PIN 19 PIN 10 just GPIO
|
||||
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 51 PIN 21 PIN 11 Input 2 (Quad A)
|
||||
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 52 PIN 23 PIN 12 Input 3 (Quad B))
|
||||
IOPortTag & x"01" & QCountTag & QCountIdxPin, -- I/O 53 PIN 25 PIN 13 Input 4 (Quad Idx)
|
||||
|
||||
|
||||
emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
|
||||
end package PIN_7C80_5ABOBD_54;
|
||||
195
5i24/configs/hostmot2/source/PIN_7C80_7I74D_54.vhd
Executable file
195
5i24/configs/hostmot2/source/PIN_7C80_7I74D_54.vhd
Executable file
@@ -0,0 +1,195 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
|
||||
package PIN_7C80_7I74D_54 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"01", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"06", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(PWMTag, x"00", ClockHighTag, x"01", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
|
||||
(XFrmrOutTag, x"00", ClockLowTag, x"01", XFrmrDataAddr&PadT, XFrmrNumRegs, x"00", XFrmrMPBitMask ),
|
||||
(InMuxTag, x"00", ClockLowTag, x"01", InMuxControlAddr&PadT, InMuxNumRegs, x"00", InmuxMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(InMuxWidth0Tag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000018") -- hide this tag here until we find a better way
|
||||
);
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
|
||||
-- Base func sec unit sec func sec pin
|
||||
|
||||
--
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 00 embedded 7C80 Stepgen
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 01
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 02
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 03
|
||||
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 04
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 05
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 06
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 07
|
||||
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 08
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 09
|
||||
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 10
|
||||
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 11
|
||||
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 12 embedded sserial expansion
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 13
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn0Pin, -- I/O 14
|
||||
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 15 embedded 7C80 encoder
|
||||
|
||||
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 16
|
||||
IOPortTag & x"00" & QCountTag & QCountIDXPin, -- I/O 17
|
||||
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 18 Spindle PWM
|
||||
IOPortTag & x"00" & PWMTag & PWMCEnaPin, -- I/O 19 Analog ENA
|
||||
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 20 ENA/FWD
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 21 DIR/REV
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr0Pin, -- I/O 22 muxadd0
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr1Pin, -- I/O 23 muxadd1
|
||||
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr2Pin, -- I/O 24 muxadd2
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr3Pin, -- I/O 25 muxadd3
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr4Pin, -- I/O 26 muxadd4
|
||||
|
||||
|
||||
IOPortTag & x"00" & InMuxTag & InMuxDataPin, -- I/O 27 muxindata
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut0Pin, -- I/O 28
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut1Pin, -- I/O 29
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut2Pin, -- I/O 30 muxindata
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut3Pin, -- I/O 31
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut4Pin, -- I/O 32
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut5Pin, -- I/O 33
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut6Pin, -- I/O 34
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut7Pin, -- I/O 35
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrRefPin, -- I/O 36
|
||||
-- Base func sec unit sec func sec pin -- P3 DB25
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 37 PIN 1
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, -- I/O 38 PIN 14
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX3Pin, -- I/O 39 PIN 2
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX4Pin, -- I/O 40 PIN 15
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 41 PIN 3
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, -- I/O 42 PIN 16
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX3Pin, -- I/O 43 PIN 4
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX4Pin, -- I/O 44 PIN 17
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX5Pin, -- I/O 45 PIN 5
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX6Pin, -- I/O 46 PIN 6
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 47 PIN 7
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 48 PIN 8
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX5Pin, -- I/O 49 PIN 9
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX6Pin, -- I/O 50 PIN 10
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 51 PIN 11
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 52 PIN 12
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 53 PIN 13
|
||||
|
||||
|
||||
emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
|
||||
end package PIN_7C80_7I74D_54;
|
||||
195
5i24/configs/hostmot2/source/PIN_7C80_7I74SSID_54.vhd
Executable file
195
5i24/configs/hostmot2/source/PIN_7C80_7I74SSID_54.vhd
Executable file
@@ -0,0 +1,195 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
|
||||
package PIN_7C80_7I74SSID_54 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"01", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"06", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(SSSITag, x"00", ClockLowTag, x"08", SSSIDataAddr0&PadT, SSSINumRegs, x"00", SSSIMPBitMask),
|
||||
(PWMTag, x"00", ClockHighTag, x"01", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
|
||||
(XFrmrOutTag, x"00", ClockLowTag, x"01", XFrmrDataAddr&PadT, XFrmrNumRegs, x"00", XFrmrMPBitMask ),
|
||||
(InMuxTag, x"00", ClockLowTag, x"01", InMuxControlAddr&PadT, InMuxNumRegs, x"00", InmuxMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(InMuxWidth0Tag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000018") -- hide this tag here until we find a better way
|
||||
);
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
|
||||
-- Base func sec unit sec func sec pin
|
||||
|
||||
--
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 00 embedded 7C80 Stepgen
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 01
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 02
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 03
|
||||
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 04
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 05
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 06
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 07
|
||||
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 08
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 09
|
||||
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 10
|
||||
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 11
|
||||
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 12 embedded sserial expansion
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 13
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn0Pin, -- I/O 14
|
||||
IOPortTag & x"00" & QCountTag & QCountQAPin, -- I/O 15 embedded 7C80 encoder
|
||||
|
||||
IOPortTag & x"00" & QCountTag & QCountQBPin, -- I/O 16
|
||||
IOPortTag & x"00" & QCountTag & QCountIDXPin, -- I/O 17
|
||||
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 18 Spindle PWM
|
||||
IOPortTag & x"00" & PWMTag & PWMCEnaPin, -- I/O 19 Analog ENA
|
||||
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 20 ENA/FWD
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 21 DIR/REV
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr0Pin, -- I/O 22 muxadd0
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr1Pin, -- I/O 23 muxadd1
|
||||
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr2Pin, -- I/O 24 muxadd2
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr3Pin, -- I/O 25 muxadd3
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr4Pin, -- I/O 26 muxadd4
|
||||
|
||||
|
||||
IOPortTag & x"00" & InMuxTag & InMuxDataPin, -- I/O 27 muxindata
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut0Pin, -- I/O 28
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut1Pin, -- I/O 29
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut2Pin, -- I/O 30 muxindata
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut3Pin, -- I/O 31
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut4Pin, -- I/O 32
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut5Pin, -- I/O 33
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut6Pin, -- I/O 34
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut7Pin, -- I/O 35
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrRefPin, -- I/O 36
|
||||
-- P2 26 HDR DB25
|
||||
IOPortTag & x"00" & SSSITag & SSSIDataPin, -- I/O 37 PIN 1 PIN 1
|
||||
IOPortTag & x"01" & SSSITag & SSSIDataPin, -- I/O 38 PIN 2 PIN 14
|
||||
IOPortTag & x"02" & SSSITag & SSSIDataPin, -- I/O 39 PIN 3 PIN 2
|
||||
IOPortTag & x"03" & SSSITag & SSSIDataPin, -- I/O 40 PIN 4 PIN 15
|
||||
IOPortTag & x"00" & SSSITag & SSSIClkPin, -- I/O 41 PIN 5 PIN 3
|
||||
IOPortTag & x"01" & SSSITag & SSSIClkPin, -- I/O 42 PIN 6 PIN 16
|
||||
IOPortTag & x"02" & SSSITag & SSSIClkPin, -- I/O 43 PIN 7 PIN 4
|
||||
IOPortTag & x"03" & SSSITag & SSSIClkPin, -- I/O 44 PIN 8 PIN 17
|
||||
IOPortTag & x"04" & SSSITag & SSSIDataPin, -- I/O 45 PIN 9 PIN 5
|
||||
IOPortTag & x"05" & SSSITag & SSSIDataPin, -- I/O 46 PIN 11 PIN 6
|
||||
IOPortTag & x"06" & SSSITag & SSSIDataPin, -- I/O 47 PIN 13 PIN 7
|
||||
IOPortTag & x"07" & SSSITag & SSSIDataPin, -- I/O 48 PIN 15 PIN 8
|
||||
IOPortTag & x"04" & SSSITag & SSSIClkPin, -- I/O 49 PIN 17 PIN 9
|
||||
IOPortTag & x"05" & SSSITag & SSSIClkPin, -- I/O 50 PIN 19 PIN 10
|
||||
IOPortTag & x"06" & SSSITag & SSSIClkPin, -- I/O 51 PIN 21 PIN 11
|
||||
IOPortTag & x"07" & SSSITag & SSSIClkPin, -- I/O 52 PIN 23 PIN 12
|
||||
IOPortTag & x"07" & SSSITag & SSSIClkEnPin, -- I/O 53 PIN 25 PIN 13
|
||||
|
||||
|
||||
emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
|
||||
end package PIN_7C80_7I74SSID_54;
|
||||
194
5i24/configs/hostmot2/source/PIN_7C80_7I85D_54.vhd
Executable file
194
5i24/configs/hostmot2/source/PIN_7C80_7I85D_54.vhd
Executable file
@@ -0,0 +1,194 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
|
||||
package PIN_7C80_7I85D_54 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(MuxedQcountTag, MQCRev, ClockLowTag, x"06", MuxedQcounterAddr&PadT, MuxedQCounterNumRegs,x"00", MuxedQCounterMPBitMask),
|
||||
(MuxedQCountSelTag, x"00", ClockLowTag, x"01", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(StepGenTag, x"02", ClockLowTag, x"06", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(PWMTag, x"00", ClockHighTag, x"01", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
|
||||
(XFrmrOutTag, x"00", ClockLowTag, x"01", XFrmrDataAddr&PadT, XFrmrNumRegs, x"00", XFrmrMPBitMask ),
|
||||
(InMuxTag, x"00", ClockLowTag, x"01", InMuxControlAddr&PadT, InMuxNumRegs, x"00", InmuxMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(InMuxWidth0Tag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000018") -- hide this tag here until we find a better way
|
||||
);
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
|
||||
-- Base func sec unit sec func sec pin
|
||||
|
||||
--
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 00 embedded 7C80 Stepgen
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 01
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 02
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 03
|
||||
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 04
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 05
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 06
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 07
|
||||
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 08
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 09
|
||||
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 10
|
||||
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 11
|
||||
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 12 embedded sserial expansion
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 13
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn0Pin, -- I/O 14
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 15 embedded 7C80 encoder
|
||||
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 16
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 17
|
||||
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 18 Spindle PWM
|
||||
IOPortTag & x"00" & PWMTag & PWMCEnaPin, -- I/O 19 Analog ENA
|
||||
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 20 ENA/FWD
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 21 DIR/REV
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr0Pin, -- I/O 22 muxadd0
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr1Pin, -- I/O 23 muxadd1
|
||||
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr2Pin, -- I/O 24 muxadd2
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr3Pin, -- I/O 25 muxadd3
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr4Pin, -- I/O 26 muxadd4
|
||||
|
||||
|
||||
IOPortTag & x"00" & InMuxTag & InMuxDataPin, -- I/O 27 muxindata
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut0Pin, -- I/O 28
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut1Pin, -- I/O 29
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut2Pin, -- I/O 30 muxindata
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut3Pin, -- I/O 31
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut4Pin, -- I/O 32
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut5Pin, -- I/O 33
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut6Pin, -- I/O 34
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut7Pin, -- I/O 35
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrRefPin, -- I/O 36
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 00 PIN 1
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 01 PIN 14
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 02 PIN 2
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 03 PIN 15
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX3Pin, -- I/O 04 PIN 3
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX3Pin, -- I/O 05 PIN 16
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, -- I/O 06 PIN 4
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, -- I/O 07 PIN 17
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 08 PIN 5
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 09 PIN 6
|
||||
IOPortTag & x"00" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 10 PIN 7
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 11 PIN 8
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 12 PIN 9
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 13 PIN 10
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 14 PIN 11
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 15 PIN 12
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 16 PIN 13
|
||||
|
||||
|
||||
emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
|
||||
end package PIN_7C80_7I85D_54;
|
||||
194
5i24/configs/hostmot2/source/PIN_7C80_7I89D_54.vhd
Executable file
194
5i24/configs/hostmot2/source/PIN_7C80_7I89D_54.vhd
Executable file
@@ -0,0 +1,194 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
|
||||
package PIN_7C80_7I89D_54 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(MuxedQcountTag, MQCRev, ClockLowTag, x"0A", MuxedQcounterAddr&PadT, MuxedQCounterNumRegs,x"00", MuxedQCounterMPBitMask),
|
||||
(MuxedQCountSelTag, x"00", ClockLowTag, x"01", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(StepGenTag, x"02", ClockLowTag, x"06", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(PWMTag, x"00", ClockHighTag, x"01", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
|
||||
(XFrmrOutTag, x"00", ClockLowTag, x"01", XFrmrDataAddr&PadT, XFrmrNumRegs, x"00", XFrmrMPBitMask ),
|
||||
(InMuxTag, x"00", ClockLowTag, x"01", InMuxControlAddr&PadT, InMuxNumRegs, x"00", InmuxMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(InMuxWidth0Tag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000018") -- hide this tag here until we find a better way
|
||||
);
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
|
||||
-- Base func sec unit sec func sec pin
|
||||
|
||||
--
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 00 embedded 7C80 Stepgen
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 01
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 02
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 03
|
||||
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 04
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 05
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 06
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 07
|
||||
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 08
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 09
|
||||
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 10
|
||||
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 11
|
||||
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 12 embedded sserial expansion
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 13
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn0Pin, -- I/O 14
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 15 embedded 7C80 encoder
|
||||
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 16
|
||||
IOPortTag & x"04" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 17
|
||||
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 18 Spindle PWM
|
||||
IOPortTag & x"00" & PWMTag & PWMCEnaPin, -- I/O 19 Analog ENA
|
||||
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 20 ENA/FWD
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 21 DIR/REV
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr0Pin, -- I/O 22 muxadd0
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr1Pin, -- I/O 23 muxadd1
|
||||
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr2Pin, -- I/O 24 muxadd2
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr3Pin, -- I/O 25 muxadd3
|
||||
IOPortTag & x"00" & InMuxTag & InMuxAddr4Pin, -- I/O 26 muxadd4
|
||||
|
||||
|
||||
IOPortTag & x"00" & InMuxTag & InMuxDataPin, -- I/O 27 muxindata
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut0Pin, -- I/O 28
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut1Pin, -- I/O 29
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut2Pin, -- I/O 30 muxindata
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut3Pin, -- I/O 31
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut4Pin, -- I/O 32
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut5Pin, -- I/O 33
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut6Pin, -- I/O 34
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrOut7Pin, -- I/O 35
|
||||
IOPortTag & x"00" & XfrmrOutTag & XfrmrRefPin, -- I/O 36
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 37 PIN 1
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 38 PIN 14
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 39 PIN 2
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 40 PIN 15
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 41 PIN 3
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 42 PIN 16
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 43 PIN 4
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 44 PIN 17
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 45 PIN 5
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 46 PIN 6
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 47 PIN 7
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 48 PIN 8
|
||||
IOPortTag & x"00" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 49 PIN 9
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 50 PIN 10 POWOP
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 51 PIN 11
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 52 PIN 12
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEN1Pin, -- I/O 53 PIN 13
|
||||
|
||||
|
||||
emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
|
||||
end package PIN_7C80_7I89D_54;
|
||||
196
5i24/configs/hostmot2/source/PIN_7I49_7I77_72.vhd
Executable file
196
5i24/configs/hostmot2/source/PIN_7I49_7I77_72.vhd
Executable file
@@ -0,0 +1,196 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_7I49_7I77_72 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(MuxedQcountTag, MQCRev, ClockLowTag, x"06", MuxedQcounterAddr&PadT, MuxedQCounterNumRegs,x"00", MuxedQCounterMPBitMask),
|
||||
(MuxedQCountSelTag, x"00", ClockLowTag, x"01", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(ResModTag, x"00", ClockLowTag, x"01", ResModCommandAddr&PadT, ResModNumRegs, x"00", ResModMPBitMask),
|
||||
(PWMTag, x"00", ClockHighTag, x"06", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin
|
||||
IOPortTag & x"00" & PWMTag & PWMCEnaPin, -- I/O 00
|
||||
IOPortTag & x"00" & ResModTag & ResModPwrEnPin, -- I/O 01
|
||||
IOPortTag & x"00" & ResModTag & ResModSPIDI0Pin, -- I/O 02
|
||||
IOPortTag & x"00" & ResModTag & ResModSPIDI1Pin, -- I/O 03
|
||||
IOPortTag & x"00" & ResModTag & ResModChan2Pin, -- I/O 04
|
||||
IOPortTag & x"00" & ResModTag & ResModChan1Pin, -- I/O 05
|
||||
IOPortTag & x"00" & ResModTag & ResModChan0Pin, -- I/O 06
|
||||
IOPortTag & x"00" & ResModTag & ResModSPIClkPin, -- I/O 07
|
||||
IOPortTag & x"00" & ResModTag & ResModSPICSPin, -- I/O 08
|
||||
IOPortTag & x"00" & ResModTag & ResModPDMMPin, -- I/O 09
|
||||
IOPortTag & x"00" & ResModTag & ResModPDMPPin, -- I/O 10
|
||||
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 11
|
||||
IOPortTag & x"00" & PWMTag & PWMBDirPin, -- I/O 12
|
||||
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 13
|
||||
IOPortTag & x"01" & PWMTag & PWMBDirPin, -- I/O 14
|
||||
IOPortTag & x"02" & PWMTag & PWMAOutPin, -- I/O 15
|
||||
IOPortTag & x"02" & PWMTag & PWMBDirPin, -- I/O 16
|
||||
IOPortTag & x"03" & PWMTag & PWMAOutPin, -- I/O 17
|
||||
IOPortTag & x"03" & PWMTag & PWMBDirPin, -- I/O 18
|
||||
IOPortTag & x"04" & PWMTag & PWMAOutPin, -- I/O 19
|
||||
IOPortTag & x"04" & PWMTag & PWMBDirPin, -- I/O 20
|
||||
IOPortTag & x"05" & PWMTag & PWMAOutPin, -- I/O 21
|
||||
IOPortTag & x"05" & PWMTag & PWMBDirPin, -- I/O 22
|
||||
IOPortTag & x"00" & PWMTag & PWMCEnaPin, -- I/O 23
|
||||
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEN2Pin, -- I/O 24
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, -- I/O 25
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, -- I/O 26
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 27
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 28
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 29
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 30
|
||||
IOPortTag & x"00" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 31
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 32
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 33
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 34
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 35
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 36
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 37
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 38
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 39
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 40
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 41
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 42
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 43
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 44
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 45
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 46
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 47
|
||||
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 48
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 49
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 50
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 51
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 52
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 53
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 54
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 55
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 56
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 57
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 58
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 59
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 60
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 61
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 62
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 63
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 64
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 65
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 66
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 67
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 68
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 69
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 70
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 71
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_7I49_7I77_72;
|
||||
197
5i24/configs/hostmot2/source/PIN_7I65_7I44_72.vhd
Executable file
197
5i24/configs/hostmot2/source/PIN_7I65_7I44_72.vhd
Executable file
@@ -0,0 +1,197 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_7I65_7I44_72 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(MuxedQcountTag, MQCRev, ClockLowTag, x"08", MuxedQcounterAddr&PadT, MuxedQCounterNumRegs, x"00", MuxedQCounterMPBitMask),
|
||||
(MuxedQCountSelTag, x"00", ClockLowTag, x"01", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(BSPITag, x"00", ClockLowTag, x"01", BSPIDataAddr&PadT, BSPINumRegs, x"11", BSPIMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 00
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 01
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 02
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 03
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 04
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 05
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 06
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 07
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 08
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 09
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 10
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 11
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 12
|
||||
IOPortTag & x"00" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 37
|
||||
IOPortTag & x"00" & BSPITag & BSPIFramePin, -- I/O 14
|
||||
IOPortTag & x"00" & BSPITag & BSPIOutPin, -- I/O 15
|
||||
IOPortTag & x"00" & BSPITag & BSPIClkPin, -- I/O 16
|
||||
IOPortTag & x"00" & BSPITag & BSPIInPin, -- I/O 17
|
||||
IOPortTag & x"00" & BSPITag & BSPICS2Pin, -- I/O 18
|
||||
IOPortTag & x"00" & BSPITag & BSPICS1Pin, -- I/O 19
|
||||
IOPortTag & x"00" & BSPITag & BSPICS0Pin, -- I/O 20
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 21
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 22
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 23
|
||||
|
||||
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 24
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 25
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 26
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 27
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 28
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 29
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 30
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 31
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 32
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 33
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 34
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 35
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 36
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 37
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 38
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 39
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 40
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 41
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 42
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 43
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 44
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 45
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 46
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 47
|
||||
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 48
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 49
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, -- I/O 50
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX3Pin, -- I/O 51
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 52
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn0Pin, -- I/O 53
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 54
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn1Pin, -- I/O 55
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, -- I/O 56
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn2Pin, -- I/O 57
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX3Pin, -- I/O 58
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn3Pin, -- I/O 59
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX4Pin, -- I/O 60
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX5Pin, -- I/O 61
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX6Pin, -- I/O 62
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX7Pin, -- I/O 63
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX4Pin, -- I/O 64
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn4Pin, -- I/O 65
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX5Pin, -- I/O 66
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn5Pin, -- I/O 67
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX6Pin, -- I/O 68
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn6Pin, -- I/O 69
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX7Pin, -- I/O 70
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn7Pin, -- I/O 71
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_7I65_7I44_72;
|
||||
168
5i24/configs/hostmot2/source/PIN_7I74_7I76_34.vhd
Executable file
168
5i24/configs/hostmot2/source/PIN_7I74_7I76_34.vhd
Executable file
@@ -0,0 +1,168 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_7I74_7I76_34 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"01", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"02", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"05", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin
|
||||
-- external DB25
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX0Pin, -- I/O 00 PIN 1
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX1Pin, -- I/O 01 PIN 14
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX2Pin, -- I/O 02 PIN 2
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX3Pin, -- I/O 03 PIN 15
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX0Pin, -- I/O 04 PIN 3
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX1Pin, -- I/O 05 PIN 16
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX2Pin, -- I/O 06 PIN 4
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX3Pin, -- I/O 07 PIN 17
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX4Pin, -- I/O 08 PIN 5
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX5Pin, -- I/O 09 PIN 6
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX6Pin, -- I/O 10 PIN 7
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX7Pin, -- I/O 11 PIN 8
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX4Pin, -- I/O 12 PIN 9
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX5Pin, -- I/O 13 PIN 10
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX6Pin, -- I/O 14 PIN 11
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX7Pin, -- I/O 15 PIN 12
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTXEn7Pin, -- I/O 16 PIN 13
|
||||
|
||||
-- DB25 IDC 26
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 17 PIN 1 PIN 1
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 18 PIN 14 PIN 2
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 19 PIN 2 PIN 3
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 20 PIN 15 PIN 4
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 21 PIN 3 PIN 5
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 22 PIN 16 PIN 6
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 23 PIN 4 PIN 7
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 24 PIN 17 PIN 8
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 25 PIN 5 PIN 9
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 26 PIN 6 PIN 11
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 27 PIN 7 PIN 13
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 28 PIN 8 PIN 15
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 29 PIN 9 PIN 17
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 30 PIN 10 PIN 19
|
||||
IOPortTag & x"00" & QCountTag & x"03", -- I/O 31 PIN 11 PIN 21
|
||||
IOPortTag & x"00" & QCountTag & x"02", -- I/O 32 PIN 12 PIN 23
|
||||
IOPortTag & x"00" & QCountTag & x"01", -- I/O 33 PIN 13 PIN 25
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_7I74_7I76_34;
|
||||
167
5i24/configs/hostmot2/source/PIN_7I74_7I77_34.vhd
Executable file
167
5i24/configs/hostmot2/source/PIN_7I74_7I77_34.vhd
Executable file
@@ -0,0 +1,167 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_7I74_7I77_34 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(MuxedQcountTag, MQCRev, ClockLowTag, x"06", MuxedQcounterAddr&PadT, MuxedQCounterNumRegs,x"00", MuxedQCounterMPBitMask),
|
||||
(MuxedQCountSelTag, x"00", ClockLowTag, x"01", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(SSerialTag, x"00", ClockLowTag, x"02", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin -- P3 DB25
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX0Pin, -- I/O 00 PIN 1
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX1Pin, -- I/O 01 PIN 14
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX2Pin, -- I/O 02 PIN 2
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX3Pin, -- I/O 03 PIN 15
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX0Pin, -- I/O 04 PIN 3
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX1Pin, -- I/O 05 PIN 16
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX2Pin, -- I/O 06 PIN 4
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX3Pin, -- I/O 07 PIN 17
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX4Pin, -- I/O 08 PIN 5
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX5Pin, -- I/O 09 PIN 6
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX6Pin, -- I/O 10 PIN 7
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX7Pin, -- I/O 11 PIN 8
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX4Pin, -- I/O 12 PIN 9
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX5Pin, -- I/O 13 PIN 10
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX6Pin, -- I/O 14 PIN 11
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX7Pin, -- I/O 15 PIN 12
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTXEn7Pin, -- I/O 16 PIN 13
|
||||
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEN2Pin, -- I/O 17 PIN 1 PIN 1
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, -- I/O 18 PIN 2 PIN 14
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, -- I/O 19 PIN 3 PIN 2
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 20 PIN 4 PIN 15
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 21 PIN 5 PIN 3
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 22 PIN 6 PIN 16
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 23 PIN 7 PIN 4
|
||||
IOPortTag & x"00" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 24 PIN 8 PIN 17
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 25 PIN 9 PIN 5
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 26 PIN 11 PIN 6
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 27 PIN 13 PIN 7
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 28 PIN 15 PIN 8
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 29 PIN 17 PIN 9
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 30 PIN 19 PIN 10
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 31 PIN 21 PIN 11
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 32 PIN 23 PIN 12
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 33 PIN 25 PIN 13
|
||||
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_7I74_7I77_34;
|
||||
166
5i24/configs/hostmot2/source/PIN_7I74_PKT_34.vhd
Executable file
166
5i24/configs/hostmot2/source/PIN_7I74_PKT_34.vhd
Executable file
@@ -0,0 +1,166 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_7I74_PKT_34 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(PktUARTTTag, x"00", ClockLowTag, x"08", PktUARTTDataAddr&PadT, PktUARTTNumRegs, x"00", PktUARTTMPBitMask),
|
||||
(PktUARTRTag, x"00", ClockLowTag, x"08", PktUARTRDataAddr&PadT, PktUARTRNumRegs, x"00", PktUARTRMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin -- P3 DB25
|
||||
IOPortTag & x"00" & PktUARTRTag & PktURDataPin, -- I/O 00 PIN 1
|
||||
IOPortTag & x"01" & PktUARTRTag & PktURDataPin, -- I/O 01 PIN 14
|
||||
IOPortTag & x"02" & PktUARTRTag & PktURDataPin, -- I/O 02 PIN 2
|
||||
IOPortTag & x"03" & PktUARTRTag & PktURDataPin, -- I/O 03 PIN 15
|
||||
IOPortTag & x"00" & PktUARTTTag & PktUTDataPin, -- I/O 04 PIN 3
|
||||
IOPortTag & x"01" & PktUARTTTag & PktUTDataPin, -- I/O 05 PIN 16
|
||||
IOPortTag & x"02" & PktUARTTTag & PktUTDataPin, -- I/O 06 PIN 4
|
||||
IOPortTag & x"03" & PktUARTTTag & PktUTDataPin, -- I/O 07 PIN 17
|
||||
IOPortTag & x"04" & PktUARTRTag & PktURDataPin, -- I/O 08 PIN 5
|
||||
IOPortTag & x"05" & PktUARTRTag & PktURDataPin, -- I/O 09 PIN 6
|
||||
IOPortTag & x"06" & PktUARTRTag & PktURDataPin, -- I/O 10 PIN 7
|
||||
IOPortTag & x"07" & PktUARTRTag & PktURDataPin, -- I/O 11 PIN 8
|
||||
IOPortTag & x"04" & PktUARTTTag & PktUTDataPin, -- I/O 12 PIN 9
|
||||
IOPortTag & x"05" & PktUARTTTag & PktUTDataPin, -- I/O 13 PIN 10
|
||||
IOPortTag & x"06" & PktUARTTTag & PktUTDataPin, -- I/O 14 PIN 11
|
||||
IOPortTag & x"07" & PktUARTTTag & PktUTDataPin, -- I/O 15 PIN 12
|
||||
IOPortTag & x"07" & PktUARTTTag & PktUTDrvEnPin, -- I/O 16 PIN 13
|
||||
|
||||
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 17 -- internal 26 pin header
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 18
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 19
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 20
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 21
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 22
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 23
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 24
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 25
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 26
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 27
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 28
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 29
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 30
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 31
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 32
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 33
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_7I74_PKT_34;
|
||||
166
5i24/configs/hostmot2/source/PIN_7I74_SSI_SSx2_34.vhd
Executable file
166
5i24/configs/hostmot2/source/PIN_7I74_SSI_SSx2_34.vhd
Executable file
@@ -0,0 +1,166 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_7I74_SSI_SSx2_34 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(SSSITag, x"00", ClockLowTag, x"08", SSSIDataAddr0&PadT, SSSINumRegs, x"00", SSSIMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin -- P3 DB25
|
||||
IOPortTag & x"00" & SSSITag & SSSIDataPin, -- I/O 00 PIN 1
|
||||
IOPortTag & x"01" & SSSITag & SSSIDataPin, -- I/O 01 PIN 14
|
||||
IOPortTag & x"02" & SSSITag & SSSIDataPin, -- I/O 02 PIN 2
|
||||
IOPortTag & x"03" & SSSITag & SSSIDataPin, -- I/O 03 PIN 15
|
||||
IOPortTag & x"00" & SSSITag & SSSIClkPin, -- I/O 04 PIN 3
|
||||
IOPortTag & x"01" & SSSITag & SSSIClkPin, -- I/O 05 PIN 16
|
||||
IOPortTag & x"02" & SSSITag & SSSIClkPin, -- I/O 06 PIN 4
|
||||
IOPortTag & x"03" & SSSITag & SSSIClkPin, -- I/O 07 PIN 17
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 08 PIN 5
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, -- I/O 09 PIN 6
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX3Pin, -- I/O 10 PIN 7
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX4Pin, -- I/O 11 PIN 8
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 12 PIN 9
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, -- I/O 13 PIN 10
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX3Pin, -- I/O 14 PIN 11
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX4Pin, -- I/O 15 PIN 12
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn4Pin, -- I/O 16 PIN 13
|
||||
|
||||
-- P2 26 HDR DB25
|
||||
IOPortTag & x"04" & SSSITag & SSSIDataPin, -- I/O 17 PIN 1 PIN 1
|
||||
IOPortTag & x"05" & SSSITag & SSSIDataPin, -- I/O 18 PIN 2 PIN 14
|
||||
IOPortTag & x"06" & SSSITag & SSSIDataPin, -- I/O 19 PIN 3 PIN 2
|
||||
IOPortTag & x"07" & SSSITag & SSSIDataPin, -- I/O 20 PIN 4 PIN 15
|
||||
IOPortTag & x"04" & SSSITag & SSSIClkPin, -- I/O 21 PIN 5 PIN 3
|
||||
IOPortTag & x"05" & SSSITag & SSSIClkPin, -- I/O 22 PIN 6 PIN 16
|
||||
IOPortTag & x"06" & SSSITag & SSSIClkPin, -- I/O 23 PIN 7 PIN 4
|
||||
IOPortTag & x"07" & SSSITag & SSSIClkPin, -- I/O 24 PIN 8 PIN 17
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX5Pin, -- I/O 25 PIN 9 PIN 5
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX6Pin, -- I/O 26 PIN 11 PIN 6
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX7Pin, -- I/O 27 PIN 13 PIN 7
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX8Pin, -- I/O 28 PIN 15 PIN 8
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX5Pin, -- I/O 29 PIN 17 PIN 9
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX6Pin, -- I/O 30 PIN 19 PIN 10
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX7Pin, -- I/O 31 PIN 21 PIN 11
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX8Pin, -- I/O 32 PIN 23 PIN 12
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn8Pin, -- I/O 33 PIN 25 PIN 13
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_7I74_SSI_SSx2_34;
|
||||
166
5i24/configs/hostmot2/source/PIN_7I74x1_4_4D_34.vhd
Executable file
166
5i24/configs/hostmot2/source/PIN_7I74x1_4_4D_34.vhd
Executable file
@@ -0,0 +1,166 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_7I74x1_4_4D_34 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"02", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin -- P1 HDR
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 00 PIN 1
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 01 PIN 14
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, -- I/O 02 PIN 2
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX3Pin, -- I/O 03 PIN 15
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 04 PIN 3
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 05 PIN 16
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, -- I/O 06 PIN 4
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX3Pin, -- I/O 07 PIN 17
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX0Pin, -- I/O 08 PIN 5
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX1Pin, -- I/O 09 PIN 6
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX2Pin, -- I/O 10 PIN 7
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX3Pin, -- I/O 11 PIN 8
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX0Pin, -- I/O 12 PIN 9
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX1Pin, -- I/O 13 PIN 10
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX2Pin, -- I/O 14 PIN 11
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX3Pin, -- I/O 15 PIN 12
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTXEn3Pin, -- I/O 16 PIN 13
|
||||
|
||||
-- P2 26 HDR DB25
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 17 PIN 1 PIN 1
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 18 PIN 2 PIN 14
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 19 PIN 3 PIN 2
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 20 PIN 4 PIN 15
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 21 PIN 5 PIN 3
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 22 PIN 6 PIN 16
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 23 PIN 7 PIN 4
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 24 PIN 8 PIN 17
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 25 PIN 9 PIN 5
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 26 PIN 11 PIN 6
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 27 PIN 13 PIN 7
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 28 PIN 15 PIN 8
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 29 PIN 17 PIN 9
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 30 PIN 19 PIN 10
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 31 PIN 21 PIN 11
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 32 PIN 23 PIN 12
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 33 PIN 25 PIN 13
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_7I74x1_4_4D_34;
|
||||
166
5i24/configs/hostmot2/source/PIN_7I74x2_34.vhd
Executable file
166
5i24/configs/hostmot2/source/PIN_7I74x2_34.vhd
Executable file
@@ -0,0 +1,166 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_7I74x2_34 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"02", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin -- P3 DB25
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 00 PIN 1
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 01 PIN 14
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, -- I/O 02 PIN 2
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX3Pin, -- I/O 03 PIN 15
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 04 PIN 3
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 05 PIN 16
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, -- I/O 06 PIN 4
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX3Pin, -- I/O 07 PIN 17
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX4Pin, -- I/O 08 PIN 5
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX5Pin, -- I/O 09 PIN 6
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX6Pin, -- I/O 10 PIN 7
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX7Pin, -- I/O 11 PIN 8
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX4Pin, -- I/O 12 PIN 9
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX5Pin, -- I/O 13 PIN 10
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX6Pin, -- I/O 14 PIN 11
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX7Pin, -- I/O 15 PIN 12
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn7Pin, -- I/O 16 PIN 13
|
||||
|
||||
-- P2 26 HDR DB25
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX0Pin, -- I/O 17 PIN 1 PIN 1
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX1Pin, -- I/O 18 PIN 2 PIN 14
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX2Pin, -- I/O 19 PIN 3 PIN 2
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX3Pin, -- I/O 20 PIN 4 PIN 15
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX0Pin, -- I/O 21 PIN 5 PIN 3
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX1Pin, -- I/O 22 PIN 6 PIN 16
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX2Pin, -- I/O 23 PIN 7 PIN 4
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX3Pin, -- I/O 24 PIN 8 PIN 17
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX4Pin, -- I/O 25 PIN 9 PIN 5
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX5Pin, -- I/O 26 PIN 11 PIN 6
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX6Pin, -- I/O 27 PIN 13 PIN 7
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX7Pin, -- I/O 28 PIN 15 PIN 8
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX4Pin, -- I/O 29 PIN 17 PIN 9
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX5Pin, -- I/O 30 PIN 19 PIN 10
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX6Pin, -- I/O 31 PIN 21 PIN 11
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX7Pin, -- I/O 32 PIN 23 PIN 12
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTXEn7Pin, -- I/O 33 PIN 25 PIN 13
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_7I74x2_34;
|
||||
198
5i24/configs/hostmot2/source/PIN_7I74x4_68.vhd
Executable file
198
5i24/configs/hostmot2/source/PIN_7I74x4_68.vhd
Executable file
@@ -0,0 +1,198 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_7I74x4_68 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"04", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"04", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
|
||||
-- Base func sec unit sec func sec pin -- P3 DB25
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 00 PIN 1
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 01 PIN 14
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, -- I/O 02 PIN 2
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX3Pin, -- I/O 03 PIN 15
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 04 PIN 3
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 05 PIN 16
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, -- I/O 06 PIN 4
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX3Pin, -- I/O 07 PIN 17
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX4Pin, -- I/O 08 PIN 5
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX5Pin, -- I/O 09 PIN 6
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX6Pin, -- I/O 10 PIN 7
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX7Pin, -- I/O 11 PIN 8
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX4Pin, -- I/O 12 PIN 9
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX5Pin, -- I/O 13 PIN 10
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX6Pin, -- I/O 14 PIN 11
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX7Pin, -- I/O 15 PIN 12
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEn7Pin, -- I/O 16 PIN 13
|
||||
|
||||
-- Base func sec unit sec func sec pin -- P3 DB25
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX0Pin, -- I/O 00 PIN 1
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX1Pin, -- I/O 01 PIN 14
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX2Pin, -- I/O 02 PIN 2
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX3Pin, -- I/O 03 PIN 15
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX0Pin, -- I/O 04 PIN 3
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX1Pin, -- I/O 05 PIN 16
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX2Pin, -- I/O 06 PIN 4
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX3Pin, -- I/O 07 PIN 17
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX4Pin, -- I/O 08 PIN 5
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX5Pin, -- I/O 09 PIN 6
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX6Pin, -- I/O 10 PIN 7
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX7Pin, -- I/O 11 PIN 8
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX4Pin, -- I/O 12 PIN 9
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX5Pin, -- I/O 13 PIN 10
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX6Pin, -- I/O 14 PIN 11
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX7Pin, -- I/O 15 PIN 12
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTXEn7Pin, -- I/O 16 PIN 13
|
||||
|
||||
-- Base func sec unit sec func sec pin -- P3 DB25
|
||||
IOPortTag & x"02" & SSerialTag & SSerialRX0Pin, -- I/O 00 PIN 1
|
||||
IOPortTag & x"02" & SSerialTag & SSerialRX1Pin, -- I/O 01 PIN 14
|
||||
IOPortTag & x"02" & SSerialTag & SSerialRX2Pin, -- I/O 02 PIN 2
|
||||
IOPortTag & x"02" & SSerialTag & SSerialRX3Pin, -- I/O 03 PIN 15
|
||||
IOPortTag & x"02" & SSerialTag & SSerialTX0Pin, -- I/O 04 PIN 3
|
||||
IOPortTag & x"02" & SSerialTag & SSerialTX1Pin, -- I/O 05 PIN 16
|
||||
IOPortTag & x"02" & SSerialTag & SSerialTX2Pin, -- I/O 06 PIN 4
|
||||
IOPortTag & x"02" & SSerialTag & SSerialTX3Pin, -- I/O 07 PIN 17
|
||||
IOPortTag & x"02" & SSerialTag & SSerialRX4Pin, -- I/O 08 PIN 5
|
||||
IOPortTag & x"02" & SSerialTag & SSerialRX5Pin, -- I/O 09 PIN 6
|
||||
IOPortTag & x"02" & SSerialTag & SSerialRX6Pin, -- I/O 10 PIN 7
|
||||
IOPortTag & x"02" & SSerialTag & SSerialRX7Pin, -- I/O 11 PIN 8
|
||||
IOPortTag & x"02" & SSerialTag & SSerialTX4Pin, -- I/O 12 PIN 9
|
||||
IOPortTag & x"02" & SSerialTag & SSerialTX5Pin, -- I/O 13 PIN 10
|
||||
IOPortTag & x"02" & SSerialTag & SSerialTX6Pin, -- I/O 14 PIN 11
|
||||
IOPortTag & x"02" & SSerialTag & SSerialTX7Pin, -- I/O 15 PIN 12
|
||||
IOPortTag & x"02" & SSerialTag & SSerialTXEn7Pin, -- I/O 16 PIN 13
|
||||
|
||||
-- Base func sec unit sec func sec pin -- P3 DB25
|
||||
IOPortTag & x"03" & SSerialTag & SSerialRX0Pin, -- I/O 00 PIN 1
|
||||
IOPortTag & x"03" & SSerialTag & SSerialRX1Pin, -- I/O 01 PIN 14
|
||||
IOPortTag & x"03" & SSerialTag & SSerialRX2Pin, -- I/O 02 PIN 2
|
||||
IOPortTag & x"03" & SSerialTag & SSerialRX3Pin, -- I/O 03 PIN 15
|
||||
IOPortTag & x"03" & SSerialTag & SSerialTX0Pin, -- I/O 04 PIN 3
|
||||
IOPortTag & x"03" & SSerialTag & SSerialTX1Pin, -- I/O 05 PIN 16
|
||||
IOPortTag & x"03" & SSerialTag & SSerialTX2Pin, -- I/O 06 PIN 4
|
||||
IOPortTag & x"03" & SSerialTag & SSerialTX3Pin, -- I/O 07 PIN 17
|
||||
IOPortTag & x"03" & SSerialTag & SSerialRX4Pin, -- I/O 08 PIN 5
|
||||
IOPortTag & x"03" & SSerialTag & SSerialRX5Pin, -- I/O 09 PIN 6
|
||||
IOPortTag & x"03" & SSerialTag & SSerialRX6Pin, -- I/O 10 PIN 7
|
||||
IOPortTag & x"03" & SSerialTag & SSerialRX7Pin, -- I/O 11 PIN 8
|
||||
IOPortTag & x"03" & SSerialTag & SSerialTX4Pin, -- I/O 12 PIN 9
|
||||
IOPortTag & x"03" & SSerialTag & SSerialTX5Pin, -- I/O 13 PIN 10
|
||||
IOPortTag & x"03" & SSerialTag & SSerialTX6Pin, -- I/O 14 PIN 11
|
||||
IOPortTag & x"03" & SSerialTag & SSerialTX7Pin, -- I/O 15 PIN 12
|
||||
IOPortTag & x"03" & SSerialTag & SSerialTXEn7Pin, -- I/O 16 PIN 13
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_7I74x4_68;
|
||||
181
5i24/configs/hostmot2/source/PIN_7I76E_51.vhd
Executable file
181
5i24/configs/hostmot2/source/PIN_7I76E_51.vhd
Executable file
@@ -0,0 +1,181 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_7I76E_51 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"03", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"05", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"01", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
|
||||
-- Base func sec unit sec func sec pin
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 00 embedded 7I76
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 01
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 02
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 03
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 04
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 05
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 06
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 07
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 08
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 09
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 10
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 11
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 12
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 13
|
||||
IOPortTag & x"00" & QCountTag & x"03", -- I/O 14
|
||||
IOPortTag & x"00" & QCountTag & x"02", -- I/O 15
|
||||
IOPortTag & x"00" & QCountTag & x"01", -- I/O 16
|
||||
|
||||
-- P1 DB25
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 17 PIN 1
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 18 PIN 14
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 19 PIN 2
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 20 PIN 15
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 21 PIN 3
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 22 PIN 16
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 23 PIN 4
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 24 PIN 17
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 25 PIN 5
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 26 PIN 6
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 27 PIN 7
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 28 PIN 8
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 29 PIN 9
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 30 PIN 10
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 31 PIN 11
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 32 PIN 12
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 33 PIN 13
|
||||
-- P2
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 34 PIN 1
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 35 PIN 14
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 36 PIN 2
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 37 PIN 15
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 38 PIN 3
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 39 PIN 16
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 40 PIN 4
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 41 PIN 17
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 42 PIN 5
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 43 PIN 6
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 44 PIN 7
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 45 PIN 8
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 46 PIN 9
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 47 PIN 10
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 48 PIN 11
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 49 PIN 12
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 50 PIN 13
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_7I76E_51;
|
||||
166
5i24/configs/hostmot2/source/PIN_7I76P_7I76_34.vhd
Executable file
166
5i24/configs/hostmot2/source/PIN_7I76P_7I76_34.vhd
Executable file
@@ -0,0 +1,166 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_7I76P_7I76_34 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"02", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(PWMTag, x"00", ClockHighTag, x"05", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"0A", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin -- external DB25
|
||||
IOPortTag & x"00" & PWMTag & PWMBDirPin, -- I/O 00 PIN 1
|
||||
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 01 PIN 14
|
||||
IOPortTag & x"01" & PWMTag & PWMBDirPin, -- I/O 02 PIN 2
|
||||
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 03 PIN 15
|
||||
IOPortTag & x"02" & PWMTag & PWMBDirPin, -- I/O 04 PIN 3
|
||||
IOPortTag & x"02" & PWMTag & PWMAOutPin, -- I/O 05 PIN 16
|
||||
IOPortTag & x"03" & PWMTag & PWMBDirPin, -- I/O 06 PIN 4
|
||||
IOPortTag & x"03" & PWMTag & PWMAOutPin, -- I/O 07 PIN 17
|
||||
IOPortTag & x"04" & PWMTag & PWMBDirPin, -- I/O 08 PIN 5
|
||||
IOPortTag & x"04" & PWMTag & PWMAOutPin, -- I/O 09 PIN 6
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 10 PIN 7
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 11 PIN 8
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 12 PIN 9
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 13 PIN 10
|
||||
IOPortTag & x"00" & QCountTag & x"03", -- I/O 14 PIN 11
|
||||
IOPortTag & x"00" & QCountTag & x"02", -- I/O 15 PIN 12
|
||||
IOPortTag & x"00" & QCountTag & x"01", -- I/O 16 PIN 13
|
||||
|
||||
-- 26 HDR -- IDC DB25
|
||||
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 17 PIN 1 PIN 1
|
||||
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 18 PIN 2 PIN 14
|
||||
IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 19 PIN 3 PIN 2
|
||||
IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 20 PIN 4 PIN 15
|
||||
IOPortTag & x"07" & StepGenTag & StepGenDirPin, -- I/O 21 PIN 5 PIN 3
|
||||
IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 22 PIN 6 PIN 16
|
||||
IOPortTag & x"08" & StepGenTag & StepGenDirPin, -- I/O 23 PIN 7 PIN 4
|
||||
IOPortTag & x"08" & StepGenTag & StepGenStepPin, -- I/O 24 PIN 8 PIN 17
|
||||
IOPortTag & x"09" & StepGenTag & StepGenDirPin, -- I/O 25 PIN 9 PIN 5
|
||||
IOPortTag & x"09" & StepGenTag & StepGenStepPin, -- I/O 26 PIN 11 PIN 6
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, -- I/O 27 PIN 13 PIN 7
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, -- I/O 28 PIN 15 PIN 8
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX3Pin, -- I/O 29 PIN 17 PIN 9
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX3Pin, -- I/O 30 PIN 19 PIN 10
|
||||
IOPortTag & x"01" & QCountTag & x"03", -- I/O 31 PIN 21 PIN 11
|
||||
IOPortTag & x"01" & QCountTag & x"02", -- I/O 32 PIN 23 PIN 12
|
||||
IOPortTag & x"01" & QCountTag & x"01", -- I/O 33 PIN 25 PIN 13
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_7I76P_7I76_34;
|
||||
166
5i24/configs/hostmot2/source/PIN_7I76P_7I85_34.vhd
Executable file
166
5i24/configs/hostmot2/source/PIN_7I76P_7I85_34.vhd
Executable file
@@ -0,0 +1,166 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_7I76P_7I85_34 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(MuxedQcountTag, MQCRev, ClockLowTag, x"06", MuxedQcounterAddr&PadT, MuxedQCounterNumRegs,x"00", MuxedQCounterMPBitMask),
|
||||
(MuxedQCountSelTag, x"00", ClockLowTag, x"01", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(PWMTag, x"00", ClockHighTag, x"05", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin -- external DB25
|
||||
IOPortTag & x"00" & PWMTag & PWMBDirPin, -- I/O 00 PIN 1
|
||||
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 01 PIN 14
|
||||
IOPortTag & x"01" & PWMTag & PWMBDirPin, -- I/O 02 PIN 2
|
||||
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 03 PIN 15
|
||||
IOPortTag & x"02" & PWMTag & PWMBDirPin, -- I/O 04 PIN 3
|
||||
IOPortTag & x"02" & PWMTag & PWMAOutPin, -- I/O 05 PIN 16
|
||||
IOPortTag & x"03" & PWMTag & PWMBDirPin, -- I/O 06 PIN 4
|
||||
IOPortTag & x"03" & PWMTag & PWMAOutPin, -- I/O 07 PIN 17
|
||||
IOPortTag & x"04" & PWMTag & PWMBDirPin, -- I/O 08 PIN 5
|
||||
IOPortTag & x"04" & PWMTag & PWMAOutPin, -- I/O 09 PIN 6
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 10 PIN 7
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 11 PIN 8
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 12 PIN 9
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 13 PIN 10
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 14 PIN 11
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 15 PIN 12
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 16 PIN 13
|
||||
|
||||
-- 26 HDR -- IDC DB25
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX6Pin, -- I/O 00 PIN 1 PIN 1
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX6Pin, -- I/O 01 PIN 14 PIN 2
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX5Pin, -- I/O 02 PIN 2 PIN 3
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX5Pin, -- I/O 03 PIN 15 PIN 4
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX4Pin, -- I/O 04 PIN 3 PIN 5
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX4Pin, -- I/O 05 PIN 16 PIN 6
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX3Pin, -- I/O 06 PIN 4 PIN 7
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX3Pin, -- I/O 07 PIN 17 PIN 8
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, -- I/O 08 PIN 5 PIN 9
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, -- I/O 09 PIN 6 PIN 11
|
||||
IOPortTag & x"01" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 10 PIN 7 PIN 13
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 11 PIN 8 PIN 15
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 12 PIN 9 PIN 17
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 13 PIN 10 PIN 19
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 14 PIN 11 PIN 21
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 15 PIN 12 PIN 23
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 16 PIN 13 PIN 25
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_7I76P_7I85_34;
|
||||
166
5i24/configs/hostmot2/source/PIN_7I76XY2Modx1D_34.vhd
Executable file
166
5i24/configs/hostmot2/source/PIN_7I76XY2Modx1D_34.vhd
Executable file
@@ -0,0 +1,166 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_7I76XY2Modx1D_34 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"01", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"03", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(XY2ModTag, x"00", ClockLowTag, x"01", XY2ModAccelXAddr&PadT, XY2ModNumRegs, x"00", XY2ModMPBitMask ),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin -- external DB25
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 00 PIN 1
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 01 PIN 14
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 02 PIN 2
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 03 PIN 15
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 04 PIN 3
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 05 PIN 16
|
||||
IOPortTag & x"00" & XY2ModTag & XY2ModDataXPin, -- I/O 06 PIN 4
|
||||
IOPortTag & x"00" & XY2ModTag & XY2ModDataYPin, -- I/O 07 PIN 17
|
||||
IOPortTag & x"00" & XY2ModTag & XY2ModDataClkPin, -- I/O 08 PIN 5
|
||||
IOPortTag & x"00" & XY2ModTag & XY2ModSyncPin, -- I/O 09 PIN 6
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 10 PIN 7
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 11 PIN 8
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 12 PIN 9
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 13 PIN 10
|
||||
IOPortTag & x"00" & XY2ModTag & XY2ModStatusPin, -- I/O 14 PIN 11
|
||||
IOPortTag & x"00" & QCountTag & x"02", -- I/O 15 PIN 12
|
||||
IOPortTag & x"00" & QCountTag & x"01", -- I/O 16 PIN 13
|
||||
|
||||
-- 26 HDR IDC DB25
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 17 PIN 1 PIN 1
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 18 PIN 2 PIN 14
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 19 PIN 3 PIN 2
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 20 PIN 4 PIN 15
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 21 PIN 5 PIN 3
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 22 PIN 6 PIN 16
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 23 PIN 7 PIN 4
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 24 PIN 8 PIN 17
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 25 PIN 9 PIN 5
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 26 PIN 11 PIN 6
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 27 PIN 13 PIN 7
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 28 PIN 15 PIN 8
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 29 PIN 17 PIN 9
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 30 PIN 19 PIN 10
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 31 PIN 21 PIN 11
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 32 PIN 23 PIN 12
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 33 PIN 25 PIN 13
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_7I76XY2Modx1D_34;
|
||||
166
5i24/configs/hostmot2/source/PIN_7I76XY2Modx2D_34.vhd
Executable file
166
5i24/configs/hostmot2/source/PIN_7I76XY2Modx2D_34.vhd
Executable file
@@ -0,0 +1,166 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_7I76XY2Modx2D_34 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"02", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"0A", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(XY2ModTag, x"00", ClockLowTag, x"02", XY2ModAccelXAddr&PadT, XY2ModNumRegs, x"00", XY2ModMPBitMask ),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin -- external DB25
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 00 PIN 1
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 01 PIN 14
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 02 PIN 2
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 03 PIN 15
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 04 PIN 3
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 05 PIN 16
|
||||
IOPortTag & x"00" & XY2ModTag & XY2ModDataXPin, -- I/O 06 PIN 4
|
||||
IOPortTag & x"00" & XY2ModTag & XY2ModDataYPin, -- I/O 07 PIN 17
|
||||
IOPortTag & x"00" & XY2ModTag & XY2ModDataClkPin, -- I/O 08 PIN 5
|
||||
IOPortTag & x"00" & XY2ModTag & XY2ModSyncPin, -- I/O 09 PIN 6
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 10 PIN 7
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 11 PIN 8
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 12 PIN 9
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 13 PIN 10
|
||||
IOPortTag & x"00" & XY2ModTag & XY2ModStatusPin, -- I/O 14 PIN 11
|
||||
IOPortTag & x"00" & QCountTag & x"02", -- I/O 15 PIN 12
|
||||
IOPortTag & x"00" & QCountTag & x"01", -- I/O 16 PIN 13
|
||||
|
||||
-- 26 HDR -- IDC DB25
|
||||
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 17 PIN 1 PIN 1
|
||||
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 18 PIN 2 PIN 14
|
||||
IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 19 PIN 3 PIN 2
|
||||
IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 20 PIN 4 PIN 15
|
||||
IOPortTag & x"07" & StepGenTag & StepGenDirPin, -- I/O 21 PIN 5 PIN 3
|
||||
IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 22 PIN 6 PIN 16
|
||||
IOPortTag & x"01" & XY2ModTag & XY2ModDataXPin, -- I/O 23 PIN 7 PIN 4
|
||||
IOPortTag & x"01" & XY2ModTag & XY2ModDataYPin, -- I/O 24 PIN 8 PIN 17
|
||||
IOPortTag & x"01" & XY2ModTag & XY2ModDataClkPin, -- I/O 25 PIN 9 PIN 5
|
||||
IOPortTag & x"01" & XY2ModTag & XY2ModSyncPin, -- I/O 26 PIN 11 PIN 6
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, -- I/O 27 PIN 13 PIN 7
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, -- I/O 28 PIN 15 PIN 8
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX3Pin, -- I/O 29 PIN 17 PIN 9
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX3Pin, -- I/O 30 PIN 19 PIN 10
|
||||
IOPortTag & x"01" & XY2ModTag & XY2ModStatusPin, -- I/O 31 PIN 21 PIN 11
|
||||
IOPortTag & x"01" & QCountTag & x"02", -- I/O 32 PIN 23 PIN 12
|
||||
IOPortTag & x"01" & QCountTag & x"01", -- I/O 33 PIN 25 PIN 13
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_7I76XY2Modx2D_34;
|
||||
166
5i24/configs/hostmot2/source/PIN_7I76_2P_7I77D_34.vhd
Executable file
166
5i24/configs/hostmot2/source/PIN_7I76_2P_7I77D_34.vhd
Executable file
@@ -0,0 +1,166 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_7I76_2P_7I77D_34 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(MuxedQcountTag, MQCRev, ClockLowTag, x"08", MuxedQcounterAddr&PadT, MuxedQCounterNumRegs,x"00", MuxedQCounterMPBitMask),
|
||||
(MuxedQCountSelTag, x"00", ClockLowTag, x"01", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(PWMTag, x"00", ClockHighTag, x"02", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"04", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin -- P3 DB25
|
||||
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 0 PIN 1
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 1 PIN 14
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 2 PIN 2
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 3 PIN 15
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 4 PIN 3
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 5 PIN 16
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 6 PIN 4
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 7 PIN 17
|
||||
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 8 PIN 5
|
||||
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 9 PIN 6
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 10 PIN 7
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 11 PIN 8
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 12 PIN 9
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 13 PIN 10
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 14 PIN 11
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 15 PIN 12
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 16 PIN 13
|
||||
-- P2 26 HDR DB25
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEN4Pin, -- I/O 17 PIN 1 PIN 1
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX4Pin, -- I/O 18 PIN 2 PIN 14
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX4Pin, -- I/O 19 PIN 3 PIN 2
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX3Pin, -- I/O 20 PIN 4 PIN 15
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX3Pin, -- I/O 21 PIN 5 PIN 3
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, -- I/O 22 PIN 6 PIN 16
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, -- I/O 23 PIN 7 PIN 4
|
||||
IOPortTag & x"00" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 24 PIN 8 PIN 17
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 25 PIN 9 PIN 5
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 26 PIN 11 PIN 6
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 27 PIN 13 PIN 7
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 28 PIN 15 PIN 8
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 29 PIN 17 PIN 9
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 30 PIN 19 PIN 10
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 31 PIN 21 PIN 11
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 32 PIN 23 PIN 12
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 33 PIN 25 PIN 13
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_7I76_2P_7I77D_34;
|
||||
166
5i24/configs/hostmot2/source/PIN_7I76_2Px2D_34.vhd
Executable file
166
5i24/configs/hostmot2/source/PIN_7I76_2Px2D_34.vhd
Executable file
@@ -0,0 +1,166 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_7I76_2Px2D_34 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(PWMTag, x"00", ClockHighTag, x"04", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"02", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"08", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin -- external DB25
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 00 PIN 1
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 01 PIN 14
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 02 PIN 2
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 03 PIN 15
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 04 PIN 3
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 05 PIN 16
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 06 PIN 4
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 07 PIN 17
|
||||
IOPortTag & x"01" & PWMTag & PWMAOutPin, -- I/O 08 PIN 5
|
||||
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 09 PIN 6
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 10 PIN 7
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 11 PIN 8
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 12 PIN 9
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 13 PIN 10
|
||||
IOPortTag & x"00" & QCountTag & x"03", -- I/O 14 PIN 11
|
||||
IOPortTag & x"00" & QCountTag & x"02", -- I/O 15 PIN 12
|
||||
IOPortTag & x"00" & QCountTag & x"01", -- I/O 16 PIN 13
|
||||
|
||||
-- 26 HDR -- IDC DB25
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 17 PIN 1 PIN 1
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 18 PIN 2 PIN 14
|
||||
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 19 PIN 3 PIN 2
|
||||
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 20 PIN 4 PIN 15
|
||||
IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 21 PIN 5 PIN 3
|
||||
IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 22 PIN 6 PIN 16
|
||||
IOPortTag & x"07" & StepGenTag & StepGenDirPin, -- I/O 23 PIN 7 PIN 4
|
||||
IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 24 PIN 8 PIN 17
|
||||
IOPortTag & x"03" & PWMTag & PWMAOutPin, -- I/O 25 PIN 9 PIN 5
|
||||
IOPortTag & x"02" & PWMTag & PWMAOutPin, -- I/O 26 PIN 11 PIN 6
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, -- I/O 27 PIN 13 PIN 7
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, -- I/O 28 PIN 15 PIN 8
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX3Pin, -- I/O 29 PIN 17 PIN 9
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX3Pin, -- I/O 30 PIN 19 PIN 10
|
||||
IOPortTag & x"01" & QCountTag & x"03", -- I/O 31 PIN 21 PIN 11
|
||||
IOPortTag & x"01" & QCountTag & x"02", -- I/O 32 PIN 23 PIN 12
|
||||
IOPortTag & x"01" & QCountTag & x"01", -- I/O 33 PIN 25 PIN 13
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_7I76_2Px2D_34;
|
||||
166
5i24/configs/hostmot2/source/PIN_7I76_34.vhd
Executable file
166
5i24/configs/hostmot2/source/PIN_7I76_34.vhd
Executable file
@@ -0,0 +1,166 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_7I76_34 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"01", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"05", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 00 -- I/O 00 PIN 1-- external DB25
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 01 -- I/O 01 PIN 14
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 02 -- I/O 02 PIN 2
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 03 -- I/O 03 PIN 15
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 04 -- I/O 04 PIN 3
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 05 -- I/O 05 PIN 16
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 06 -- I/O 06 PIN 4
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 07 -- I/O 07 PIN 17
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 08 -- I/O 08 PIN 5
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 09 -- I/O 09 PIN 6
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 10 -- I/O 10 PIN 7
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 11 -- I/O 11 PIN 8
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 12 -- I/O 12 PIN 9
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 13 -- I/O 13 PIN 10
|
||||
IOPortTag & x"00" & QCountTag & x"01", -- I/O 14 -- I/O 14 PIN 11
|
||||
IOPortTag & x"00" & QCountTag & x"02", -- I/O 15 -- I/O 15 PIN 12
|
||||
IOPortTag & x"00" & QCountTag & x"03", -- I/O 16 -- I/O 16 PIN 13
|
||||
|
||||
-- 26 HDR -- IDC DB25
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 17 PIN 1 PIN 1
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 18 PIN 2 PIN 14
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 19 PIN 3 PIN 2
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 20 PIN 4 PIN 15
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 21 PIN 5 PIN 3
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 22 PIN 6 PIN 16
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 23 PIN 7 PIN 4
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 24 PIN 8 PIN 17
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 25 PIN 9 PIN 5
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 26 PIN 11 PIN 6
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 27 PIN 13 PIN 7
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 28 PIN 15 PIN 8
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 29 PIN 17 PIN 9
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 30 PIN 19 PIN 10
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 31 PIN 21 PIN 11
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 32 PIN 23 PIN 12
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 33 PIN 25 PIN 13
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_7I76_34;
|
||||
167
5i24/configs/hostmot2/source/PIN_7I76_5ABOB_34.vhd
Executable file
167
5i24/configs/hostmot2/source/PIN_7I76_5ABOB_34.vhd
Executable file
@@ -0,0 +1,167 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_7I76_5ABOB_34 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(PWMTag, x"00", ClockHighTag, x"01", PWMValAddr&PadT, PWMNumRegs, x"00", PWMMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"02", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"0A", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin -- external DB25 7I76 pinout
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 00 PIN 1
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 01 PIN 14
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 02 PIN 2
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 03 PIN 15
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 04 PIN 3
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 05 PIN 16
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 06 PIN 4
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 07 PIN 17
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 08 PIN 5
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 09 PIN 6
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 10 PIN 7
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 11 PIN 8
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 12 PIN 9
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 13 PIN 10
|
||||
IOPortTag & x"00" & QCountTag & x"03", -- I/O 14 PIN 11
|
||||
IOPortTag & x"00" & QCountTag & x"02", -- I/O 15 PIN 12
|
||||
IOPortTag & x"00" & QCountTag & x"01", -- I/O 16 PIN 13
|
||||
|
||||
-- 5ABOB pinout
|
||||
-- 26 HDR -- IDC DB25
|
||||
IOPortTag & x"00" & PWMTag & PWMAOutPin, -- I/O 17 PIN 1 PIN 1 Spindle DAC PWM
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 18 PIN 2 PIN 14 just GPIO
|
||||
IOPortTag & x"05" & StepGenTag & StepGenStepPin, -- I/O 19 PIN 3 PIN 2 X2 Dir
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 20 PIN 4 PIN 15 just GPIO
|
||||
IOPortTag & x"05" & StepGenTag & StepGenDirPin, -- I/O 21 PIN 5 PIN 3 X2 Step
|
||||
IOPortTag & x"09" & StepGenTag & StepGenStepPin, -- I/O 22 PIN 6 PIN 16 B2 Step
|
||||
IOPortTag & x"06" & StepGenTag & StepGenStepPin, -- I/O 23 PIN 7 PIN 4 Y2 Dir
|
||||
IOPortTag & x"09" & StepGenTag & StepGenDirPin, -- I/O 24 PIN 8 PIN 17 B2 Dir
|
||||
IOPortTag & x"06" & StepGenTag & StepGenDirPin, -- I/O 25 PIN 9 PIN 5 Y2 Step
|
||||
IOPortTag & x"07" & StepGenTag & StepGenStepPin, -- I/O 26 PIN 11 PIN 6 Z2 Dir
|
||||
IOPortTag & x"07" & StepGenTag & StepGenDirPin, -- I/O 27 PIN 13 PIN 7 Z2 Step
|
||||
IOPortTag & x"08" & StepGenTag & StepGenStepPin, -- I/O 28 PIN 15 PIN 8 A2 Dir
|
||||
IOPortTag & x"08" & StepGenTag & StepGenDIrPin, -- I/O 29 PIN 17 PIN 9 A2 Step
|
||||
IOPortTag & x"00" & NullTag & NullPin, -- I/O 30 PIN 19 PIN 10 just GPIO
|
||||
IOPortTag & x"01" & QCountTag & QCountQAPin, -- I/O 31 PIN 21 PIN 11 Input 2 (Quad A)
|
||||
IOPortTag & x"01" & QCountTag & QCountQBPin, -- I/O 32 PIN 23 PIN 12 Input 3 (Quad B))
|
||||
IOPortTag & x"01" & QCountTag & QCountIdxPin, -- I/O 33 PIN 25 PIN 13 Input 4 (Quad Idx)
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_7I76_5ABOB_34;
|
||||
166
5i24/configs/hostmot2/source/PIN_7I76_7I74D_34.vhd
Executable file
166
5i24/configs/hostmot2/source/PIN_7I76_7I74D_34.vhd
Executable file
@@ -0,0 +1,166 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_7I76_7I74D_34 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"01", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"02", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"05", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin -- external DB25
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 00 PIN 1
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 01 PIN 14
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 02 PIN 2
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 03 PIN 15
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 04 PIN 3
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 05 PIN 16
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 06 PIN 4
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 07 PIN 17
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 08 PIN 5
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 09 PIN 6
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 10 PIN 7
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 11 PIN 8
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 12 PIN 9
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 13 PIN 10
|
||||
IOPortTag & x"00" & QCountTag & x"03", -- I/O 14 PIN 11
|
||||
IOPortTag & x"00" & QCountTag & x"02", -- I/O 15 PIN 12
|
||||
IOPortTag & x"00" & QCountTag & x"01", -- I/O 16 PIN 13
|
||||
|
||||
-- 26 HDR -- IDC DB25
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX0Pin, -- I/O 17 PIN 1 PIN 1
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX1Pin, -- I/O 18 PIN 2 PIN 14
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX2Pin, -- I/O 19 PIN 3 PIN 2
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX3Pin, -- I/O 20 PIN 4 PIN 15
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX0Pin, -- I/O 21 PIN 5 PIN 3
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX1Pin, -- I/O 22 PIN 6 PIN 16
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX2Pin, -- I/O 23 PIN 7 PIN 4
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX3Pin, -- I/O 24 PIN 8 PIN 17
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX4Pin, -- I/O 25 PIN 9 PIN 5
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX5Pin, -- I/O 26 PIN 11 PIN 6
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX6Pin, -- I/O 27 PIN 13 PIN 7
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX7Pin, -- I/O 28 PIN 15 PIN 8
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX4Pin, -- I/O 29 PIN 17 PIN 9
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX5Pin, -- I/O 30 PIN 19 PIN 10
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX6Pin, -- I/O 31 PIN 21 PIN 11
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX7Pin, -- I/O 32 PIN 23 PIN 12
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTXEn7Pin, -- I/O 33 PIN 25 PIN 13
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_7I76_7I74D_34;
|
||||
166
5i24/configs/hostmot2/source/PIN_7I76_7I74D_6SS_34.vhd
Executable file
166
5i24/configs/hostmot2/source/PIN_7I76_7I74D_6SS_34.vhd
Executable file
@@ -0,0 +1,166 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_7I76_7I74D_SS6_34 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"01", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"05", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin -- external DB25
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 00 PIN 1
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 01 PIN 14
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 02 PIN 2
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 03 PIN 15
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 04 PIN 3
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 05 PIN 16
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 06 PIN 4
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 07 PIN 17
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 08 PIN 5
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 09 PIN 6
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 10 PIN 7
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 11 PIN 8
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 12 PIN 9
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 13 PIN 10
|
||||
IOPortTag & x"00" & QCountTag & x"03", -- I/O 14 PIN 11
|
||||
IOPortTag & x"00" & QCountTag & x"02", -- I/O 15 PIN 12
|
||||
IOPortTag & x"00" & QCountTag & x"01", -- I/O 16 PIN 13
|
||||
|
||||
-- 26 HDR -- IDC DB25
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, -- I/O 17 PIN 1 PIN 1
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX3Pin, -- I/O 18 PIN 2 PIN 14
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX4Pin, -- I/O 19 PIN 3 PIN 2
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX5Pin, -- I/O 20 PIN 4 PIN 15
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, -- I/O 21 PIN 5 PIN 3
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX3Pin, -- I/O 22 PIN 6 PIN 16
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX4Pin, -- I/O 23 PIN 7 PIN 4
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX5Pin, -- I/O 24 PIN 8 PIN 17
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX6Pin, -- I/O 25 PIN 9 PIN 5
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX7Pin, -- I/O 26 PIN 11 PIN 6
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 27 PIN 13 PIN 7
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 28 PIN 15 PIN 8
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX6Pin, -- I/O 29 PIN 17 PIN 9
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX7Pin, -- I/O 30 PIN 19 PIN 10
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 31 PIN 21 PIN 11
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 32 PIN 23 PIN 12
|
||||
IOPortTag & x"00" & NullTag & x"00", -- I/O 33 PIN 25 PIN 13
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_7I76_7I74D_SS6_34;
|
||||
166
5i24/configs/hostmot2/source/PIN_7I76_7I74_34.vhd
Executable file
166
5i24/configs/hostmot2/source/PIN_7I76_7I74_34.vhd
Executable file
@@ -0,0 +1,166 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_7I76_7I74_34 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(QcountTag, x"02", ClockLowTag, x"01", QcounterAddr&PadT, QCounterNumRegs, x"00", QCounterMPBitMask),
|
||||
(SSerialTag, x"00", ClockLowTag, x"02", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"05", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin -- external DB25
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 00 PIN 1
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 01 PIN 14
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 02 PIN 2
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 03 PIN 15
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 04 PIN 3
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 05 PIN 16
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 06 PIN 4
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 07 PIN 17
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 08 PIN 5
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 09 PIN 6
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 10 PIN 7
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 11 PIN 8
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 12 PIN 9
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 13 PIN 10
|
||||
IOPortTag & x"00" & QCountTag & x"03", -- I/O 14 PIN 11
|
||||
IOPortTag & x"00" & QCountTag & x"02", -- I/O 15 PIN 12
|
||||
IOPortTag & x"00" & QCountTag & x"01", -- I/O 16 PIN 13
|
||||
|
||||
-- 26 HDR -- IDC DB25
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX0Pin, -- I/O 17 PIN 1 PIN 1
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX1Pin, -- I/O 18 PIN 2 PIN 14
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX2Pin, -- I/O 19 PIN 3 PIN 2
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX3Pin, -- I/O 20 PIN 4 PIN 15
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX0Pin, -- I/O 21 PIN 5 PIN 3
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX1Pin, -- I/O 22 PIN 6 PIN 16
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX2Pin, -- I/O 23 PIN 7 PIN 4
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX3Pin, -- I/O 24 PIN 8 PIN 17
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX4Pin, -- I/O 25 PIN 9 PIN 5
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX5Pin, -- I/O 26 PIN 11 PIN 6
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX6Pin, -- I/O 27 PIN 13 PIN 7
|
||||
IOPortTag & x"01" & SSerialTag & SSerialRX7Pin, -- I/O 28 PIN 15 PIN 8
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX4Pin, -- I/O 29 PIN 17 PIN 9
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX5Pin, -- I/O 30 PIN 19 PIN 10
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX6Pin, -- I/O 31 PIN 21 PIN 11
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTX7Pin, -- I/O 32 PIN 23 PIN 12
|
||||
IOPortTag & x"01" & SSerialTag & SSerialTXEn7Pin, -- I/O 33 PIN 25 PIN 13
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_7I76_7I74_34;
|
||||
166
5i24/configs/hostmot2/source/PIN_7I76_7I77D_34.vhd
Executable file
166
5i24/configs/hostmot2/source/PIN_7I76_7I77D_34.vhd
Executable file
@@ -0,0 +1,166 @@
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all; -- defines std_logic types
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
-- Copyright (C) 2007, Peter C. Wallace, Mesa Electronics
|
||||
-- http://www.mesanet.com
|
||||
--
|
||||
-- This program is is licensed under a disjunctive dual license giving you
|
||||
-- the choice of one of the two following sets of free software/open source
|
||||
-- licensing terms:
|
||||
--
|
||||
-- * GNU General Public License (GPL), version 2.0 or later
|
||||
-- * 3-clause BSD License
|
||||
--
|
||||
--
|
||||
-- The GNU GPL License:
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 2 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program; if not, write to the Free Software
|
||||
-- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
--
|
||||
--
|
||||
-- The 3-clause BSD License:
|
||||
--
|
||||
-- Redistribution and use in source and binary forms, with or without
|
||||
-- modification, are permitted provided that the following conditions
|
||||
-- are met:
|
||||
--
|
||||
-- * Redistributions of source code must retain the above copyright
|
||||
-- notice, this list of conditions and the following disclaimer.
|
||||
--
|
||||
-- * Redistributions in binary form must reproduce the above
|
||||
-- copyright notice, this list of conditions and the following
|
||||
-- disclaimer in the documentation and/or other materials
|
||||
-- provided with the distribution.
|
||||
--
|
||||
-- * Neither the name of Mesa Electronics nor the names of its
|
||||
-- contributors may be used to endorse or promote products
|
||||
-- derived from this software without specific prior written
|
||||
-- permission.
|
||||
--
|
||||
--
|
||||
-- Disclaimer:
|
||||
--
|
||||
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
-- COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
-- POSSIBILITY OF SUCH DAMAGE.
|
||||
--
|
||||
|
||||
use work.IDROMConst.all;
|
||||
|
||||
package PIN_7I76_7I77D_34 is
|
||||
constant ModuleID : ModuleIDType :=(
|
||||
(HM2DPLLTag, x"00", ClockLowTag, x"01", HM2DPLLBaseRateAddr&PadT, HM2DPLLNumRegs, x"00", HM2DPLLMPBitMask),
|
||||
(WatchDogTag, x"00", ClockLowTag, x"01", WatchDogTimeAddr&PadT, WatchDogNumRegs, x"00", WatchDogMPBitMask),
|
||||
(IOPortTag, x"00", ClockLowTag, x"02", PortAddr&PadT, IOPortNumRegs, x"00", IOPortMPBitMask),
|
||||
(MuxedQcountTag, MQCRev, ClockLowTag, x"08", MuxedQcounterAddr&PadT, MuxedQCounterNumRegs,x"00", MuxedQCounterMPBitMask),
|
||||
(MuxedQCountSelTag, x"00", ClockLowTag, x"01", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(SSerialTag, x"00", ClockLowTag, x"01", SSerialCommandAddr&PadT, SSerialNumRegs, x"10", SSerialMPBitMask),
|
||||
(StepGenTag, x"02", ClockLowTag, x"05", StepGenRateAddr&PadT, StepGenNumRegs, x"00", StepGenMPBitMask),
|
||||
(LEDTag, x"00", ClockLowTag, x"01", LEDAddr&PadT, LEDNumRegs, x"00", LEDMPBitMask),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000"),
|
||||
(NullTag, x"00", NullTag, x"00", NullAddr&PadT, x"00", x"00", x"00000000")
|
||||
);
|
||||
|
||||
|
||||
constant PinDesc : PinDescType :=(
|
||||
-- Base func sec unit sec func sec pin -- P3 DB25
|
||||
|
||||
IOPortTag & x"00" & StepGenTag & StepGenDirPin, -- I/O 0 PIN 1
|
||||
IOPortTag & x"00" & StepGenTag & StepGenStepPin, -- I/O 1 PIN 14
|
||||
IOPortTag & x"01" & StepGenTag & StepGenDirPin, -- I/O 2 PIN 2
|
||||
IOPortTag & x"01" & StepGenTag & StepGenStepPin, -- I/O 3 PIN 15
|
||||
IOPortTag & x"02" & StepGenTag & StepGenDirPin, -- I/O 4 PIN 3
|
||||
IOPortTag & x"02" & StepGenTag & StepGenStepPin, -- I/O 5 PIN 16
|
||||
IOPortTag & x"03" & StepGenTag & StepGenDirPin, -- I/O 6 PIN 4
|
||||
IOPortTag & x"03" & StepGenTag & StepGenStepPin, -- I/O 7 PIN 17
|
||||
IOPortTag & x"04" & StepGenTag & StepGenDirPin, -- I/O 8 PIN 5
|
||||
IOPortTag & x"04" & StepGenTag & StepGenStepPin, -- I/O 9 PIN 6
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX0Pin, -- I/O 10 PIN 7
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX0Pin, -- I/O 11 PIN 8
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX1Pin, -- I/O 12 PIN 9
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX1Pin, -- I/O 13 PIN 10
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 14 PIN 11
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 15 PIN 12
|
||||
IOPortTag & x"03" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 16 PIN 13
|
||||
-- P2 26 HDR DB25
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTXEN4Pin, -- I/O 17 PIN 1 PIN 1
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX4Pin, -- I/O 18 PIN 2 PIN 14
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX4Pin, -- I/O 19 PIN 3 PIN 2
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX3Pin, -- I/O 20 PIN 4 PIN 15
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX3Pin, -- I/O 21 PIN 5 PIN 3
|
||||
IOPortTag & x"00" & SSerialTag & SSerialTX2Pin, -- I/O 22 PIN 6 PIN 16
|
||||
IOPortTag & x"00" & SSerialTag & SSerialRX2Pin, -- I/O 23 PIN 7 PIN 4
|
||||
IOPortTag & x"00" & MuxedQCountSelTag & MuxedQCountSel0Pin, -- I/O 24 PIN 8 PIN 17
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 25 PIN 9 PIN 5
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 26 PIN 11 PIN 6
|
||||
IOPortTag & x"00" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 27 PIN 13 PIN 7
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 28 PIN 15 PIN 8
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 29 PIN 17 PIN 9
|
||||
IOPortTag & x"01" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 30 PIN 19 PIN 10
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQAPin, -- I/O 31 PIN 21 PIN 11
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountQBPin, -- I/O 32 PIN 23 PIN 12
|
||||
IOPortTag & x"02" & MuxedQCountTag & MuxedQCountIDXPin, -- I/O 33 PIN 25 PIN 13
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for 34 pin 5I25
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin, -- added for IDROM v3
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,
|
||||
emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin,emptypin);
|
||||
|
||||
end package PIN_7I76_7I77D_34;
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user